Investigation of Plasma Enhanced Chemical Vapor Deposition Chamber Mismatching by Photoluminescence and Raman Spectroscopy

Slight differences between supposedly identical process chambers are a well known problem in semiconductor manufacturing. In particular, individual plasma-aided process chambers are difﬁcult to characterize and tune to match each other because plasma is a non-equilibrium state and can leave its “footprint” in subtle ways on a wafer. This process chamber mismatching phenomena was investigated in a dual chamber, commercial, high density plasma chemical vapor deposition system by monitoring SiO 2 /Si interface quality using multiwavelength room temperature photoluminescence and Raman spectroscopy. Effects on the SiO 2 /Si interface quality, from altering the gas ﬂow pattern in the plasma process chamber, are also studied.

Multiple processing systems are used for a single task in large scale Si semiconductor device manufacturing facilities. A processing system often consists of more than one process chamber. Sometimes the identical task may even be performed in process chambers from different equipment suppliers. Even if the process chambers are from the same equipment supplier and supposedly identical, we often experience difficulty in matching the process results after a lot of process tuning effort. 1-3 Process tuning is typically done by matching physical dimensions and apparent physical properties of processed materials on Si wafers (for example; deposition, etching, bulk and surface treatment, annealing etc.). [4][5][6][7][8][9][10][11] In some cases, problematic process chambers cannot be commissioned for device manufacturing, even after process tuning due to unexplained device performance variations of wafers processed in them for undiscovered reasons. 2,3,12 It takes several iterations of device fabrication and test cycles to figure this out. It can easily take several months and significant resources. [7][8][9] Process chamber mismatching problems are more prone to processes in which plasma takes an active role. 7,[10][11][12] Since plasma itself is a non-equilibrium state, with many variables (such as pressure, gas flow pattern, r. f. frequency, r. f. power, electrode configurations, d. c. bias, impedance, wafer temperature, chamber seasoning, etc.), it is difficult to characterize a plasma state and match the process results perfectly. 4-7,10-12 Electrical performance variations of final devices processed in different process chambers generally determines whether a particular process chamber can be commissioned for device manufacturing, or not. 2,3,12 If we can detect the potential mismatching problems in a process chamber at an early stage and without going through the lengthy device fabrication and test cycles, it would greatly reduce cost and perhaps shorten the process tuning cycle.
For these reasons, gathering large amounts of data, and data mining to extract and analyze useful information, are getting increasingly more important to solve challenging problems which impact yield. 1,4,7,12 Unfortunately, the number of published studies in this area is very small because it naturally contains very sensitive information such as trade secrets, technical competence and business competitiveness. Very valuable and critical information is often kept internally, rather than made open to the public.
In this study, SiO 2 films deposited using a commercial, dual chamber, high density plasma chemical vapor deposition (HDP-CVD) system with mismatched process chambers (one disqualified process chamber and one qualified process chamber, determined by device electrical performance and yield tests) were investigated by non-contact, optical characterization techniques, to gain insights into subtle differences (hidden variables) which specific diagnostic metrology evaluation of the SiO 2 films and/or SiO 2 /Si interface might reveal. The thickness and optical properties of the SiO 2 were measured as essentially identical using conventional measurement techniques. Multiwavelength, room temperature photoluminescence (RTPL) and Raman spectroscopy were then used to characterize SiO 2 /Si interface quality and stress of the Si beneath the SiO 2 layers. The SiO 2 films were grown under identical control process variables, but, not necessarily identical (chamber) process conditions. Effects of gas flow pattern changes in the qualified HDP-CVD chamber on SiO 2 films and SiO 2 /Si interfaces were also investigated.

Experimental
Thin (6 nm thick) SiO 2 films were thermally grown on 300 mm p − -Si(100) wafers in a commercial vertical batch furnace. The thickness of Si wafers was 775 μm. The thermal SiO 2 /Si wafers were used as the optical characterization reference material for the purpose of investigating and characterizing HDP-CVD chamber mismatching using controlled starting materials. Details of the HDP-CVD system can be found in Ref. 13. Plasma SiO 2 films with a target thickness of ∼580 nm were deposited on top of thermally grown 6 nm-thick SiO 2 /Si wafers in a commercially available HDP-CVD system using SiH 4 and O 2 as source gases. The wafer temperature and chamber pressure were maintained at ∼350 • C and ∼5 mTorr for both (disqualified) Chamber A and (qualified) Chamber B process chambers, respectively. Two gas flow patterns (high and low gas flow ratios of chamber center nozzles to chamber edge nozzles) were tested in the qualified process chamber to see the effect of gas flow patterns on the oxide film thickness and oxide quality distribution. Figure 1 shows UV-VIS-NIR reflectance spectra, in the wavelength range of 200 ∼ 1100 nm, from a bare Si wafer with native oxide, a thermally grown 6 nm-thick SiO 2 /Si reference wafer and three ∼580 nm-thick HDP-CVD SiO 2 films grown on 6 nm-thick SiO 2 /Si wafers. The 6 nm-thick SiO 2 /Si wafer showed similar reflectance spectra to the bare Si wafer with a native oxide layer. They showed two distinct peaks at ∼280 nm and ∼360 nm corresponding to E 1 (∼3.4 eV) and E 2 (∼4.2 eV), the energy separation characteristic of Si. Due to the ultra thin layers of native oxide (∼1 nm) and thermal oxide (∼6 nm), very small interference on the reflectance spectra were observed. The wafers with ∼580 nm thick HDP-CVD oxide films showed numerous interference fringes corresponding to the thickness and refractive index (RI) of oxide films. From just the oxide thickness and RI   Figure 1. Reflectance spectra of blanket Si wafers with native oxide, 6 nm thick low temperature thermal oxide and 6 nm thick thermal oxide + 580 nm thick HDP-CVD oxide deposited in different process chambers and gas flow patterns.

Results and Discussion
measurements of the HDP-CVD oxide films on Si, the disqualified and qualified chambers were nearly identical. No noticeable differences were observed. Similarly, from a device performance perspective, the differences between wafers processed in the disqualified process chamber and qualified chamber are not detectable from film thickness and RI measurements of blanket Si wafers processed under the identical process conditions. Other physical characteristics of the SiO 2 /Si seemed to be responsible for the difference in device performance of wafers processed in the disqualified and qualified process chambers.
To gain further insights into the physical properties of SiO 2 /Si structures prepared in different process chambers, and with various gas flow patterns in the same process chamber, multiwavelength RTPL and Raman characterizations were performed on the thermally grown 6 nm-thick SiO 2 /Si reference wafer and three ∼580 nm-thick HDP-CVD SiO 2 films grown on 6 nm-thick SiO 2 /Si wafers.
It is well known that RTPL of crystalline Si at wavelengths near band edge of Si (∼1.1 μm) is very sensitive to the density of nonradiative bulk and surface defects. 14,15 Most RTPL studies on Si measure RTPL intensity centered at ∼1.1 μm using a photodiode, without measuring actual RTPL spectra. No spectral information is available to separate the asymmetric band-to-band transition RTPL peak centered ∼1140 nm and a small band tail RTPL peak extended to ∼1270 nm, which is sensitive to the Si lattice damage. Multiwavelength spectroscopic RTPL is useful in understanding defects in silicon and electronic property changes (such as band bending) at the dielectrics/Si interface, which would be missed by a single wavelength measurement.
RTPL spectra were measured from the thermal SiO 2 /Si and HDP-CVD SiO 2 /Si wafers under two excitation wavelengths (650 and 827 nm). The spectroscopic RTPL system (WaferMasters' MPL-300 system) is described elsewhere. [16][17][18][19][20][21][22][23] Multiwavelength, spectroscopic RTPL mapping was done at 15,101 points in 2 mm intervals in x-and y-directions. The penetration depths for the RTPL excitation wavelengths of 650 and 827 nm were ∼4.0 μm and ∼10 μm, respectively. The excitation laser beam was focused at the wafer surface with diameter in the range of 50 ∼ 100 μm. Since the electronic properties, including electronic carrier lifetime and radiative recombination (photoluminescence: PL) probability, are strongly influenced by the SiO 2 /Si interface quality, the presence of Si lattice damage (possibly by plasma process induced damage (PPID)) and charges (ions and traps) in SiO 2 can significantly impact RTPL spectra/intensity, as well as the electrical properties of SiO 2 /Si in device wafers. In this study, due to the non-contact nature of the spectroscopic RTPL technique, it is used as a technique for early determination of the potential acceptability of electrical performance of devices, without using physical electrodes.
Micro-Raman wafer mapping of the SiO 2 /Si wafers was performed under three excitation wavelengths (457.9, 488.0 and 514.5 nm) in the visible wavelength range to investigate Si lattice stress from the SiO 2 /Si interface in the depth direction. Multiwavelength micro-Raman system (MRS-300) is described elsewhere. [16][17][18]21,[23][24][25] The focused laser beam diameter at the wafer surface was in the range of ∼1 μm. The Raman probing depths in Si for 457.9, 488.0 and 514.5 nm laser beam are ∼290 nm, ∼490 nm and ∼645 nm, respectively. [23][24][25] Weighted average stress of Si from the SiO 2 /Si interface, over the Raman probing depths, can be measured at a given excitation wavelength. [23][24][25] By measuring the Raman signal from Si under different excitation wavelengths, Si lattice stress under the SiO 2 and its distribution into bulk Si can be evaluated. Figure 2 summarizes the SiO 2 film thickness, calculated from ellipsometry measurements, using an He-Ne laser (633 nm), RTPL wafer maps and RTPL line scan results, under 650 and 827 nm excitation, in the Y-direction from the wafer notch. The RTPL spectra line scans in the wavelength range of 900 ∼ 1400 nm were plotted in the Y-direction from the wafer notch. Ellipsometry measurements were done for all wafers at 225 points with 10 mm edge exclusion. The average film thickness and uniformity of the reference thermal SiO 2 /Si wafer were 5.5 nm and 6.3% in 1σ. The average thickness (and uniformity) of three HDP-CVD SiO 2 films were calculated to be 582.8 nm (0.96%), 584.6 nm (1.95%) and 588.2 nm (1.37%), in order, from Chamber A (high gas flow ratio at the center), Chamber B-1 (high gas flow ratio at the center) and Chamber B-2 (low gas flow ratio at the center). From a thickness uniformity point of view, HDP-CVD Chamber A (the disqualified chamber) gave better results than the SiO 2 deposition conditions (B-1 and B-2) of the qualified chamber.
RTPL intensity of the ∼6 nm-thick thermal SiO 2 /Si reference wafer showed very low counts (∼5,000 counts at 650 nm excitation and ∼10,000 counts at 827 nm). The RTPL line scans show very uniform intensity/spectra across the wafer, under both excitation wavelengths, indicating homogeneous SiO 2 /Si interface quality. RTPL spectral distributions were almost identical across the wafer. No noticeable RTPL spectral distribution change, due to the significant localized lattice damage, was observed across the wafer. Since the RTPL spectral distributions are alike at all measurement points, it is safe to simply compare the RTPL intensity between HDP-CVD SiO 2 /Si wafers measured in this study. All HDP-CVD SiO 2 /Si wafers showed very intense (5 ∼ 8 times stronger) RTPL signals compared to the reference SiO 2 /Si wafer with ∼6 nm thick thermal oxide. However, the RTPL line scans in the Y-direction showed ∼30% variation in the RTPL intensity range.
In general, RTPL intensity was higher at the wafer center and lower near the wafer edge. The HDP-CVD SiO 2 /Si deposited in the disqualified chamber (Chamber A, with high gas flow ratio of chamber center nozzles to chamber edge nozzles) showed ∼20% lower RTPL intensity compared to the wafers processed in qualified chamber (Chamber B with high (B-1) and low (B-2) gas flow ratios of chamber center nozzles to chamber edge nozzles). Two RTPL intensity dips, near −45 and −35 mm, in the Y-direction from the wafer center are due to the end effector marks of the HDP-CVD system from the wafer back side. Electrically active defects generated on the wafer back side by end effector contact are responsible for localized drops in RTPL intensity. Since Chamber A and Chamber B are attached to the same wafer transfer module, the end effector marks appear as mirror images to each other. The mean free path of free carriers in high quality Si can easily exceed 1 mm (larger than the thickness of a Si wafer) and PL signal intensity is very sensitive to band bending at the SiO 2 /Si interface, residual damage in Si (especially residual damage within the probing depths) and wafer back side interface quality variations, even though the RTPL probing depths are up to ∼10 μm from the SiO 2 /Si interface.
The RTPL intensity Y-line scan trends, for the same high gas flow ratio of chamber center to chamber edge nozzles, for the disqualified chamber (Chamber A) and qualified chamber (Chamber B-1) were very similar, other than for the RTPL intensity itself. The gas flow ratio is often varied to adjust within wafer distribution of electrical properties of devices without having good understanding of its physical impact. It is considered "a knob" for process tuning. Since most process and material monitoring and/or characterization techniques (such as thickness measurement, refractive index measurement and film stress measurements through wafer bow measurements) are not as meaningful or sensitive enough to the electrical properties of devices. In practice, these time consuming trial-and-error approaches are wastefully repeated on device wafers. Good process and material monitoring and/or characterization techniques, which are sensitive enough to the electrical properties of devices processed under the same conditions, have long been desired to save valuable device wafers. The RTPL line scan results of the Chamber B-1 and Chamber B-2 in the Y-direction show the correlation between the change of RTPL intensity patterns and the change of gas flow ratios of chamber center to the chamber edge nozzles. The change of SiO 2 film thickness maps due to changes of the gas flow ratio showed almost no correlation with the change of RTPL intensity maps. The changes in the SiO 2 film thickness map does not, to first order, reflect the changes seen in the RTPL intensity map. This strongly suggests that the way the source gases are supplied to the HDP-CVD process chamber can affect the electrical properties of SiO 2 /Si interface and possibly the electrical properties of devices.
Previous RTPL studies on PPID on Si wafers that underwent plasma etching (PE) of an SiO 2 layer and plasma enhanced chemical deposition (PECVD) of SiO 2 showed significant drops in RTPL intensities where PPID is present on the Si wafers. 16 Other RTPL studies also showed significant drops in RTPL intensities in SiO 2 /Si with UV exposure during routine optical characterization and ionic charge exposure in air during Corona charge-based, non-contact electrical (I-V and C-V) characterization. 19 All of these left permanent damage to the Si lattice and/or SiO 2 /Si integrity which can impact electrical properties. Portions of the damage were recovered after annealing in forming gas (96% N 2 + 4% H 2 ). Multiwavelength RTPL intensity measurements of SiO 2 /Si wafers showed very promising features as a non-contact optical characterization technique for probing electrical properties of dielectric/Si structures. [16][17][18][19][20][21][22][23] The chamber-to-chamber RTPL intensity comparisons between the qualified chamber (Chamber B-1) and disqualified chamber (Chamber A) showed ∼20% reduction. The gas flow pattern change within the qualified chamber (Chamber B-1 and B-2) showed how gas flow impacts SiO 2 thickness distribution and RTPL intensity distribution on Si wafers. The increase of gas flow from the chamber edge nozzles (Chamber B-2) resulted in ∼10% drop in RTPL intensity at wafer edge, while the RTPL intensity at wafer center stayed the same. The change in RTPL intensity distribution on Si wafers (Chamber B-1 and B-2) resembles the change of typical yield patterns on device wafers processed under the same gas flow patterns in the qualified chamber (Chamber B). The RTPL intensity, and its intensity ratio, can be used as an indicator and signal for evaluating HDP-CVD process chambers as seen in Figs. 3 and 4.
To investigate possible changes in Si lattice stress under various process conditions, multiwavelength Raman wafer mapping measurements were done at 93 points on all wafers. Figure 5 shows the average Raman shift, full-width-at-half-maximum (FWHM) of Raman peak and Raman peak intensity of all wafers under three excitation wavelengths (457.9, 488.0 and 514.5 nm). The reference Si wafer, with native oxide, showed a Raman peak at 520.    depths of 290 ∼ 645 nm, were in the compressive stress range of -30.7 ∼ -37.5 MPa. The highest compressive stress was measured under 457.9 nm excitation indicating effect from very near the SiO 2 /Si interface. The resolution and repeatability of Raman measurements after curve fitting are 0.01 cm −1 and 0.05 cm −1 , respectively. All ∼580 nmthick HDP-CVD SiO 2 /Si wafers showed slightly higher compressive stress values. The HDP-CVD SiO 2 /Si wafer deposited in the disqualified chamber (Chamber A) showed the lowest compressive Si lattice stress compared to the other HDP-CVD SiO 2 /Si wafers processed in the qualified chamber (Chamber B). It also showed a significant drop in Si lattice stress, as the probing depths of Raman measurements increased from ∼290 nm to ∼490 nm (from 457.9 nm to 488.0 nm excitation). Relatively steep compressive Si lattice stress drop in the depth direction is present. The two HDP-CVD SiO 2 /Si wafers deposited in the qualified chamber (Chamber B) showed slightly higher compressive stress of −51.7∼−52.1 MPa and the gradual release of compressive Si lattice stress in the depth direction, regardless of the alteration of the gas flow ratio of the center nozzles to the edge nozzles. This Si lattice stress value, and its change in the depth direction beneath the HDP-CVD SiO 2 layer, seemed to be correlated to the RTPL intensity difference in the HDP-CVD SiO 2 /Si wafers deposited in the different plasma process chambers.
Raman FWHM values are very similar, within measurement errors, for all SiO 2 /Si wafers, including the 6 nm-thick thermally grown SiO 2 /Si wafer. The variations of FWHM under different excitation wavelengths were close to the limit of the wavelength (or frequency) coherency of the Ar + laser of micro-Raman system. Raman intensity of the 6 nm-thick thermally grown SiO 2 /Si wafer was relatively weak under all excitation wavelengths due to the negligible interference from the 6 nm-thick SiO 2 layer (Fig. 1)  to the lower reflectance for 580 nm-thick HDP-CVD SiO 2 /Si at that wavelength (Fig. 1).
The device issues related to carrier recombination and stress effects are in the Si region. PPID in the Si region and distribution of residual electrical charges in HDP-CVD oxide films can strongly affect carrier recombination rates and band bending at the SiO 2 /Si interface. The area of weak RTPL intensity of the disqualified chamber (Chamber A) generally showed a higher threshold voltage (V th ) shift than did the surrounding areas and strongly affected device yield. The RTPL intensity maps of HDP-CVD SiO 2 /Si, from the disqualified chamber, showed good correlation with device yield-loss maps.

Summary
In summary, process chamber mismatching phenomena was investigated in a dual chamber, commercial, HDP-CVD system by monitoring SiO 2 /Si interface quality using multiwavelength RTPL and Raman spectroscopy. Different HDP-CVD SiO 2 /Si electrical properties, obtained from supposedly identical process chambers, were investigated. Effects on the SiO 2 /Si interface quality, from altering the gas flow pattern in the plasma process chamber, were also studied. Multiwavelength Raman characterization of Si lattice stress beneath the SiO 2 layer, and its change in the depth direction, can provide very valuable insights into the state of the Si, which cannot be accessed from typical routine monitoring of thickness and optical properties of SiO 2 films after deposition. Multiwavelength RTPL measurements also provide the effect of SiO 2 film deposition techniques and conditions on electrical integrity of the SiO 2 /Si structure. New characterization techniques such as multiwavelength RTPL and Raman spectroscopy can provide additional insights into the root cause of the "mysterious" process chamber mismatching problems which causes significant shortfalls in semiconductor manufacturing. The use of multiwavelength RTPL and Raman spectroscopy can provide very valuable inputs on process chamber behaviors on processed wafers for process chamber qualification/disqualification and guide process chamber tuning without going through lengthy device fabrication and test cycles. This will greatly shorten the process chamber qualification/disqualification.