Abstract
Experimental results of strained Si nanowire (NW) TFETs with tri-gate and gate all around (GAA) configurations are presented. Steep tunneling junctions formed by ion implantation into silicide (IIS) and low temperature annealing for dopant segregation allow to achieve subthreshold slope SS<60mV/dec. Improvement of the electrostatics by using GAA and smaller nanowires enhances the tunneling currents, lowers SS and lessens trap assisted tunneling (TAT). Pulsed I-V measurements demonstrate that suppression of TAT is the key to achieve steeper SS over a large range of drain currents. We also show that complementary TFET inverters and p-logic NAND gates can be operated at VDD=0.2V, demonstrating the great potential of TFETs for ultra-low power application.