Abstract
A pass gate (PG) configured with a configuration memory (CM) composed of a c-axis aligned crystalline In-Ga-Zn-O (CAAC-IGZO) FET and a pass transistor composed of an NMOS FET is applied to a multi-context routing switch (MC-RS) of a dynamically reconfigurable programmable logic device (DRPLD) based on multi-context architecture (MC-DRPLD). The proposed PG (OS PG) requires fewer transistors than a conventional PG configured with an SRAM cell served as a CM (SRAM PG). A MC-RS configured with the OS PG (OS MC-RS) has enabled its layout area to be 40% less than that of a MC-RS configured with the SRAM PG (SRAM MC-RS). Further, the delays of the MC-RSs with 2 to 16 contexts have been reduced by 24% to 37%. The MC-DRPLD including the OS MC-RS can switch contexts in one clock (50 nsec) at a clock frequency of 20 MHz, which enables dynamic reconfiguration at high speed.