Ternary Łukasiewicz logic using memristive devices

Memristive devices based on the Valence Change Mechanism (VCM) are promising devices for storage class memory, neuromorphic computing and logic-in-memory (LIM) applications. They are suited for such a wide range of applications, due to their possibility for extreme dense integration, low power consumption and multilevel capabilities. Through LIM concepts, Boolean logic operations can be performed directly in memory. In many of these concepts, the resistance state of the device is interpreted as the logical input and output of the logic function, which is why these concepts are called ‘stateful’ logic. Most of the proposed ideas, however, are defined based on only binary switching VCM devices and neglect their multi-level capabilities. Extending LIM concepts towards multinary logic, e.g. a ternary logic, would increase the data density inside the memory array and reduce the number of devices required to perform a certain operation. In this work, we discuss two possibilities of realizing a ternary logic based on the analog switching in the RESET or in the SET direction. For both directions we verify the logic functionality by showing the basic operations of implication, negation and false operation, which together form a functionally complete logic. Additionally, for both switching directions, we discuss a 41-Trit ( ≈ 64-Bit) addition. For all investigations the physics-based compact model JART VCM v1b is used, which has been verified on the RESET direction multilevel properties of the TaO x devices.


Introduction
Bipolar and filamentary switching memristive devices based on the Valence Change Mechanism (VCM) [1] are a heavily researched class of devices, due to their potential applications, ranging from non-volatile storage class memories, over neuromorphic computing and also logic-in-memory (LIM) concepts [2,3].These devices store their information state, in the form of a configuration of oxygen defects, as a resistive state.Through the application of a suitable voltage pulse, the VCM devices can change the resistive state between a high resistive state (HRS) and a low resistive state (LRS).This resistance change is non-volatile and abrupt in the SET direction, while more gradual in the RESET direction [4].Gradual switching can be achieved in the SET direction, by limiting the maximum current.In the RESET direction multiple distinct resistance levels can be realized through a variation of the maximum RESET voltage amplitude.In recent years, many Boolean logic gates and larger arithmetic circuits, such as adders and multipliers, were proposed based on binary switching VCM devices [5][6][7][8][9][10][11][12][13][14][15][16][17][18].Via these concepts, computation and data storage can be performed in the same physical location, which avoids costly data transfer between Central Processing Unit (CPU) and the main memory.The reduction in data movement is seen as one of the main opportunities towards efficiency improvements in today's computing systems, as they are, for some applications, rather bound by the memory bandwidth than by the performance of the CPU [2,19].
However, as most of the VCM based logic concepts are only considering binary switching devices, they do not fully utilize the potential of the VCM devices.Multilevel capabilities of VCM cells are well established [20][21][22][23], requiring extended, multinary LIM concepts that can inherently deal with more than two resistance states.So far, only a few multinary LIM concepts were proposed, such as a ternary adder concept by Fey et al [24,25] or a fuzzy logic by Serb et al [26].In addition, a ternary Łukasiewicz (Ł 3 ) logic concept and a ternary adder concept have been experimentally demonstrated [27,28].In this work, we demonstrate a ternary Łukasiewicz logic concept (Ł3), exploiting the analog switching properties of bipolar and filamentary switching VCM cells in the SET and RESET direction.The logic concept itself is based on applying the logical inputs as voltages to a VCM cell and interpreting the resulting resistance as the logical output.It can be executed in either the SET direction or the RESET direction.In the RESET direction, the concept is based on modifying the maximum RESET voltage to program different HRS.In this direction, the single VCM devices can be combined with a passive selector element [29], allowing for ultra dense 1S1R arrays, that only require 4 F 2 per device, where F is the minimum achievable feature size.The selector element is required, as in 1 R arrays the programming of single VCM elements disturbs the resistance states of neighboring cells [30].Additionally, 1 R crossbar arrays suffer from the sneak path issue [31].In the SET direction, the logic concept is based on modifying the current compliance of a transistor connected in series with the VCM cell to program different LRS.Therefore, for both SET and RESET direction, the logical inputs have to be converted into appropriate voltage levels to provide distinguishable HRS or LRS.As transistors are required for the correct logic operation in the SET direction, the required area per element is higher than in the RESET direction (>8 F 2 per 1T1R cell [32]).They also act as selector for the VCM cells, suppressing write disturb and sneak-paths.
The rest of this paper is structured as follows.In section 2 the simulation models of the VCM device, the selector and the transistor are introduced and the programming scheme to achieve multilevel programming is presented.Section 3 provides detailed information on the voltage application schemes, required to perform the basic logic gates in RESET and SET direction.Section 4 explains, how an array level addition can be performed, again for the RESET and SET case.Section 5 discusses and compares the trade-offs of both approaches and section 6 concludes the paper.

Simulation model and framework
The VCM stack to which the compact model was fitted in this paper, as well as its fabrication and measurement procedure are described in [21,33].It consists of a 30 nm thick active Pt bottom electrode as the active electrode (AE), the active switching layer of 7 nm thick Ta 2 O 5 and a 13 nm thick W top electrode as the ohmic electrode (OE) as demonstrated in figure 1(a).To prevent W oxidation at the ambient air, a 25 nm Pt capping layer is added.The stack is structured as 5 µm × 5 µm crossbar devices.These devices are filamentary switching VCM cells, whose switching mechanism is based on the modulation of the number of oxygen defects close to the AE.In this work, the deterministic JART VCM v1b model [34][35][36][37], with the parameter set from table 1, is used for the simulations.
The equivalent circuit diagram (ECD) of this model is shown in figure 1(a) in the orientation in which it is fabricated.In the model, the concentration of oxygen defects (i.e.oxygen vacancies) close to the AE interface is called N disc and represents the state variable of the system.A high N disc value represents a LRS and a low N disc value represents a HRS.For these devices, an abrupt transition from the HRS to the LRS (SET operation) occurs, when a sufficiently high or long negative voltage is applied to the AE.At a high enough positive voltage, the device shows a gradual RESET transition from the LRS to the HRS [33,38].These properties are typical for filamentary bipolar switching VCM devices [1].Due to the gradual nature of the RESET switching, it can be directly exploited for multilevel programming.The SET switching on the other hand has to be limited via external means, such as a current compliance provided by a series transistor.The voltage across the VCM cell is given as where AE denotes the AE and OE denotes the OE.(e) and (f) highlight the different ways of multilevel programming for filamentary VCM cells in SET (e) and RESET (f) direction.In (e) the cell initially is in the HRS.First a SET sweep of 1 ms is applied in which the voltage at the AE is increased from 0 V to −2 V and back to 0 V with different limitations on the maximum current of −300 µA (blue line), −600 µA (red curve) and −900 µA (yellow curve).As can be expected, higher current compliance lead to smaller LRS.After the  SET direction sweep, a RESET direction sweep is applied in which the voltage at the AE is increased from 0 V to 1.5 V and back to 0 V in 1 ms.Depending on the LRS state the RESET is more gradual (for small current compliances) or more abrupt (for larger current compliances).The transition from gradual to more abrupt RESET can be explained from the change of the voltage divider between device resistance and internal series resistance [4,35].In (f) the cell is initialized in the LRS and first RESET sweeps are applied with different maximum voltages.The voltage is swept from 0 V to 1 V (blue curve), 1.2 V (red curve) and 1.4 V (yellow curve) in 1 ms.Higher RESET voltages lead to higher HRS.After the different RESET direction sweeps, the voltage is swept from 0 V to −2 V and back to 0 V in 1 ms.Higher HRS lead to an increase of the SET voltage [35].
The programming behavior in the RESET direction has been characterized experimentally in [21,33].These measurements are fitted using the deterministic compact model JART VCM v1b using the parameter set shown in table 1.In this parameter set, R th is chosen the same for SET and RESET and the temperature-dependent series resistance of the lines is neglected as it is very small for a µm-sized device.The RESET direction programming uses a controlled SET pulse for the initialization of the devices in the LRS.The multilevel programming is then achieved via RESET pulses at different amplitudes.All SET and RESET pulses have rise and fall times of 50 ns and hold times of 150 ns.The SET pulse has an amplitude of V Device = −2 V and always results in the LRS shown in table 3.In [37], it was shown that the model can fit the experimental behavior for all experimentally observed resistance states (R 0 to R 5 ), which are programmed with voltages between 1.5 V and 2.25 V with a spacing of 0.15 V.The ternary logic gates only require three resistance states.For that purpose, the LRS, R 0 and R 1 are chosen.Originally, all six resistance states were required for the ternary adder concept as demonstrated in [28].However, as we have simplified the addition procedure for this paper, we now only require R 0 , R 1 and R 2 .The different resistances states, as well as the voltage pulses used to program them, are color encoded consistently throughout this manuscript in the following way.The LRS is petrol colored, R 0 is light blue, R 1 is dark green and R 2 is light green.
The selector model that was used in this paper, is based on Pt/TaO x /TiO 2 /TaO x /Pt devices with a bidirectionally symmetric nonlinear I − V characteristic.The selector is modeled according to equations (2)-( 5) and it is fitted to the I − V data shown in [29].Here, A selector denotes the area of the selector, R s,A the series resistance per unit area, R p,A the parallel resistance per unit area, C p,A the parallel capacitance per unit area, j 0 the current density, V 0 the threshold voltage and the exponent α determines the slope of the characteristic.The parameter list is shown in table 2. Through its nonlinearity it prevents the half selected devices in neighboring Source-and Bitlines from switching With the same parameter set the abrupt transition from the HRS to the LRS can be exploited for implementing the logic operation as well.In this scenario, an extra NMOS-transistor was connected in series (e) shows a simulation of the multi level switching in the SET direction by using different current compliances (−300 µA, −600 µA and −900 µA) and (f) shows multi level switching in the RESET direction for the by using different maximum RESET voltages (1 V, 1.2 V and 1.4 V increments).For (e) and (f) the simulations are based on a single VCM cell.
Table 2. Deterministic model parameters fitted to the selector from [29].

Symbol
Value Symbol Value to the memristive device (1T1R structure), serving as a current limiter.The applied model for the transistor is the Predictive Technology Model (PTM) 45 nm BSIM4 for bulk CMOS with parameter set w = 1.35 µm, l = 135 nm.In simulation, the VCM device was set to the HRS in the initialization step with a 100 ns long 3 V RESET voltage pulse with 5 ns long rise/fall time, with full opening of the transistor.To keep the same form of the stimuli, the rise/fall time stays the same in all steps and the pulse length is kept as 100 ns.After initialization the device will be programmed to lower resistive states with a 4 V SET voltage along with variable voltage V gs drop between the gate and source of the transistor.In the end, the state of the device was measured with a 100 mV read out voltage pulse and a 500 mV V gs on the transistor.The simulated results during the SET process as shown in figure 2 are color encoded as follows: LRS is red, MRS is orange and HRS is blue.To avoid misunderstanding, the resistances after initialization are directly read out for comparing with the read out resistances after the SET process.As shown in figure 2(a), the read out resistance is larger than the ones after set processing.For simplification the read out steps after initialization will not be shown in the following sections.

Łukasiewicz logic and basic logic gates
In 1917, Łukasiewicz presented a ternary logic system, using the implication (→) and the negation (¬) as basic operands [39].In this section, we will explain how implication and negation can be mapped and performed in the RESET and in the SET direction.For binary logic, implication and false form a functionally complete logic set.In a multinary logic, such as the ternary logic in this paper, the negation operation is also required.The negation and implication operation will be demonstrated in the next subsections.The compute the false operation the device is programmed to the maximum resistance value for the RESET direction logic and the minimum resistance value for the SET direction logic.In this type of logic, the inputs are applied as different voltages and the results are stored in the resistance state of a single VCM cell.Regarding our proposed logic scheme the ternary logic system by Łukasiewicz has an advantage over other ternary logic concepts such as the one introduced by Kleene for example.This advantage lies in the fact that the truth table of the implication operation from Łukasiewicz (as shown in figure 4(c) and table 6) has the same resistance states (and therefore the same logical level) on the diagonals of the truth table which is not the case for the implication as defined by Kleene [40].In our voltage mapping schemes we also achieve the same voltage levels on the same diagonals.

Implication and negation in the RESET direction
Table 3 shows the different resistance states required for the RESET direction Łukasiewicz logic simulated in the 1 R structure.The resistance values and states of the adder in the 1S1R structure are shown in table 7.For the ternary logic, only the states LRS, R 0 and R 1 are required, while the adder requires one more state R 2 .
Next to the experimental resistance values, the simulated values are shown that result from the fitted JART VCM model v1b [34].Additionally, the assignment of resistances to logic states and their mapping to voltage levels as well as the required total device voltages is shown.Implication and negation consist of three steps each, first an initialization into the LRS, second the application of the voltages according to the different mapping schemes for implication and negation and third a read out of the device state.
Table 3. Measured and simulated resistance states and their assignment in the RESET direction Łukasiewicz logic using the 1 R structure.

Negation
The result of the negation operation of p, which is ¬p, depends on the initial state of the cell.While an initial resistance level R 0 (logical state 1) is mapped unto itself, the resistance level LRS (logical state 0) is mapped to R 1 (logical state 2) and vice versa, R 1 is mapped to the LRS.The negation is shown in figure 3. (a) shows the voltages applied at the AE as differently colored solid lines and the OE voltage is shown as dashed black line.In (b) the resistance transients are shown that are calculated based on the values of the state variable N disc .
For that purpose, the cell is first initialized into the LRS by applying −1 V at the AE and 1 V at the OE, V logic is chosen according to table 3 and V offset is chosen as 1.5 V (corresponding to the required V device for the resistance state which is mapped to the logic state 1).Half of V offset is applied at the AE and half is applied negated at the OE.After the initialization, V device = V offset + V p is applied.In the last step the result is read out by applying −0.1 V. From the colors we can see that the in the case of p = 2 the resistance is actually larger than the nominal LRS resistance due to a limited switching at a device voltage of −1.35 V. Therefore, all resistances below the R 0 level have to be interpreted as belonging to the LRS.

Implication
The implication p → q also consists first of an initialization into the LRS, then a logic step and finally a read out step.It is performed in three steps as shown in figure 4. As for the negation, (a) shows the voltage schemes, with the solid lines displaying the AE voltage and the dashed line displaying the OE voltage.(b) shows the resistance trace calculated based on the current and voltage results.First, the targeted cell is initialized in the LRS by applying a −1 V at the AE and 1 V at the OE.In the RESET step, V offset /2 + V logic,p and −V offset /2 + V logic,q are applied at the AE and OE, respectively.For the implication operation, V offset is always 1.35 V, while the logical input states p and q are again converted using table 3. Lastly, the result is read out by applying a small read voltage of −0.1 V to the AE while the OE is grounded.In figure 4 q is always 2 and p is 2 (petrol line), 1 (light blue line), and 0 (dark green).Therefore, the OE voltage is always −0.675 V+(−0.15V) = −0.825V, while the AE voltage changes from 0.525 V for p = 2, to 0.825 V for p = 0.

Ł 3 logic exploiting the SET operation
This section focuses on the Ł 3 logic implementation utilizing the SET process of the mentioned VCM device.The logic states for the Ł 3 logic are listed in table 4. The simulation results indicate a tolerance with ±0.01 V of the required voltage drop V gs .For example, the simulation ranging from 4.23 MΩ to 4.7 MΩ corresponds to the V gs ranging from 0.51 V to 0.49 V.For HRS, without strong enough driving force V gs , the device cannot be programmed to lower resistive states.When the tolerances are taken into consideration, the HRS is equal to or larger than the resistance corresponding to V gs = 0.51 V.In the following simulations, the device is always initialized with a 3 V RESET voltage applied to the source of the transistor and SET with a 4 V SET voltage along with the logical inputs being applied to the OE of the device.Unlike utilizing absolute voltage drops over the device in RESET operation, computing in SET operation needs a sufficient voltage drop across the device considering the voltage divider effect with the transistor.In addition, the switching process is mainly controlled by the voltage drop across the gate and source of the transistor.With a variable gate-source voltage drop over the transistor the drain saturation current flowing through the device is tuned to limit the SET operation.The larger the V gs , the wider opens the transistor, so that the lower resistive states can be reached in the device.According to the schematic shown in figure 1(d), the gate-source voltage drop over the transistor during the SET process is given as: When using only two operands, they can be applied to the gate and source separately.With three operands the third one is linked into the source side, as presented in the parentheses as logic input c.The voltage at the OE terminal is as follows: where α is a coefficient for adjusting the effective voltage drop over the device.It is associated with the chosen resistances in the device and the resistance of the transistor because of the voltage divider effect.For the resistances in the MΩ range and the applied transistor in this work, it is set to 1.62.In other cases, the optimal α can be found through simulation as well.Since the logic states are linked to the gate-source voltage drop, the logical inputs can be converted into the voltage inputs at the gate and source of the transistor.To better represent the logical states and the voltage inputs, offset voltages (V offset ) are used in this concept as well, which are integrated into the gate voltages of the transistor (cf equation ( 6)).The offset voltages are chosen as 0.5 V in order to match the programming voltages V gs in table 4, so that the other logical inputs can be mapped to the corresponding voltage levels.As shown in the schematic, V gate is applied to the gate of the transistor and V source to the source terminal.The mapping of the voltage inputs with the logic states are shown in table 4. It is clearly evident that the difference(∆) between logic states or voltage inputs is constant.
After mapping the pair of starting states, the following mapping can be achieved with counting the number of the increasing levels ∆s.For example, when logic 0 was mapped to V logic,start = 0 V, for logic 1 it has two increased ∆s so that the corresponding V logic should be added with two level states (2 * 0.05 V) from the starting level 0 V, resulting in 0.1 V.This concept is easy to be extended to higher multi-valued logic.

Negation
The definition of the negation operation has been described in the previous section.Firstly the device will be programmed to the HRS.Then, the device is programmed to the desired output state by applying suitable voltages V gs and V source .As there is only one input for the negation operation, i.e. p, V logic,input,q is set to 0 V.When performing the Ł 3 negation operation with the SET process, to maintain the mirroring effect around the middle value, the middle logical voltage input V gs has to be mapped with the middle logic value (1) which means V gs = 0.55 V coupled with V logic,input,p = 1.By setting the V offset to 0.5 V, V p=1 must be V gs minus V offset , resulting in 0.05 V.With mapping the interval of logic level to 0.05 V of the voltage input, the V p is linked to logic p in an opposite direction.While logic p = 2 increases from logic p = 1 by 1, V p = 0 V decreases from V p = 0.05 V by 0.05 V.The mapping for logic p = 0 can be achieved similarly, resulting in V p = 0.1 V.By coding the read out states of resistances with logic values and voltage inputs the mapping is achieved in the end and shown in table 5.
Figure 5(a) shows the three voltage input signals at the gate and the source of the transistor and the OE of the device.Figure 5(b) is the gate-source voltage drop on the transistor.The simulation results of the negation operation is shown in figures 5(c) and (d).Compared with the states shown in figure 2, the marked colors are exactly in the opposite direction and the final read out resistances are listed in table 5.

Implication
The operation of the implication in the SET direction consists of three steps as well: RESET-initialization, logic computing or programming and read out.The RESET and read out procedure are the same as in the negation operation in last subsection, while the logic computing step differs.First of all, the logic input q is converted into a voltage level and added to the source voltage.The offset voltage V offset in the gate voltage is set to 0.5 V corresponding to the V gs for achieving HRS.In this operation, V logic,q is no longer 0 V, so that the V gs is exactly the same as given in equation (8).Like the programming voltage curve in last negation section, the applied voltage input signals and V gs are presented in figures 6(a) and (b), respectively.During the implication operation, V gs has 5 levels in the SET programming procedure, two of which are able to switch the device into lower resistive states, MRS and LRS, marked in orange and red, respectively.The other three blue lines represent the HRS.As discussed before, all read out resistances larger than 4.28 MΩ are considered as HRS (blue).The resulting resistances are shown in figures 6(c) and (d) presents the corresponding concentration of oxygen vacancies in the disc.The mapping of the voltage levels to the logic inputs of this operation is shown in table 4.
The final simulation result of the implication is shown in table 6.The color in the background together with the logic value of p and q verify the truth table of the implication logic operation.Because of the read out procedure, the applied limit for the HRS is set to 0.5 V as before.Therefore, the read out resistance for p = 0 and q = 2 should be 2 levels larger than the corresponding resistances (4.48 MΩ) and this is verified in the table.

Implementation of the ternary addition
By using logic concepts in which more than two truth values are utilized, the number of devices needed for a certain operation can be reduced.This increases the memory capacity.In this work, we propose two full adder concepts that are array compatible based on the multilevel switching in RESET and SET direction.The  adder in the RESET direction is a ternary modulo adder and can be operated in passive 1S1R arrays, while the adder in the SET can be integrated in active 1T1R arrays.For both adder concepts we demonstrate a 41 Trit addition, which is roughly equivalent to a 64 Bit addition regarding its value range.

41 Trit addition based on multilevel RESET switching
The ternary adder demonstrated here is adapted from the scheme introduced in [28].While in [28] six HRS levels were required, we show how this can be reduced to three HRS by using a constant offset reduction.The flow chart of the adder operation is shown in figure 7(a) for the ith bit position.To perform the addition for one bit position only one cell is required.Additionally, the carry from the previous stage (i − 1) has to be stored, as it determines the offset voltage.The addition is then performed in the following way.First, the ith cell is initialized into the LRS.For that purpose, the SET voltage of −4.5 V is split equally between the OE and the Bitline.Then, depending on the carry output of the previous stage (c i ) the offset is either chosen as 1.825 V (if c i = 0) or 1.875 V (if c i = 1).Next, the cell is RESET based on the chosen offset voltage and the converted logical inputs.The RESET voltages are in the range 3.65 V-3.85 V with a 0.1 V spacing between the different levels.The resistances R 0 , R 1 and R 2 are used to represent the logic levels 0, 1 and 2, respectively.The operands of the addition are encoded as voltages (V op,i ), with a logical zero being mapped to 0 V, logical 1 being mapped to 0.1 V and logical 2 being mapped to 0.2 V, corresponding to the spacing of the RESET voltages.The first operand is applied to the BL V BL = −(V offset + V op,1 ) and the second operand together with the offset voltage is applied to the OE V OE =(V offset + V op,2 ).The resulting device voltage is then given as A voltage increment of 0.1 V corresponds to a logical increment of 1. Directly after the RESET, the cell is read out at −1.7 V applied at the OE.The resistance state of the read out cell is then compared with R 2 .If it is smaller or equal to R 2 , the carry for the next stage c i+1 is zero and the sum bit at position i is equal to the cell resistance.If the resistance of the cell is larger than R 2 , c i+1 is one and the cell has to be reprogrammed.For that purpose, first the offset voltage is reduced by 0.3 V.Then, the cell is SET, RESET with the adapted offset voltage and read out again.The new read resistance is then the sum bit s i .For a 41 Trit addition, 42 devices are required as one device is needed to store the carry output of the 41st stage.Due to the program disturb effect in m•n arrays, where m and n are both larger than one, a selector element is required for each device to prevent read disturb.The 1S1R array structure is shown in figure 7(b), with three devices that are connected with each other via a single OE.Each device has an individual BL and the device direction is defined, such that the SET occurs at negative V device and the RESET occurs at positive V device .To make the adder scheme array compatible a selector element is added in series to the VCM cell and the voltages are split between OE and Bitlines, similar as for a V/2 scheme.Adding the selector requires an increase in the required voltages compared to the initial demonstration in [28].Figures 7(c)-(e) show the OE voltages (red solid lines) and BL voltages (black dashed lines) of the different devices.The final current levels can be seen in figures 7(f)-(h).They are also summarized in table 7.
The SET phase of the addition is encoded in orange, the RESET phase is encoded in green and the read phase in blue.SET and read phase are always performed in the same way, only the RESET phase changes based on the current operand voltages and the offset.The x-axis is scaled to highlight the interesting section for each cell for the first cell (c) and (f), the middle cell (d) and (g) and the last cell (e) and (h).The final resistances of the three devices shown are R 2 for the first device, R 0 for the 22nd device and R 1 for the last device.If the addition has finished for a certain cell, the corresponding BL is set to ground and the cell only sees around half of the operating voltage via the OE.Due to the selector device in series this does not lead to unwanted switching anymore.

41 Trit addition based on the multilevel SET process
With the same parameter set given in table 1 a ternary adder can be implemented in the SET process as well.This concept is also based on the modulo sum operation.Besides the three resistive states presented in table 4 additional space for the read out resistances smaller than LRS is essential for judging the carry Trit.This state does not have to and will not be stored in the end, therefore it is named as TRS (temporary resistive state).TRS is naturally defined in the range < 0.25 MΩ.To represent the logic values, HRS, MRS, LRS and TRS are mapped to sum Trit as 0, 1, 2 and carry bit as 1, respectively.All the relationships of the inputs are given in the following equations: where 0.15 V is used to keep the source voltage positive and it should be compensated in the gate voltage as well and V OE = V SET + α * V source offers the driving force in the switching process.The operands V p and V q of the operation are embedded in the gate and the source voltage of the transistor, respectively.Meanwhile, an offset voltage is needed as well to tune the V gs for achieving the expected resistive states in the device.The voltage input V c for the carry bit is added to the source (and OE) voltage, serving as the 3rd operand This equation perfectly represent the additive operation with three operands.Only the carry has to be considered and realized in an extra operation step.The mapping of the logic values to the voltage levels are given in table 4. It is clear that V c depends on the previous operation and because of the procedure of the judgement in between: whether the read out resistance equals to or is lower than TRS, it is required to run the RESET-SET-READ-cycle twice for a single Trit sum operation, which are named as pre-sum and end-sum here.In case the carry of the current sum operation was 1, the end-sum operation has to implemented with a new offset voltage, 0.15 V lower, as shown in the flow diagram in figure 8(a).All devices have to be operated with the pre-offset voltage in the first operation cycles.Is the read out resistance lower than TRS, the device has to be operated again with the end-offset voltage (0.15 V lower than pre-offset voltage) for the end-sum, meanwhile the carry for the next Trit will be set to 1, otherwise it will be 0. Theoretically, when the carry equals to 0, the second sum operation could be avoided, but for the universal computation logic this step is still preserved in this concept.Furthermore, while performing the end-sum operation for the last Trit the pre-sum operation of the current Trit could be performed simultaneously.Therefore, an n-Trit addition operation takes n+1 cycles.A part of the 41 Trit Addition simulation (Trit 2 and 3) is taken as example for the proof-of-concept.In this case, the two 'partial' ternary numbers are p = p 3 p 2 = 12( =5) and q = q 3 q 2 = 21( =7), and the carry bit from prior Trit c 1 is 0. In the end, the carry of the addition p 3 + q 3 + c 2 will be sent to the next Trit as c 3 .With the given logic value of p, q and c 1 = 0, V offset,2 = 0.5 V, V p,2 = 0.1 V, and V q,2 = 0.05 V is set for the first pre-sum operation.Leading to V gs2 = 0.65 V, which sets the device resistance to TRS.Therefore, V offset,2 has to be 0.15 V lower for the end-sum operation, resulting in V gs2 = 0.35 V and c 2 = 1 is sent to Trit3.The corresponding read out resistance in the end-sum is switched to HRS (s 2 = 0).Meanwhile, with c 2 = 1, the pre-sum operation for Trit 3 is performed simultaneously, as shown on the time axis in figure 8(b).During the pre-sum operation of Trit 3, V offset,3 = V offset,3 = 0.5 V and V gs3 = 0.5 V+0.05 V(p 3 ) + 0.1 V(q 3 ) + 0.05 V (carry 2 ) = 0.7 V. V gs3 is larger than V gs2 so that it sets the resistance of the device to a lower value, i.e TRS.Then for the end-sum operation V offset,new,3 has to be lowered by 0.15 V as well, which changes the V gs3 to 0.55 V and sets the c 3 to 1.With the new V gs MRS (s 3 = 1) is achieved in the end.Therefore, Because an extra Trit is reserving the carry bit of the MSB, 42 devices are required for implementing a 41-Trits addition operation, same as in the RESET direction implementation.All devices share the BL connected to the bottom electrode.For all devices, which are not in the computing states, the gate voltages are set to 0 V to ensure the system functioning properly.
As a representative only the processing signals of 1st, 20th and 41th Trits are shown in figure 8(c).From Trit 19 it can be recognized that the gate-source voltage drop is set to 0 V out of working time to prevent the drift current flowing into the device.When it is set to TRS in the first set step, the device will be programmed with a new V gs in the end-sum operation.The two read out resistances are clearly different while the ones of the 41th Trit are at the same level.By different read out resistances the carry bit is always set to 1 and the offset voltage is lowered by 0.15 V.

Discussion
In this section, we discuss the performance of the Łukasiewicz logic operation and the adder for the RESET and SET direction based on the required number of devices, the number of cycles and the energy consumption.Generally, for the presented ternary Ł 3 logic and for the n-bit adder concept, the same algorithm is used for the RESET and SET direction with inverted initialization states and inverted logical states.The operations presented in this paper operate only on single elements.For the RESET direction this single element consist of a series connection between a two terminal selector device and a VCM cell (1S1R structure), while for the SET direction, the single element consists of a series connection between a three terminal NMOS transistor and a VCM cell (1T1R structure).While the 1S1R structure allows for the smallest possible footprint of 4 F 2 the 1T1R structure has a larger footprint of >8 F 2 [32].Regarding the energy consumption the SET direction approach using 1T1R structures has a distinct advantage over the RESET direction.While the initialization for the RESET direction logic (which is a SET operation) is an unrestricted switching process, it results in a very small LRS.The operation is unrestricted, as the selector element is very low ohmic when selected, and because the SET process is self accelerating in filamentary VCM devices due to a positive thermal feedback loop [1].This will result in high currents flowing during read out and will also lead to higher programming energies.On the other hand, the SET processes for the SET direction logic (during which the logic operations are performed) are restricted by the different current compliances of the series transistor, meaning that the resulting LRS can be controlled.The switching processes in RESET direction are always restricted, as a RESET at a constant voltage level will reduce the current over time until the device stops switching.Therefore, the 1T1R array could also be used to realize the RESET direction logic.

General properties of SET and RESET direction
The ternary Ł 3 logic in its functionally complete form consists of three basic operations, namely negation, implication and false operation.The negation and implication operation each consist of a initialization step into the LRS/HRS for the RESET/SET direction logic, then an logic step and finally a read out step.The read out step is technically not needed to successfully perform the logic operation and has only been included in the previous sections to show the correctness of the logic operations.The false operation consists of writing the cell into the highest/lowest resistive state for the RESET/SET logic.All logical operations in SET and RESET direction operate on a single cell per Trit.
The ternary adder concepts for the RESET and SET direction operate on a single cell at each bit position plus an additional cell to store the carry output of the last bit position.The n-bit adder then requires n+1 devices to operate for both directions.In both switching direction, the device at position n is first initialized.Depending on the carry output of the previous stage the offset voltage is chosen.Thereafter, the logic step is performed and the device state is read out, to assess whether it belongs to the three valid resistance states (R 0 , R 1 or R 2 for the RESET direction and HRS, MRS and LRS for the SET direction).If it does, the addition is finished, otherwise the offset is modified and the device is initialized, programmed and read out again.Therefore, for the calculation of each bit of the addition, either one initialization, one programming and one read step are required or two of each.As for the logic computation, the second read out step is only included to verify the correctness.

Programming energy
The programming energies for the various operations are extracted from the simulations using where t 1 and t 2 indicate the beginning and end of the voltage pulse.All relevant energy components are shown in table 8 for the RESET direction and in table 9 for the SET direction.For the RESET direction logic operations, only the LRS, R 0 , and R 1 are required.The logic operations are evaluated based on simulation results from 1 R line array structures, as in the experimental study in [28].For the adder, the results are based on 1S1R simulations as the selectors are required to enable the adder in crossbar arrays.If multiple values are given, the first value refers to the 1 R simulations and the second value refers to the 1S1R simulations.For the original adder concept six HRS and one LRS were required to be differentiated.This requirement was simplified here to only require the differentiation of three HRS states and one LRS state.Still, depending on the RESET voltage all six HRS levels can be accessed.Therefore, table 8 is extended to include all possible HRS states.The initialization step costs the most energy.Due to the higher initial current flow at lower resistances, starting from a smaller resistance and programming into the LRS is more expensive.The higher energy consumption with selector results from the higher programming voltages which are roughly larger by a factor of two.This is due to the fact that if the devices are in the LRS, a large voltage will drop across the selector resulting in a very low ohmic selector.Programming from the LRS consumes more energy if the HRS state towards which we program is smaller, due to the higher currents.For the readout step the energy consumption is higher the smaller the resistances are.The readout consumes significantly more energy if the 1S1R structure is used, as the read voltage is much higher (−1.7 V instead of −0.1 V).
The results for the SET direction scheme are obtained in the same fashion.Generally, the energy cost is smaller due to the higher resistances programmed through the multilevel SET.Here, all results are obtained from simulations in the 1T1R configuration.From these results, the best and worst cases energy consumption can be determined.For a logic operation in the RESET direction in the 1S1R array the worst/best case energy costs are 2.425 nJ/2.114nJ.They are obtained, when the cell is in the LRS/R 1 initially and is programmed to the LRS/R 1 .The corresponding values for the SET direction are 98 pJ/86.5 pJ, obtained for the initial device being in the TRS/HRS and being programmed into the LRS/HRS.The addition algorithm requires in the best case one SET, one RESET and one read operation per Bit position.In the worst case it requires 2 SET, 2 RESET and one read operation per Bit position.For the last Bit position an additional SET and RESET is required, to program the final sum bit corresponding to the carry Bit from the second to last stage.The number of operations is the same for the SET and RESET direction mapping approaches, only the sequence of SET and RESET is switched.The corresponding worst case energy per Bit for the RESET direction is 4.252 pJ.This is obtained, when the cell is initially in the LRS, is then programmed into R 3 and read out.The readout of R 3 requires another initialization (from R 3 ) and a subsequent programming into R 0 .The best case energy is obtained, if the device is initialised into the LRS starting from R 5 , then programmed into R 2 and finally readout, resulting in a best case energy of 1.85 nJ.For the SET direction adder the worst case and best case energies for the addition are 659 pJ and 77.5 pJ.The worst case energy is obtained, if the device is initially in the TRS3 and subsequently programmed into the TRS3 and read out.This requires an additional initialization from the TRS3 with a programming into the LRS and a read out.In the best case situation, the device is initially in the HRS, programmed into the HRS and then read out.

Conclusion
In this paper, we have presented a ternary Lukasiewicz logic concept as well as an ternary adder.For both concepts, we explore how they can be executed by exploiting the multilevel programming capabilities, either in the RESET or in the SET direction.The main advantage of the logic concept is, that it can be easily extended to n-valued logic systems (for odd n), by only adapting the voltage assignments for offset and logical state equivalent voltages.Another advantage is that our logic concepts puts only very little requirements on the devices which should result in high success probabilities.Essentially, we only require the devices to be able to achieve multilevel programming since we always initialize our devices to the LRS (for the RESET direction) or to the HRS (for the SET direction).The logic operation then consists in a multilevel programming step starting from one initial state.Multilevel programming in the SET direction by modifying the gate voltage in a 1T1R structure has been shown to be possible many times in literature [41,42].Regarding the possibility of multilevel switching in 1S1R devices, it was shown for example in [43] that different applied reset voltages also lead to different reset voltages seen by the 1 R cell in the 1S1R structure.These different RESET voltages can then in principle be used to program different HRS states in the same fashion as for the 1 R structure.One advantage of the adder is that it distributes the programming across all devices very evenly, as each device considered for the addition is programmed either two times or four times during an n-bit addition.We have shown that it is possible to use the multilevel switching capabilities of VCM cells in different ways to realize logical and arithmetic circuits.Based on the proposed schemes it is now possible, to build larger computing systems that are fundamentally based on the here proposed basic logic gates.

Figure 1 (
b) shows the basic array elements for the 1S1R array and (c) shows the ECD of the selector model.The basic elements of the 1T1R array with the definitions of V Source , V OE , V Gate and V Device are shown in (d).

Figure 1 .
Figure 1.(a) shows the equivalent circuit diagram of the JART VCM v1b model, adapted to the Ta2O5 based VCM cells.(b) shows the basic element of the 1S1R array and (c) shows equivalent circuit diagram of the selector model.(d) shows the basic 1T1R cell.(e)shows a simulation of the multi level switching in the SET direction by using different current compliances (−300 µA, −600 µA and −900 µA) and (f) shows multi level switching in the RESET direction for the by using different maximum RESET voltages (1 V, 1.2 V and 1.4 V increments).For (e) and (f) the simulations are based on a single VCM cell.

Figure 2 .
Figure 2. Ternary states in SET progress with additional read out step after initialization.(a) shows the changing of the resistance of the device, calculated by dividing the voltage drop across the device by the current flowing through it.(b) indicates the real time concentration of oxygen vacancies in the disc.

Figure 3 .
Figure 3. Simulation of the negation for the RESET direction Ł3-logic.The applied voltage signals are shown in (a) where the solid lines show the voltages applied to the AE while the dashed line shows the voltage applied to the OE.(b) shows the simulated resulting change of the resistance.

Figure 4 .
Figure 4. Implementation of the implication operation in Ł3-logic in the RESET direction.The applied voltages are shown as colored solid lines for the AE voltage and as striped line for the OE voltage in (a).(b) shows the simulated resulting change of the resistance and (c) shows the results of the implication operation for all combinations of p and q.

Figure 5 .
Figure 5. Simulation of the negation in Ł3-logic.The applied input signals are shown in (a) and (b) shows the gate-source voltage drop on the transistor.(c)shows the resistance in the device and (d) indicates the concentration of the oxygen vacancies in the disc.

Figure 6 .
Figure 6.Simulation of the implication in Ł3-logic.The applied input signals are shown in (a) and (b) shows the gate-source voltage drop on the transistor.(c) shows the resistance in the device and (d) indicates the concentration of the oxygen vacancies in the disc.

Figure 7 .
Figure 7. (a) shows the flow diagram of the adder in RESET direction at position i.(b) the proposed 1S1R array structure for a 41 Trit addition.Only the first, middle and last device of the whole array are shown.(c)-(e) show the OE voltages (black dashed lines) and the Bitline voltages (red solid lines).For the specific device numbers 1, 22 and 42.(f)-(h) show the current through the respective devices.In (c)-(h) the different adder phases are color coded.Orange denotes the SET phase, green the RESET phase and blue the read phase.

Figure 8 .
Figure 8.(a) shows the flow diagram of the adder in SET direction at cell i.(b) The Vgs, read out resistance, V Device and I Device of the second and third device for Trit2 and Trit3, respectively.(c) The processing signals of Vgs, V device , I device and R device of the 1st, 20th and 41th device.Number 1, 2 and 3 represent the initialization, set and reading steps, respectively.

Table 1 .
Deterministic model parameters of the JART VCM v1b model.

Table 4 .
Simulated resistance states and their assignment in the different Łukasiewicz logic.The rightmost column shows the required absolute programming voltages Vgs required to reach the specific level.

Table 5 .
Mapping of the logical input states to the equivalent voltage levels for the negation operation and the simulated final results of the negation operation.

Table 6 .
Simulation results of p → q for Ł3 in SET progress.

Table 7 .
Resistance definitions and current levels of the different states in the 1S1R array at the read voltage of −1.7 V applied to the OE with the bitline being grounded.The rightmost column shows the voltage required to program the corresponding state in the 1S1R array.

Table 8 .
Overview of the Possible Resistance Levels and the Energy Cost of the RESET Direction Logic and for the RESET Direction Adder.

Table 9 .
Overview of the possible resistance levels and the energy cost of the SET direction logic and for the SET direction adder.