Neuromorphic functionality of ferroelectric domain walls

Mimicking and replicating the function of biological synapses with engineered materials is a challenge for the 21st century. The field of neuromorphic computing has recently seen significant developments, and new concepts are being explored. One of these approaches uses topological defects, such as domain walls in ferroic materials, especially ferroelectrics, that can naturally be addressed by electric fields to alter and tailor their intrinsic or extrinsic properties and functionality. Here, we review concepts of neuromorphic functionality found in ferroelectric domain walls and give a perspective on future developments and applications in low-energy, agile, brain-inspired electronics and computing.


Introduction
By 2024, the complementary metal-oxide-semiconductors (CMOSs)-based von Neumann computing is expected to reach its performance limits [1]. Energy and speed issues of CMOS computing which are nearing their ultimate limits are further worsened by a rapid rise of the internet of things, big data, edge computing, and artificial intelligence-powered applications. The development of alternative computational approaches and hardware is thus required to enable low-power, fast data-centric computing. Most of these alternative approaches are inspired by the functioning of the human brain-thus the name neuromorphic computing, which outperforms traditional computers in terms of speed and energy efficiency by orders of magnitude for tasks as simple as image, voice and pattern recognition. Exceptional data processing and learning abilities of the human brain are linked to its massive parallelism and interconnected dense network of synapses connecting neurons. Synapses act like plastic memory elements wherein the value of the stored weight is dynamic and depends on the history of electrical or chemical signals transmitted by neurons. The goal, therefore, is to be able to mimic these functionalities and build nano-synapses at the level of a single device.
The electronic analogue of a biological synapse is a memristor, proposed in 1971 [2] and first demonstrated in 2008 [3], whose resistance can be continuously tuned and depends on the history of the applied electrical signals, and thus exhibits plasticity. A memristor, therefore, is essentially a non-volatile memory that can be initialized into multiple unique conductance states depending on the strength, timing, and history of the applied stimuli. A high conduction state corresponds to a strong synaptic connection, whereas in a low conduction state, the connection becomes weak. The learning and processing abilities of our brain are linked to the strength of the synaptic connection that varies as the information flow between neurons. Memristive devices emulating this synaptic functionality [4][5][6] have been realized utilizing various physical phenomena and advanced materials, such as using ionic or atom motion in binary metal oxides [3,7,8] and amorphous Si [9], electron tunnelling in ferroelectrics [10], spintronics [11][12][13], phase change materials [14,15] and quantum [16] and layered van der Waals materials [17][18][19].
Nanoscale topological defects or textures [20][21][22][23]-i.e. singularities where symmetry is disrupted, of various kinds including skyrmions, merons, hopfions, solitons, vortices and domain walls, that arise in solids exhibiting spontaneous order or co-existing orders (e.g. spin, polarization, strain and toroidal moment) leading to novel rich physics and electronic effects present yet another attractive platform for the development of beyond CMOS neuromorphic electronics [24][25][26][27]. Among these domain walls in ferroelectrics-reconfigurable topological interfaces in materials with spontaneous polarization, are quite special because of their intrinsic nanoscale size (wall width ∼1-2 nm), and the fact that these interfaces can be injected, erased or pushed around with control voltages [28][29][30] rather than electric currents enabling low-energy operation [31][32][33][34][35][36][37][38][39][40][41][42]. Ferroelectric domain walls embody the ultimate adaptive property of 'now it is here' and 'now it is not' . The ferroelectric walls thus can be envisioned as nano-synaptic channels with an electrically programmable connection strength leading to memristive behaviour or multi-level states.
In this brief review, we discuss the latest developments and reported approaches leading to memristive or multi-level conduction properties of ferroelectric domain walls including memory devices, principles, and outline key challenges and opportunities for their applications in low-energy, agile, brain-inspired electronics and computing.

Memristive domain walls
Domain walls in ferroelectrics are nanoscale transition regions across which the polarization reorients. The concurrent atomic displacements and changes at the wall which include crystal symmetry, polar discontinuity, strain distribution, elemental valence state, and defect accumulation lead to a drastic modification of mechanical, optical and electronic properties at the walls, and thus distinct functional property confinement. Ferroelectric domain walls across diverse material systems have by now been shown to exhibit enhanced electrical conduction compared to the surrounding insulating or the semiconducting parent bulk (although there are some exceptions). This is similar to nanoscale phase boundaries [43][44][45][46][47][48] separating different crystalline regions.
Both intrinsic, e.g. band gap lowering, polarization discontinuity, chirality, and extrinsic factors such as oxygen vacancy and charged defect accumulation have been suggested to play a role [36,39,42,49]. Nevertheless, by utilizing various controls and external stimuli, such as doping, defects, temperature, strain and electric fields, the wall's electronic conduction is shown to be tunable, therefore, enabling the development of memristive functionality or multi-level states. For instance, the 109 • domain walls [50] in BiFeO 3 were shown to exhibit dynamic conductivity (figure 1(a))-the equivalent of adaptable connection strength in synapses. The wall conductance was found to depend on both the history and magnitude of the applied voltage, a behaviour typical of memristive systems. The wall conductance for the voltage cycle in the reverse direction was higher than in the forward direction (the direction of sweep is indicated by arrows), pointing to an electrically activated behaviour. Notably, the hysteretic behaviour became increasingly pronounced with bias. Depending on the applied maximum voltage, a set of unique (current in the reverse direction) wall conduction states spanning three orders of magnitude were achieved. This indicated the possibility of realizing voltage-controlled quasi-continuous conduction states at the wall. The wall's apparent memristive behaviour was attributed to field-driven (in a certain range) reversible and stable polarization distortions leading to a change in the wall's electronic structure and properties.
The orders of magnitude tunability of the wall's conductance were argued to arise from a non-linear tunnelling mechanism due to polarization-caused changes in the tunnelling barrier height between the tip and wall (sample). The conduction, therefore, depends on the degree of the bias-induced polarization distortion or structure driving electronic transitions within the wall. Further, using such an electrical activation, the wall segments were shown to selectively transition from an initial insulating to a conductive state. By simultaneous nanoscale monitoring of wall conduction and piezoresponse, abrupt changes in polarization configuration at the wall, akin to Barkhausen jumps [53] in wall motion, were directly inferred. In this case, a direct contribution of the wall movement to memristive behaviour was ruled out but is crucial for the development of neuromorphic circuitry. External stimuli-induced domain realignment in ferroelectrics (or ferroelastics) occurs through a mix of smooth and jerky domain wall displacements [40,[54][55][56]. The jerky movements-very fast wall displacements, correspond to switching avalanches during which atomic or ionic transport through the walls is highly localised and enhanced. The wild fast-moving domain walls, therefore, can serve as synaptic channels for selective chemical diffusion, connecting ionic reservoirs mimicking neurons in the human brain. Since jerky domain wall movements occur fast, the ionic transport using these dynamical interfaces can be controlled not just spatially but over short timescales [40]. When wall conductivity is dominated by defects and ionic charges, conductive footprints arise, which stay even when the wall is displaced [57]. Defect chemistry and material synthesis [58][59][60][61], dopants [62][63][64][65], and environmental conditions [66,67] thus all have been linked to affect and control the wall's dynamical and electronic transport behaviour.
The electronic transport behaviour of individual domain walls is also reported to be tunable through an alternation of the control field magnitude [68], e.g. charged head-to-head domain walls in p-type semiconducting ErMnO 3 were selectively transitioned between resistive and conductive state by modulating Reprinted with permission from [52]. Copyright (2020) American Chemical Society. control voltage amplitude. Change in electronic transport behaviour was attributed to significant band-bending, leading to the formation of an electron inversion layer at the wall. Such that at low fields the wall is insulating (due to depletion of majority carriers-holes) but electrons dominate conduction above a threshold field. Polarization discontuity [69][70][71][72] and exact domain topology [20,35,[73][74][75][76][77][78][79][80][81][82][83][84], e.g. flux-closure domains, bubble domains, vortex-antivortex pairs, centre convergent and divergent domains) at the wall provide yet another means to control electronic transport properties ( figure 1(b)), and achieve memristive functionality at these nanoscale interfaces. As an example, the 180 • walls written by a nanoscale SPM tip in LiNbO 3 (figures 1(c) and (d)) were found inclined as much as 20 • away from their charge neutral configuration [85], and thus were strongly (head-to-head) charged leading to electron accumulation. By controlling the topology of these strongly charged walls near the sub-surface regions (∼up to a depth of 60 nm from the surface) by application of sub-coercive bias pulses and varying their amplitude and duration, multi-level conduction states were shown to realized [85]. Wall's conduction behaviour was tuned between the resistive and conducting state in a hysteretic manner, although the magnitude of the observed conductivity was low. Lately using an in situ biasing technique within a scanning transmission electron microscope [86], an unconventional layer-by-layer switching behaviour, leading to multiple unique conductance states, was detected in which domain growth occurred along the direction of the applied electric field. Tunable electronic properties can be achieved not just at the level of a wall but can be leveraged to build and realize multi-level solid states memory and electronic devices.

Multi-level solid-state wall devices
The presence or absence of walls in solid-state devices [87] encodes binary digital information, which can be non-destructively read at voltages as low as 0.5 V. The read-out is resistive with achieved OFF-ratio's >10 3 and thus attractive for low-energy operation together with realizing multi-level states. Memristive devices, therefore, promise much higher storage densities than what can be achieved with just binary logic [42]. The overall resistance of walls is expected to scale as a function of their length (sheet length), the simplest option thus to achieve multi-level states is by precise engineering of wall length between the metal contacts. Using such an approach, changing wall length approximately by a factor of 4, the conduction level of the device was modulated across three orders of magnitude [87]. Even if the length of the injected walls were to approximately remain the same, the charge degree of freedom of domain walls [69,78,83,88] presents yet another pathway to realize multi-level states. At the charged walls, there exists a polarization discontinuity, which needs to be screened and thus leads to free charge accumulation at the wall plane. For commonly investigated ferroelectrics, polarization P is in the range of 1-100 µC cm −2 , hence at 180 • head-to-head or tail-to-tail walls, the 2D free charge densities [70,89,90] (10 12 -10 14 cm −2 ) akin to those seen at oxide heterointerfaces (i.e. high-mobility two-dimensional electron gas) [91][92][93][94][95] can arise. Hence, the charged walls usually exhibit much higher conduction compared to nominally neutral or uncharged walls [71,78,81,88,[96][97][98][99]. In BiFeO 3 thin films, a tri-state domain wall switch [100] with conduction spanning across three orders of magnitude was demonstrated through selective electrical writing and the annihilation of a pair of charged and neutral walls ( figure 2(a)). The factors enabling this precise conformational control include control of writing electric field profile (spatial and temporal) and BiFeO 3 thin films exhibiting an n-type semiconducting behaviour. Scaling these devices down improves the achieved OFF/ON ratio and sub-100 nm devices have been demonstrated [87].
More recently [102], in LiNbO 3 thin film capacitors, the conduction was shown to vary as much as 12 orders of magnitude by utilizing a dense network of strongly inclined (head-to-head) charged walls. By application of electrical pulses with changing amplitude, the extent to which the polarization reversal occurs, and thus the density of injected walls, was systematically controlled to achieve a quasi-continuous spectrum of 100 different conductance states within two orders of magnitude [102]. Furthermore, with the sequential application of pulses of fixed amplitude, the conduction state of the device was progressively altered depending on their number and thus exhibited a plasticity effect similar to ferroelectric electron junctions [10]. This means that connection strength is reinforced when the synapse is stimulated repeatedly (number of pulses), whereas it is decreased for a weaker stimulation. In a different device configuration under an applied planar field to mesa-like cells, fabricated on the surface of an X-cut LiNbO 3 film integrated on Si, domain fraction, and thus injected wall density was controlled to linearly modulate synaptic conduction [103]. The multi-level states were shown to be non-volatile and repeatable with very little dispersion in contrast to random defect-based memristors.
Neuromorphic simulation based on mesa-like LiNbO 3 synapses approaches the ideal theoretical yield and achieved high pattern recognition accuracies of ∼95% [103]. Energy efficiency and endurance of these neuromorphic tasks can be improved markedly if repeated writing or erasure of walls can be avoided, which typically require voltage pulses with amplitudes much above the coercive threshold. The potential solution is to apply sub-coercive bias pulses and exploit the as-prepared (or an initial electrically written) domain pattern with a specified domain density. For instance, using sub-coercive voltage pulses, the near-surface topology of the strongly inclined, isolated 180 • walls in LiNbO 3 thin films can be controlled to drive the walls between their insulating and conducting state [85]. The same, thus, can be achieved in a device form, and a low voltage memristive behaviour (multi-level states) [52] with an OFF/ON ratio of ∼100 was demonstrated by interfacing a polydomain LiNbO 3 film with graphene top electrode and sub-coercive bias application (figures 2(b) and (c)).
For over a century now, ferroelectric domains have been the mainstay and basic element for data encoding and storage applications. The charge-based, ferroelectric random access memory [104] is a prime example of this. The information encoded in domains can also be read resistively through partial switching and the creation of transient charged walls [34,[105][106][107][108]. The transient walls appear as the data is read at an applied bias and disappear as soon as the bias is removed. This enables a non-destructive readout and a much smaller device footprint. Both two-and three-terminal devices have been demonstrated. Translating this approach to mesa-like cells fabricated on LiNbO 3 and utilizing a thin 'interfacial layer' formed between metal contacts and ferroelectric film, a very high OFF/ON ratio >10 6 with endurance over a billion cycles was achieved [108,109]. Within this interfacial layer, the polarization direction is pinned to the initial polarization direction of the mesa, and the film underneath. As a result, when a writing voltage is applied to switch the polarization direction of mesa relative to the film underneath, a domain wall is created that bridges the metal contacts. However, in the interfacial layer, the switching is volatile, and the interfacial domain returns to its pristine direction leading to a break in the continuous wall path to the metal contact. These interfacial domains and walls, therefore, leads to diode-like behaviour, which can be initialized into multi-level states. Exploiting these multi-level interfacial wall diodes in three-terminal mesa-like devices based on LiNbO 3 ( figure 2(d)), the logic gate functionality of NOT, NAND, and NOR was demonstrated, (c) Conductance of the graphene/LiNbO3 device as a function of set pulse amplitude and duration for a polydomain state created by a poling pulse of (33 V, 1 s). The conductance readout is at 2 V dc bias. A preset pulse of (−2 V, 1 s) and (6 V, 1 s) was applied to reset the initial states for the positive and negative set pulses respectively. Reprinted with permission from [52]. which is crucial for the development of logic-in-memory computing [108]. In a different methodology, a diode-like transport behaviour was also achieved through a stable control of near-surface wall topology or inclination in LiNbO 3 [110]. These wall diodes were used to construct and show AND and OR logic gates.
Another proposal for programmable logic gates and circuitry was based on controlled writing and the erasure of walls in topologically confined vertex domains in self-assembled ferroelectric nanoislands [51]. A three-terminal, fast, field-effect junctionless transistor [101] and diode operation [111] were also realized using electrically reconfigurable stable domain walls in ion-sliced LiNbO 3 films bonded to silicon (figures 2(d) and (e)). Further, charged domain walls in electron tunnel junctions [112][113][114] can lead to quantized electronic states [115,116] affecting electronic transmission behaviour, hence presenting another means for the emulation of synaptic functionality. Most of these demonstrations and concepts are still relatively recent, and further advances would be necessary for the development of wall-based brain-inspired applications such as (stochastic or spiking) neural networks, and reservoir computing. For instance, the biologically inspired spiking neural networks used for unsupervised learning rely on spike-time dependent plasticity-STDP behaviour. STDP links the learning ability of the human brain to the plasticity of the synapse which evolves and depends on the timing and causality of the electrical signals (action potentials) from the neighbouring neurons. Figure 3 shows the concept of a wall nano synapse mimicking the STDP behaviour. The synaptic connection strength or conduction state depends on the sequence and time delay of pre-and post-neuron spikes (represented by electrical pulses on the top-right, figure 3). The pre-and post-neuron electrical pulses sum up and can with certain timing and amplitudes be large enough to initiate resistive switching originating from any or combinations of the wall-based factors and mechanisms such as domain wall shape/length, charge state, type, position etc, depending on the material type, device geometry, spatial and temporal dependence of the external field, and other electrical and mechanical constraints.
When the pre-neuron spike occurs just before the post-neuron, the synaptic connection strength (conductance-G) increases, however, if the post-neuron spike precedes the pre-neuron spike, the synaptic connection strength decreases ( figure 3(b)). The synaptic connection strength and consequently the learning is guided by the sequence and delay, i.e. the time-correlations of the pre-and post-neuron electrical signals. The characteristic wall features (dynamic adaptability and nanoscale size) together with a plethora of control mechanisms for conductance modulation across several orders of magnitude thus offer emerging opportunities for the development of domain wall-based energy-efficient neuromorphic and brain-inspired devices.

Challenges and opportunities
The development of new device concepts based on domain walls has led to initial demonstrations of neuromorphic functionality. However, a full replication of function found in natural biological systems is still in its infancy. The associated challenges are manifold and include the selection of suitable materials, parameters and device design considerations. The fact that domain walls have been discussed in the context of their 'agility' , i.e. capability to change shape, surrounding crystal structure phase [117,118], intrinsic structure, chemistry, optical properties [119], and associated electronic properties, opens a wide playground for testing concepts related to neuromorphic elements. Recent advances have also seen them integrated in serial and parallel logic gates, which could enable larger integrated circuit functionality in the future.
A combination of the above with other concepts, such as machine learning algorithms, seems feasible and could be applied to small-scale neural networks. Of specific interest is the dynamic range of changes in resistivity, which can span several orders of magnitude for domain walls [33,36,52,102,106,109]. This could be further improved through the introduction of optically controlled screening in ferroelectrics [120][121][122][123][124][125][126] or optically driven phase changes [127,128], giving rise to optoelectronic neuromorphic elements. Besides, the presence of ferroic or polar order in novel materials, e.g. CMOS-compatible doped hafnium oxide [129,130], ZnO [131,132], AlScN [133] and 2D layered van der Waals systems [134][135][136][137][138], expand the materials library for the developments of wall-based neuromorphic devices and functionality.

Data availability statement
No new data were created or analysed in this study.