Atomic-scale oxygen-vacancy engineering in Sub-2 nm thin Al2O3/MgO memristors

Ultrathin (sub-2 nm) Al2O3/MgO memristors were recently developed using an in vacuo atomic layer deposition (ALD) process that minimizes unintended defects and prevents undesirable leakage current. These memristors provide a unique platform that allows oxygen vacancies (VO) to be inserted into the memristor with atomic precision and study how this affects the formation and rupture of conductive filaments (CFs) during memristive switching. Herein, we present a systematic study on three sets of ultrathin Al2O3/MgO memristors with VO-doping via modular MgO atomic layer insertion into an otherwise pristine insulating Al2O3 atomic layer stack (ALS) using an in vacuo ALD. At a fixed memristor thickness of 17 Al2O3/MgO atomic layers (∼1.9 nm), the properties of the memristors were found to be affected by the number and stacking pattern of the MgO atomic layers in the Al2O3/MgO ALS. Importantly, the trend of reduced low-state resistance and the increasing appearance of multi-step switches with an increasing number of MgO atomic layers suggests a direct correlation between the dimension and dynamic evolution of the conducting filaments and the VO concentration and distribution. Understanding such a correlation is critical to an atomic-scale control of the switching behavior of ultrathin memristors.


Introduction
Memristors are two-terminal devices that behave like a nonlinear resistor with memory, exhibiting a pinched hysteresis loop when measuring their current-voltage (I-V ) response [1,2].Among others, metal-oxide memristors are one of the most studied types of memristors and use a common M1/M2 bilayer structure for the active layer.The M1/M2 structure is composed of a defective oxide layer (M2) which contains mobile oxygen vacancies (V O ) and acts as a V O reservoir, and a pristine oxide layer (M1) with minimal V O .Under an applied set (or reset) electrical bias and often in conjunction with Joule heating, the V O diffuse through the oxide layer, forming (or rupturing) a conductive filament (CF) between the electrodes.This CF rupture and formation leads to resistive switching between a high resistance state (HRS) and a low resistance state (LRS), respectively.Progress in developing metal-oxide memristors has been able to decrease switching speeds down to below 10 ns [3,4], switching energy to 115 fJ [5] while increasing the memristor's lifetime to over 10 12 resistive switches [6], with on/off ratios from 10 3 to as high as 10 9 have been reported [7][8][9].It has additionally been shown that memristors can have multiple distinct LRS states, and it is possible to obtain different LRS by using an appropriate compliance current [10,11].With comparable device properties to transistor technology in switching speed, energy consumption, and device endurance, as well as physical, multi-state resistive memory, memristors are promising candidates for high-density non-volatile memory and neuromorphic computing.
While the presence of V O is essential for resistive switching behavior, the presence of other defects, many originating from a defective interfacial layer (IL) at the electrode/M2 interface, contributes to leakage current, charge traps, and other deleterious effects that reduce the memristor's endurance, switching speed, and increases its switching energy [12][13][14].This IL can arise from exposing the electrode to atmosphere during the fabrication process and from nonideal conditions during the deposition process in physical vapor depositions and chemical vapor depositions including atomic layer deposition (ALD) [15][16][17][18][19][20][21].Among others, ALD has been utilized for the synthesis of metal-oxide based memristors, taking advantage of ALD's conformal coating over a large area and self-limiting deposition for atomic-scale thickness control [22][23][24][25].For many metals, native metal oxides will form on the electrode surface if it has been exposed to ambient conditions prior to the ALD deposition of the M1/M2 active layer.The native oxides are often defective, leading to incomplete ligand exchange and nonuniform deposition during the first few ALD cycles [26,27].Typically, to combat the effects of undesirable defects, a thicker active layer measuring 4-12 nm or thicker is used [28][29][30][31].The resulting thicker memristors exhibit an increased endurance, decreased leakage current, and increased on/off ratios, but at the cost of an increase in switching pulse amplitude and energy consumption [31].
The presence of undesirable defects in the oxide M1/M2 layer also leads to difficulties in controlling V O concentration, distribution, and diffusion, which impact the CF microstructure and dynamic switching behavior directly.To address this issue, an in vacuo ALD process has recently been developed [32] that is capable of creating a negligibly defective IL at the electrode/M2 interface.This process leads to a high, thicknessindependent tunnel barrier height as the Al 2 O 3 thickness is varied from 0.1-1.0nm in Josephson junctions [26,27].An ultrathin pristine Al 2 O 3 film with negligible defects also exhibits high-quality dielectric properties with a high dielectric constant of ∼8.9, close to the bulk value of 9.2 observed in 3-4 nm thick Al 2 O 3 capacitors [33].For memristors, the presence of V O with controlled concentration and distribution is critical to generate resistive switching.In a recent work by Goul et al [34], guided by density functional theory (DFT) simulations, V O doping was achieved by inserting MgO atomic layers into pristine ALD Al 2 O 3 enhancing both resistivity and the formation of V O [30,[35][36][37][38]. Interestingly, these doped Al 2 O 3 /MgO atomic layer stack (ALS) memristors exhibited tunable on/off ratios in the range of 10-40,000 as the ALS thicknesses was varied from 1.2-2.2nm, illustrating the importance of reducing or eliminating the undesired defects in ultrathin memristors.
It should be noted that these Al 2 O 3 /MgO ALS also provide a promising scheme for investigating the effect of atomically controlled V O concentration and distribution, which differs from other approaches of V O generation through formation of defects [39], on the CF microstructure and dynamic evolution.Motivated by this, this work investigates three sets of Al 2 O 3 /MgO ALS memristors all having a total of 17 atomic layers in the ALS, or a total ALS thickness of ∼1.9 nm, in which the V O concentration and distribution are controlled by inserting different numbers of MgO atomic layers in different locations of the Al 2 O 3 /MgO ALS.An interesting trend of decreasing LRS was observed with increasing V O (MgO layers), indicative of the CF lateral dimension increasing.Furthermore, multi-step switching behavior seems to be promoted by higher concentration and more uniform distribution of V O in the M1/M2 layer, suggesting a method of promoting the dynamic evolution of the CF formation through the addition of V O .

Methods
Memristors were made using the in vacuo ALD deposition described by Goul et al in their recent work [34].Memristors were deposited on an Si/SiO 2 wafer chip in an interconnected sputtering and ALD system in order to minimize exposure to atmosphere during the fabrication process.The memristor Al and Pd electrodes were deposited using a DC magnetron sputter at a base pressure of <6.0 × 10 −7 Torr, using an Ar plasma (14 mTorr/ 90 W for Al and 30 mTorr/45 W for Pd).After the 10 nm thick bottom Al electrode was deposited, the wafer chip was transferred to the ALD chamber.The ALD chamber had been pre-heated to 225 °C and the chip was allowed to dynamically heat for 25 min before ALD deposition of the memristor active layer.The active layer was made by depositing a total of 17 ALD layers composed of a mixture of Al 2 O 3 and MgO atomic layers, using trimethylaluminum or bis(cyclopentadienyl)magnesium(II), respectively, as the primary precursor.The primary precursor was injected into the ALD chamber for 2 s to deposit the Al 2 O 3 or MgO and was followed by a 35 s N 2 purge.A 2 s pulse of deionized H 2 O was introduced to the ALD chamber and followed by an N 2 purge for 35 s.The sample was removed from the ALD chamber and cooled to room temperature under vacuum following the ALD deposition.Vacuum was broken to exchange the shadow mask for the bottom electrode with the shadow mask for the top electrode.The top electrode was sputtered onto the memristor by depositing 25 nm of Pd onto the sample.The resulting memristors are 200 × 200 μm 2 .It should be noted that the lateral dimensions of memristors fabricated using shadow masks are typically several orders of magnitude larger than those of memristors fabricated using microfabrication techniques such as photolithography and e-beam lithography [40][41][42][43].The effect the larger device footprint has on the device properties is principally observed in the device HRS value since the conduction mechanism for the HRS (Poole-Frenkel emission, space-charge-limited conduction, hopping conduction, etc) are proportional to the cross-sectional area of the device.When the memristor is in the LRS, the current flow is dependent on the cross-sectional area of the CF rather than the cross-sectional area of the memristor.This is a result of the CF, and consequently the current flow, being localized to an area that is on the order of a few nm in diameter.While this simplification of the fabrication process ignores the push for device miniaturization that is prevalent in the field, it provides a facile scheme to minimize the number of steps in the fabrication process while also allowing the relevant memristor parameters to be measured and evaluated following the device fabrication.
Electrical I-V measurements were performed using an Agilent B1500 semiconductor analyzer connected to 25 μm tungsten probes (Lake Shore ZN50R probes).The grounded tungsten probe was connected to the Pd electrode while the variable voltage probe was connected to the Al electrode.An initial low voltage sweep was performed (−500 mV to 500 mV) to determine the initial resistance of each memristor.An electroforming sweep (0 V to set voltage) followed by a reset sweep (0 V to reset voltage) was done to prepare the memristors for further electrical characterization.The HRS and LRS were measured by calculating the resistance of the memristor at 100 mV during subsequent positive voltage sweeps (reset voltage to set voltage) and negative voltage sweeps (set voltage to reset voltage).Since the electrode resistance was non-negligible, it was subtracted from the calculated LRS values.In order to avoid the complications of incomplete device setting or sneak paths in the circuit [44][45][46], the I-V measurements reported in this paper were taken on individual memristor devices with no compliance current applied to the I-V sweep.ALS contains a negligible amount of V O and does not exhibit resistive switching.Instead, the sample exhibits dielectric breakdown as its I-V curve shows in figure 2(c).Based on the work by Goul et al to achieve sustained memristive switching, a minimum of 3 MgO atomic layers are needed in a 1.9 nm thick ALS memristor and the first atomic layer at the Al electrode/M2 interface must be MgO [34].The memristors in figures 1(b)-(d) follow these two rules and provide adequate V O for memristive switching, as is observed in their I-V curves in figures 2(d)-(f).Nevertheless, the variety of the V O distributions in these 3 memristors affects how the CF initially forms and dynamically evolves through repeated resistive switches.Specifically, the ALS in figure 1  Interestingly, the LRS follows a similar decreasing trend as more MgO atomic layers are added to the Al 2 O 3 /MgO ALS memristors, increasing the V O quantity in the memristor.Note that the LRS measures the resistance of the CF formed during the memristive switch under the set voltage.If the resistivity of the CF (ρ CF ) and the length of the CF (L CF ) are assumed to be the same across all the memristors, this trend in the LRS may be attributed to an increase in CF radius (r CF ) as more V O are added to the ALS.It should be noted that both single CF and multiple CFs may occur during the 'Set' operation [29,47,48].In this case, the r CF should be considered as the radius of the equivalent single filament cf.

Results & discussion
In order to estimate r CF variation, Ohm's law was applied: LRS = (ρ CF L CF )/(πr CF 2 ), and the results for the devices to the right of the dielectric breakdown lines in figures , this increase in r CF is 109% when the number of the MgO layers is increased from three to five.This suggests a direct correlation between the CF size and the V O concentration and distribution.In particular, while a higher concentration of V O will increase the CF diameter, the magnitude of the change will be more significant at a lower doping concentration using the 1:2 MgO:Al 2 O 3 stacking ratio.The radii of the memristors is plotted and shows that with more V O in the ALS, the CF radius is expected to increase.Specifically, the r CF increases by 246% as the number of the number of MgO layers increases from three to eight layers.
Figure 6(a) compares the normalized r CF of six memristors with two selected from each of the three sets of Al 2 O 3 /MgO ALS memristors presented in figures 3-5.The three memristors presented in the red curve have 5 MgO atomic layers while the memristors represented by the blue curve have 3 MgO atomic layers.In the 3 MgO memristors there are no discernable trends with respect to the stacking pattern with comparable r CF values within 10%-15%.With the addition of more MgO layers in the 5 MgO memristors the resulting CFs are larger than CFs in the 3 MgO memristors.However, among the 5 MgO memristors, the 1:1 MgO:Al 2 O 3 and 1:2 MgO:Al 2 O 3 stacking ratios are within 15% of each other while the memristor with all five MgO layers at the ALS/Al interface has a larger r CF by 67% compared to the smallest r CF in the 5 MgO series, suggesting that the number of V O comprising the CF in this memristor is significantly larger than in the other memristors.This result can be understood by noting that the in vacuo ALD process used to fabricate these memristors minimizes non-V O defects in the oxide layer [33].The effects of increasing and decreasing the number of V O in the ALS can be observed in STS measurements of these films.In figure 6  A major difference can be seen in the I-V curves of the two devices as they undergo their set.In the first memristor, a one-step switch from HRS to LRS can be observed (figure 7(c)).This suggests that the CF forms in a single action, as depicted in figure 7(e).In contrast, the second memristor has multiple sub-steps between the HRS and LRS (figure 7(d)).While a systematic microstructure analysis is needed to fully understand the CF formation in this multi-step switching, we hypothesize the multistep CF formation may involve the connection of clusters of V O formed at or near the MgO layers.Under the applied SET voltage, the formed V O diffuse from the MgO layers and their subsequent connections lead to the multi-step switching as shown schematically in figure 7(d).Each new connection between V O clusters forms a longer partial ohmic pathway through the ALS.This process would result in the resistance decreasing, as seen in the I-V traces, via a number of sub-steps, incrementally transitioning from the HRS to the LRS once all connections are completed.Since these steps are seen in subsequent I-V cycles, as shown in figure 7(b), and pass through the same resistance steps in subsequent I-V sweeps, it would suggest that the filament forms in a similar fashion cycle after cycle.In addition, similar multi-step switching was also observed in the pulsed I-V measurement of the same samples, which confirms that there are more than just the HRS and LRS states in these devices.Intermediate resistance states with resistances between the HRS and LRS are observed through pulsed voltage measurements.This suggests that we can alter the state of the device to some in-between state that is neither fully set nor fully reset.It should be mentioned that while these sub-steps can be observed in any of the Al 2 O 3 /MgO ALS memristors studied, they are more frequently observed in memristors with many MgO atomic layers, and consequently many V O .When the V O are spread throughout the ALS, multiple segments of the CF may form and their sequential connections would result in sub-steps of switches from HRS to LRS, which may enable more complex algorithms in analog memristor-based neuromorphic circuits [51,52].

Conclusion
In summary, three sets of ultrathin 1.9 nm thick Al 2 O 3 /MgO ALS memristors were fabricated using the in vacuo ALD method by stacking 17 atomic layers of Al 2 O 3 and MgO together with different constituent numbers of V O doping MgO layers inserted in different positions of the ALS to investigate the effect of V O concentration and distribution on the memristor properties.Modular insertion of these MgO atomic layers into the otherwise pristine dielectric Al 2 O 3 ALS reveals several interesting observations.Firstly, sustained memristive switching, instead of dielectric breakdowns anticipated for pristine Al 2 O 3 ALS, can be obtained in Al 2 O 3 /MgO ALS with a minimum of three MgO layers inserted near the ALS/Al interface as the M2 layer of V O reservoir.This confirms DFT simulation prediction that MgO atomic layers may introduce V O doping in Al 2 O 3 and that the in vacuo ALD approach to eliminate unwanted defects allows the V O concentration and distribution in the Al 2 O 3 /MgO ALS to be tuned with atomic precision.Indeed, the memristor parameters such as R 0 , HRS, and LRS were found to be affected directly by the number of the MgO layers and their positions in the Al 2 O 3 /MgO ALS.In particular, the LRS exhibits a decrease with increasing numbers of MgO layers in three sets of Al 2 O 3 /MgO stacking sequences.Assuming only one CF forms during the HRS to LRS switches in these memristors and the formed CFs have the same length and resistivity, the trend in the LRS suggests that r CF increases monotonically with V O concentration.Finally, the distribution of V O has been found to affect the dynamic behavior of the memristor switches.Specifically, when a high concentration of V O is present with a uniform V O distribution pattern, substeps are more likely to appear during the HRS to LRS switch.This result is therefore important for the atomic tunning of ultrathin memristors with desired static and dynamic properties as required for practical neuromorphic circuits applications.

Figure 1 .
Figure 1.Row (i) exhibits diagrams of four different Al 2 O 3 /MgO ALS composed of 17 atomic layers consisting of Al 2 O 3 (blue) and MgO (yellow).Row (ii) shows how the interposing MgO layers contribute V O (red spheres) in the four different memristors.Column (a) shows a device made only of pristine Al 2 O 3 containing a negligible amount of V O .Columns (b) -(d) are memristors with V O introduced by inserting five MgO atomic layers at regular intervals into the oxide layer with an MgO:Al 2 O 3 spacing of 1:2 and 1:1 in (b) and (c), respectively.In (d) all the MgO layers are concentrated at the Al/ALS interface.

Figure 1
Figure 1 compares four examples of Al 2 O 3 /MgO ALS, each has 17 total atomic layers, resulting in a total ALS thickness of ∼1.9 nm.A few possible stacking sequences of the MgO and Al 2 O 3 atomic layers are exhibited in Row (i) of figure 1.These different ALS structures are composed of 17 layers of Al 2 O 3 (a), or 5 MgO and 12 Al 2 O 3 atomic layers with the MgO layers inserted at first, fourth, seventh, tenth, and thirteenth positions from bottom electrode (b), first, third, fifth, seventh, and ninth positions (c), or first, second, third, fourth, and fifth positions (d).Since the MgO atomic layers introduce V O into otherwise pristine Al 2 O 3 atomic layers with negligible V O and other defects, the concentration and distribution of V O in the Al 2 O 3 /MgO ALS are predicted by DFT simulation [34] to be determined by number and location of the MgO layers, as shown schematically in Row (ii) of figure 1.Figure 2(a) exhibits the optical image of a representative crossbar array of memristors investigated in this work.The cross-sectional view of a memristor is shown schematically in figure 2(b) with an Al bottom electrode (pink) and Pd top electrode (silver) sandwiching the active oxide layer.The I-V sweeps for the four memristors presented initially in figure 1 can be seen in figures 2(c)-(f).Specifically, without any MgO layers (figure 1(a)) the

Figure 2 (
Figure 1 compares four examples of Al 2 O 3 /MgO ALS, each has 17 total atomic layers, resulting in a total ALS thickness of ∼1.9 nm.A few possible stacking sequences of the MgO and Al 2 O 3 atomic layers are exhibited in Row (i) of figure 1.These different ALS structures are composed of 17 layers of Al 2 O 3 (a), or 5 MgO and 12 Al 2 O 3 atomic layers with the MgO layers inserted at first, fourth, seventh, tenth, and thirteenth positions from bottom electrode (b), first, third, fifth, seventh, and ninth positions (c), or first, second, third, fourth, and fifth positions (d).Since the MgO atomic layers introduce V O into otherwise pristine Al 2 O 3 atomic layers with negligible V O and other defects, the concentration and distribution of V O in the Al 2 O 3 /MgO ALS are predicted by DFT simulation [34] to be determined by number and location of the MgO layers, as shown schematically in Row (ii) of figure 1.Figure 2(a) exhibits the optical image of a representative crossbar array of memristors investigated in this work.The cross-sectional view of a memristor is shown schematically in figure 2(b) with an Al bottom electrode (pink) and Pd top electrode (silver) sandwiching the active oxide layer.The I-V sweeps for the four memristors presented initially in figure 1 can be seen in figures 2(c)-(f).Specifically, without any MgO layers (figure 1(a)) the

Figure 2 .
Figure 2. A representative optical image of a set 200 × 200 μm 2 of memristors is shown in (a).A schematic view of the memristors is shown in (b).The bottom Al electrode (pink) is 10 nm thick and the top Pd electrode (silver) is 25 nm thick, both sandwiching the ∼1.9 nm thick active oxide layer.I-V measurements from the samples in figure 1 are shown in (c)-(f).The device made with only pristine Al2O3 is shown in (c) and undergoes dielectric breakdown.Memristors with an MgO:Al 2 O 3 staking ratio of 1:2, 1:1, and 1:0 are shown in (d) -(f), respectively, and exhibit resistive switching.

Figure 3 .
Figure 3.The initial resistance R 0 (black), HRS (blue), and LRS (red) for Al 2 O 3 /MgO ALS memristors are plotted.The memristors with an MgO:Al 2 O 3 stacking ratio of 1:2 are plotted in (a) and those with a ratio of 1:1 are plotted in (b).Memristors with fewer than 3 MgO atomic layers did not commonly exhibit sustained memristive switching and experienced dielectric breakdown, indicated by the black vertical lines in (a) and (b).
3(a)-(b) are exhibited in figures 4(a)-(b), respectively.For the 1:1 MgO:Al 2 O 3 ALS memristors in figure 4(a), the r CF increases by 44% as the number of the MgO layers is increased from three to six.However, for the 1:2 MgO:Al 2 O 3 ALS memristors shown in figure 4(b)

Figure 5
compares an additional set of Al 2 O 3 /MgO ALS memristors with an MgO:Al 2 O 3 stacking ratio of 1:0 for the M2 layer.This results in all the MgO layers being added to the memristor at the electrode/M2 interface

Figure 5 .
Figure 5.The R 0 (black), HRS (blue), and LRS (red) for Al 2 O 3 /MgO ALS memristors with a variable number of MgO atomic layers at the ALS/Al interface is plotted (a).The corresponding normalized r CF of the memristors is shown in (b).
with no Al 2 O 3 separating the MgO layers.The memristors studied in figure 5(a) contain 3, 5, and 8 MgO layers, respectively, and shows a decrease in the HRS and LRS, similar to what has been seen before.While the memristors are still 17 atomic layers thick, Al 2 O 3 is only present in the M1 layer immediately above the MgO layers.This construction of the memristors explains the significant decrease of the HRS since as the number of MgO layers is increased an equivalent decrease in the number of Al 2 O 3 layers in the M1 layer occurs.Also, the inverse realtionship between the LRS and the number of MgO layers in the ALS memristors observed again.The corresponding CF radii are shown in figure 5(b).
(b) a stack of Al 2 O 3 10 ALD cycles thick exhibits a tunnel barrier of 1.76 eV.This is comparable to the tunnel barrier of 1.45 that is shown in figure 6(c) which is only 9 ALD cycles thick but has 3 MgO layers distributed in the 1:2 MgO:Al 2 O 3 stacking pattern.This suggests that it is still possible to include MgO ALD layers and still have a high quality, insulating oxide layer.If all 10 ALD cycles deposited on the electrode are MgO layers then the barrier height falls to 1.23 eV, as seen in figure 4(d), which suggests that the MgO layers grown on the Al form a more defective film than the Al 2 O 3 ALD films, contributing significantly to the amount of V O in the memristor [49].This is corroborated by work done by Acharya et al and Goul et al that showed that interposing just a single Al 2 O 3 ALD layer between the electrode and the first MgO layer significantly decreased the number of V O in the oxide layer [49, 50].

Figure 6 .
Figure 6.A comparison of how the filament size changes with the MgO:Al 2 O 3 stacking ratio is shown in (a).Memristors with 3 MgO layers are depicted in the blue trace and memristors with 5 MgO layers are represented by the red trace.Representative scanning tunneling spectroscopy dI/dV plots are shown to demonstrate change of the Eb in the MgO/Al 2 O 3 ALS of ∼1 nm thickness with (b) 10 cycles of Al 2 O 3 , (c) 9 ALD cycles with MgO layers inserted into the first, fourth, and seventh positions and (d) 10 cycles of MgO.

Figure 7 .
Figure 7. I-V curves measured on two Al 2 O 3 /MgO ALS memristors: one with 3 MgO layers located near the ALS/Al interface exhibiting single step switching (a) and the other with 7 MgO layers spread more uniformly through the oxide layer exhibiting multistep switching (b).A zoomed in view of a single I-V set from the 3 MgO (c) and 7 MgO (d) memristors highlights the switching mechanism.Potential single step and multi-step mechanisms are depicted in (e) and (f), respectively.