In-situ S/TEM DC biasing of p-GaN/AlGaN/GaN heterostructure for E-mode GaN HEMT devices

This work describes an in-situ electrical DC bias study of the E-mode GaN high electron mobility transistor (HEMT) device. A single transistor structure is biased and studied in real-time. The sample was made from an E-mode GaN HEMT device using Focused Ion Beam (FIB) milling and upright lift-off. The device lamella is subjected to forward gate bias to understand the device operation and physical changes under the bias. Active device area and micron level changes due to biasing were studied and identified as crucial factors affecting device reliability during continuous operation. Electric bias-induced physical changes are observed at the p-GaN layer and AlGaN interface on the p-GaN and GaN sides. Localized damage and defect formation, along with elemental diffusion, is observed. The formation of new defects over existing growth defects was seen in the p-GaN/AlGaN/GaN heterostructure. The study helped us identify the exact location of the failure, the region affected under bias, and the occurrence of physical changes due to the electrical bias on the in-situ device. Based on the study, gate breakdown failure and its location at the metal/p-GaN interface are understood to result from physical changes activated by electrical bias.


Introduction
The physical integrity of the p-GaN gate in E-mode GaN HEMT devices is one of the dictating factors of its operations, reliability, and failure mechanism.Hence, to understand the reliability of E-mode GaN HEMTs, it becomes essential to investigate the participation of physical failure in the gate breakdown mechanism.Considerable research has been done on the gate reliability studies involving time-dependent dielectric breakdown (TDDB) studies [1,2], voltage and temperature influence on gate breakdown mechanisms [3], simulation to show the contribution of charge leakage under E field at the gate [4], based on device geometry and doping [1,5], a correlation of lifetime to operating voltages and current to define breakdown mechanism for gate failure in p-GaN E-mode GaN HEMTs [1].To add a significant step to this list, we aim to present the physical breakdown of the gate by using a real-time study done on a micro-level device studied in TEM.A handful of studies presented in [6][7][8][9][10] have been on the in-situ TEM biasing of AlGaN/GaN HEMT devices.Our study is on E-mode GaN HEMT with a p-GaN gate configuration.Also, we want to limit the current flowing through the in-situ device to minimize surface leakage for precise identification of failure.We have presented the initial study of p-GaN E-mode GaN HEMT device [11] in-situ biasing using a W probe [12].Our prior in-situ work was carried out on the Gate-Source design of lamella, and the current work is based on the Gate-Drain structure.The lamella was on the Cu grid and a Nanotechnology holder apparatus assembly.This recent work presents the E-mode GaN HEMT, where p-GaN/ AlGaN/GaN heterostructure is studied in in-situ DC biasing over an e-chip to observe gate breakdown.
This study investigates the direct correlation of electrical biasing to physical changes occurring at the gate region to strengthen the knowledge of gate failure breakdown in p-GaN gate E-Mode GaN HEMT devices.The sample design and in-situ experiment are unique approaches to studying reliability as we focus on the gate area during gate biasing in real time.Nano-level to micron-level changes can be observed in real-time using aberration-corrected scanning transmission electron microscopy (STEM).Metal/p-GaN junction is a Schottky contact, and when bias is applied on the gate, the highest E field is generated across the gate stack [13].With the acceptor doping of the p-GaN cap, the space charge layer (SCL) formed on the inside of the p-GaN layer extends with increasing bias.GaN is known to suffer physical stress under the reverse piezoelectric phenomenon [14].Thus, focusing on the gate stack, where most of the deformation is expected, becomes essential.
We aimed our work to present an in-situ device preparation and the physical changes occurring in the active region of the p-GaN gate E-Mode GaN HEMT device.Lamella was made into an in-situ TEM sample from a packaged device, and the lamella was fabricated into a lift-off sample using FIB.The lamella was made electron transparent, and electrical connections were made.E-mode GaN HEMT lamella was biased in TEM.We see the lamella retaining its transistor properties during biasing.The gate region shows signs of defect deformation under bias.The defect formation is concentrated around the gate stack.The p-GaN/AlGaN/GaN heterostructure shows extensive damage.We observed a nano-crack in the metal/p-GaN junction and drain/ metal contact.Our study reports the prospective physical changes occurring at the p-GaN gate of E-mode GaN HEMT under electrical bias.

Methodology
This study used an in-situ TEM holder from the ProtoChips Audro model, capable of in-situ electrical and heating measurements [15].The sample was prepared from an etched and de-capped device [11] using the focused ion beam (FIB) lift-out method, consisting of the gate, drain, and substrate, which was lifted out and transferred to an electrical-biasing chip (Protochip Fusion e-chip) [15] with the help of a probe.The sample was carefully milled to expose the metal/p-GaN and metal/drain contacts for biasing.The basic schematic of the e-chip, lamella, and gate stack is shown in figure 1.The electrical circuit connection was made using Platinum (Pt) deposition to connect the metal/p-GaN junction to the no. 1 lead, as shown in figure 1(b).Similarly, the drain metal contact was exposed and connected to lead no. 4 using Pt deposition.After making the electrical connections for the respective gate and drain connects, the sample is thinned using low power, 20 kV and 37 pA ion beam in FIB, followed by cleaning at 5 kV and 29 pA ion beam.
Keithley SMU model 2610 was used to bias and sense the current through the e-chip.The lamella and e-chip assembly are carefully placed on the Proto-chip holder.Outcoming connectors from the holder for the gate (1) and drain (4) were connected to the high and low of the SMU, respectively.Figure 1(a) shows the circuit's electrical design.The idea is to bias only the gate and record the gate current flowing in from the metal/p-GaN gate contact and drain/metal contact via a channel.It is essential and of utmost importance to have an excellent electrical circuit to avoid surface charges, discharges because of Pt deposition, and unwanted current leaks.The holder assembly, i.e., e-Chip and the sample, is placed inside the TEM chamber.After assessing the connectivity of the electrical circuit and initially focusing on the sample, the in-situ experiment is started.

Results and discussion
The gate is forward biased with consecutive sweeps from 0 to V, with increments of +1 volts from 0 to V, with steps of 20 mV.The corresponding current flowing from the device is recorded, shown in figures 2(b) and (c).The device shows no physical change during the low-voltage biasing.The curvature of current data shows transistor-like behavior with a gate-controlling 2-DEG channel in the sample [11].This also suggests that the gate contact and meta/p-GaN junction retain their Schottky nature.However, the lamella is conducting a considerable amount of current, which could be due to the aspect ratio of the nanostructure of the GaN HEMT device.A study done on GaN Nano-wire structure showed a 1000-time higher current in GaN nano-rod structures due to factors like piezoelectric charge, image charges, and strain on the GaN [16].As the forward bias voltage increases during the sweep, the gate area of the sample is kept in focus and observed in real-time.
Figure 2(a) shows the device's active area in the study, with the Pt probe as the metal connector of the metal/ p-GaN junction.No visible change is seen in the active regions of devices up to the gate bias of 6 V.As seen in figure 2(b), the current shows serrations during the 0-7 V sweep, which is the first sign of degradation in the gate and its proximity.During the bias application, the highest voltage drop is across the Schottky contact of the metal/p-Gan junction [13].As a result, the E y component of the E field developed in the device is highly concentrated at the gate stack.Thus, the E field developed in the gate region increases with an increase in voltage.In addition to that, the space charge layer (SCL) of acceptor dopants in the p-GaN expands in the AlGaN layer and towards the GaN region due to the increasing positive bias.As a result, the charge injecting from the gate, under the influence of the E field, will gain momentum and have enough energy to create defects in the gate stack of the p-GaN gate in the E-Mode GaN HEMTs.
Figure 3 shows the HAADF STEM images of the gate stack area.During the 0-7 V sweep, we see a contrast change below the GaN region's gate stack, as seen in figure 3. Contrast change is due to defect formation because of the stress generated in the gate region of the device.The formation of defects in the gate region and its proximity strongly supports the idea that the applied electric stress induces physical deformation during biasing, and it is similarly applicable to the packaged device when stressed under normal conditions during ex-situ operation [11].As mentioned above, the serration observed on the recorded current, shown in figures 2(b) and (c), implies physical changes occurring in the current path.It is followed by a sharp drop in the current during the 0-7 V forward bias sweep, accompanied by dark contrast in the p-GaN layer and distortion just below the AlGaN/GaN interface, as seen in figure 3(b).Furthermore, the sudden drop in recorded current suggests heavy damage in the sample, terminating the electrical connectivity in the in-situ p-GaN gate E-Mode GaN HEMT sample.As we know, the TEM sample lamella is electron beam transparent.GaN is known to undergo the reverse piezoelectric effect [14], in which the generated E field could result in mechanical stress on the sample because of bias.The stress generated because of the E-field may not be sufficient to induce plastic deformation [17].Still, it can add strain to form a defect in the device's active region [17].The defect can act as a charge scattering center, increasing the resistance to charge flow, and we can see localized damage because of increased current density.Severe changes are seen in the sample in the gate area.
Figure 4 shows the device channel area after the electrical-biasing sweep.As the bias is applied solely to the gate, the E field generated during bias is concentrated at the gate cap.The E y component of the field stresses the mismatched AlGaN/GaN interface.The E field may not be able to deform the bulk of the lamella physically, but it can form defects.A defect in the AlGaN barrier layer can increase the resistance to charge flow and lead to localized heating.
Furthermore, with the lattice mismatch and residual strain, we see the diffused interface between p-GaN/ AlGaN and AlGaN/p-GaN.It is noted that the pristine device has sharp and coherent interfaces.Biasing induces stress on the already strained interfaces, and as a result, we see discontinuity at the interfaces.Also, we have a 2-DEG channel at the AlGaN/GaN heterostructure, and charge movement could add more stress to the already strained interface.Figure 4 shows that interface continuity, crystallinity, and distinction of interface layers have deteriorated during the sweep.All three effects work together, making the gate stack susceptible to severe damage during continuous operation [11].    in the p-GaN region.Localized heating will promote elemental diffusion as the sample is thin.Elemental diffusion can also be due to high gate bias and current.
After a detailed analysis of the gate region and channel, we further investigated the drain side of the device, as the current path is from the metal/gate junction to drain through 2-DEG formed in the AlGaN/GaN channel.The sample's drain side shows an electric discharge crack that strengthens the argument of the current path going through the drain metal contact.Figure 6 shows a dark contrast in the drain metal, suggesting heavy localized elemental diffusion in the metal contact.Also, carefully studying the drain region, we see a 2 nm thick crack at the metal contact/drain interface.Figure 6(c) shows a dome-shaped contrast accompanying the crack on the interface's metal side.This shape contrast suggests the flow of charge inside the metal contact.

Conclusions
We successfully tested device lamella consisting of gate-drain structure made from packaged E-mode GaN HEMT devices by real-time in-situ electrical biasing in Transmission Electron Microscope.We found that the electrical stress generated due to biasing initiates physical change in the device.Based on the data presented, gate breakdown is a physical failure because of the electrical stress on the gate caused by gate biasing.The E-field is translated to physical stress because of the reverse piezo-electric effect and is responsible for strain in the mismatched lattices of p-GaN/AlGaN and AlGaN/interfaces.This results in structural deformation, confirmed by defect formation and non-continuously diffused interfaces at the p-GaN/AlGaN/GaN heterostructure.We see elemental diffusion under the influence of the E field during forward bias.Ga Elemental diffusion led to charge leakage paths and made the GaN lamella lose its intrinsic property to withstand high E-field.High current density leads to localized heating and Ga atom diffusion from the GaN/AlGaN layers.We conclude that gate failure is the physical degradation of gate assembly because of electrical operation and high gate bias, and failure is observed at the metal/p-GaN interface and the AlGaN/GaN interface.

Figure 1 .
Figure 1.(a) Outline of the lift-out sample attached on e-chip for in-situ biasing experiment and (b) SEM image of the sample showing the Gate/Drain connected to the leads (1) & (4) with Pt. and (c) magnified STEM High Angle Annular Dark Field (HAADF) image of the gate stack.

Figure 2 .
Figure 2. (a) STEM high angle annular dark field (HAADF) image of the sample before biasing, (b) and (c) are the forward bias sweep plots performed on two different samples.

Figure 3 .
Figure 3. STEM HAADF images of gate stack (a) at 7V of 0-7V forward gate bias sweep and (b) magnified image of the spot-like feature shown in (a), and (c) is the high-resolution image of the crack beside it.

Figure 4 (
a) shows a bright spherical contrast and distorted contourlike accumulation starting from the AlGaN/GaN interface.The bright contrast in the middle of the AlGaN layer indicates the diffusion of a high atomic element.Based on the Z contrast in figures 4(a) and (b), this could either mean Ga leaving out of the AlGaN layer or infusing in the AlGaN layer from the Ga-rich GaN region.The STEM HAADF imaging is based on the atomic number Z-contrast of the sample, and the bright-dark contrast of patches indicates elemental non-homogeneity.This also suggests diffusion is observed majorly around the AlGaN/GaN interface.

Figure 5
represents the EDS line scan data showing the Ga and Al-rich regions at the dark contrast.Ga may diffuse under the high current density and E field generated due to the Schottky junction at gate contact and SCL

Figure 5 .
Figure 5. (a) STEM ABF Images showing line scan trace, and (b) is the EDS intensity profile for the line scan.