Carbon nanotube integrated circuit technology: purification, assembly and integration

As the manufacturing process of silicon-based integrated circuits (ICs) approaches its physical limit, the quantum effect of silicon-based field-effect transistors (FETs) has become increasingly evident. And the burgeoning carbon-based semiconductor technology has become one of the most disruptive technologies in the post-Moore era. As one-dimensional nanomaterials, carbon nanotubes (CNTs) are far superior to silicon at the same technology nodes of FETs because of their excellent electrical transport and scaling properties, rendering them the most competitive material in the next-generation ICs technology. However, certain challenges impede the industrialization of CNTs, particularly in terms of material preparation, which significantly hinders the development of CNT-based ICs. Focusing on CNT-based ICs technology, this review summarizes its main technical status, development trends, existing challenges, and future development directions.


Introduction
Over the past half-century, the chip industry has progressed significantly due to Moore's law (the integration of chips doubling every 18 months), which has profoundly changed the pattern of people's lives and industries.During this transformation, the rapid iteration of new technologies constantly refreshes the technical nodes of Si-based chips, thereby surpassing Moore's limits in several cases.However, in the Original content from this work may be used under the terms of the Creative Commons Attribution 4.0 licence.Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI.second decade of the 21st century, the development speed of the chip process decreased significantly, mainly because the scale of Si-based field-effect transistors (FETs) approached the physical limitations [1,2].Currently, benefiting from advanced technologies such as extreme ultraviolet lithography, the mature manufacturing process has entered the 4 nm technology node, and the industry is evolving to the 3 nm or even 1 nm node.Each step forward incurs significant costs and requires a longer time to understand the core technologies.Moreover, merely relying on enhancing manufacturing techniques to improve the performance of Si-based chips cannot fully satisfy the current demands [3][4][5].
According to the latest International Technology Roadmap of Semiconductor (ITRS) [6], the short-channel effect becomes increasingly concerning as the technology node approaches its physical limits, as it results in the failure of  [30].Copyright (2014) American Chemical Society.microelectronic devices to follow the principles of traditional semiconductor physics [7].Hence, the potential of Si-based chips is almost exhausted [8], and Moore's law is no longer applicable.New materials and manufacturing methods are internationally recognized methods for fundamentally solving problems associated with chip performance, whereas carbonbased semiconductors are considered disruptive technologies in the post-Moore era [9][10][11][12][13].
Carbon-based electronics has been developed based on sp 2 carbon materials, that is carbon nanotubes (CNTs) [14][15][16] and graphene [17,18].However, graphene is not applicable as a channel material in ICs because of its absence of a band gap in its natural state [19].Compared with graphene, CNTs not only have excellent transport properties, but also have adjustable band gaps [20], which renders them more competitive as the next-generation ICs material.In terms of the performance of ICs [21,22], CNTs offer excellent transport properties, which are afforded by their ultrahigh carrier mobility and long average free path, thus allowing the realization of ballistic transport [23].Benefiting from their one-dimensional nanometer size and ultrathin body (one atomic layer thickness), the superior electrostatic properties of CNTs render them to be controlled more easily via the gate voltage.Research shows that the overall performance of CNT transistors can reach five times that of silicon [24], and if three-dimensional chips are realizable, then the performance of CNT-based ICs can theoretically reach thousand times higher [25,26].The ITRS highlighted that future research by the semiconductor industry should focus on carbon-based electronics and that CNTs are expected to become alternative materials for the next generation of very large scale integration circuit (VLSI) [27][28][29].
Furthermore, researchers reported that CNT-based FET (CNT FET) significantly improved electrical performance and energy consumption compared with silicon [30].For Si-based FETs scaled from 7 nm to 5 nm, the corresponding chip performance increased by approximately 20% (figure 1).By contrast, the performance of CNT-based chips under 7 nm technology nodes is three times higher than that of Si-based chips, which is equivalent to the improvement of the 15th generation of the latter; therefore, academics predict that the dominance of the Si chip industry will be terminated by the utilization of CNTs [31].
Currently, CNT-based transistors are expected to approach the performance limit determined by the laws of quantum mechanics and thermodynamics defined through continuous technical research [32], which demonstrates the significant potential of CNT electronics [33,34].According to researchers at the IBM Watson Research Center, the process for manufacturing high-performance ICs comprising CNTs will be different from the current lithography process of Si (figure 2) [31].A purification above 99.9999% of semiconductor CNTs (s-CNTs) must be strictly controlled, and CNTs in channels should be densely aligned with a density exceeding 125 tubes•µm −1 such that the performance of CNT-based transistors can exceed that of Si (figure 3).However, according to the latest international reports [35,36], significant challenges remain that hinder the development of CNT chips.Therefore, this review summarizes the recent progress of s-CNT purification, the regular assembly and cross-scale manufacturing of ICs, and the prospects for the manufacturing technology of CNT-based ICs.

Preparation of s-CNTs with high purity and high yield
The intrinsic properties of CNTs are affected significantly by their chirality.Structurally, CNTs can be viewed as a single sheet of graphite seamlessly curved along a certain direction to form a tubular structure [37].And the chiral coefficient (n, m) characterizes the wrapping direction and determines the size of the wrapping angle.Due to the fact that different electronic properties exhibited by CNTs strongly depend on the wrapping angle, researchers typically use chiral coefficients to characterize certain types of CNTs.Specifically, when n = m, CNTs have bands crossing the Fermi level and are therefore metallic.And these particular CNTs are called armchair tubes.The remaining types exhibit two possibilities.When n-m = 3 l (where l is an integer), tubes are also expected to be metallic.In the case n-m ̸ = 3 l, tubes are predicted to be semiconducting [38].
Purification is the process of controlling the range of chiral coefficients of CNTs.In terms of the yield in chips highlyintegrated manufacturing, the proportion of s-CNTs in FET channels should be extremely high (>99.9999%) to prevent circuit failure.Furthermore, from the perspective of high performance and stability of CNT FETs, the ultimate goal of carbon-based technology is to achieve the purification of chirality-specific tubes [39].However, it is difficult for current mainstream methods to obtain the chirality-specific tubes with high purity, and the results are usually less than 99% [40].But for certain methods, s-CNTs with ultra-high purity (>99.99%)can be obtained, and only a few chiral coefficients exist.
Generally, high-quality s-CNTs are mainly purified via chemical vapor deposition (CVD) and solution methods.Research shows that chirality-specific CNTs can be synthesized via CVD, but the chiral purity is far from meeting the current requirements of VLSI manufacturing [41].Moreover, based on the results achieved in existing research, the solution method has already taken the lead.Solution methods can be classified into three main categories: aqueous systems based on surfactants, organic systems based on polymers, and aqueous two-phase systems.The solution method offers significant advantages for the preparation of ultrahighpurity s-CNTs and is expected to benefit CNT-based VLSI manufacturing.
Surfactants such as sodium dodecyl sulfate (SDS) [42] and sodium dodecyl benzene sulfonate (SDBS) [43,44] can effectively disperse CNTs in aqueous solution.Notably, surfactants exhibit extremely low selectivity for different types of CNTs.After suspension formation, density gradient ultracentrifugation (DGU) [45] or column chromatography [46,47] is generally performed to further purify CNTs.Arnold et al first used the DGU method to classify CNTs [48], where single-stranded DNA and iodine octanol were used as the surfactant and density gradient medium, respectively.Under a long duration of high-speed centrifugation, the CNTs were layered in the solution based on their diameters.This study achieved a high purification efficiency for small-diameter s-CNTs, and the chiral types were (6,5), (9,1), and (8,3).Subsequently, Weisman's group improved the DGU method using a customized S-shaped gradient centrifuge tube [49], as shown in figure 4.This centrifuge tube had a very shallow gradient and was nonlinear.Under the action of an ultrahigh centrifugal force, even CNTs with insignificant chirality differences can be separated, thus significantly improving the resolution accuracy of the chirality.Using this method, researchers extracted up to 10 types of chiral s-CNTs from HiPCo carbon tubes, with diameters ranging from 0.7 nm to 1.1 nm and the highest purity of 88%.
Nish et al used conjugated polymers for the separation of metallic/semiconductor CNTs in 2007 [50].Conjugated molecules such as polyfluorene [51,52], polycarbazole [53], and polythiophene [54,55] can spirally wrap the outer walls of s-CNTs to form a stable assembly in the solvent.They exhibit ultrahigh selectivity for specific types of CNTs depending on their side chains and bodies (figure 5).
In 2017, Gu et al reported the purification of CNTs using the linear homopolymer poly[9-(1-octylonoyl)-9 H-carbazole-2,7-diyl], denoted PCz [56].Mixed CNTs and PCz molecules were subjected to mild ultrasonication and high-speed centrifugation in toluene.In the supernatant, the purity of s-CNTs exceeded 99.9%, and their average diameter was approximately 1.3 nm, based on spectral measurement.Hence, this group proposed an enhanced ultracentrifugation method (E-UCG) and a stepwise extraction processing method (STEP) in 2022 [57].To increase the chiral selectivity, CNTs were dispersed successively using two types of copolymers with intersections in the chiral selection range.Under ultrahigh centrifugal forces (650 000 g), the instability of the assembly formed by different chiral CNTs and polymers was amplified to achieve maximum purification.In this study, (10,8) chiral tubes with purities of 92.3% and (12,5) chiral tubes with purities of 95.6% were obtained, both of which featured diameters exceeding 1.2 nm, and the proportion of s-CNTs in the solution exceeded 99.94% (figure 6).
Subsequently, Liu et al improved the efficiency of PCz using a multiple dispersion and sorting process [58].Considering that dispersion effects depend on solvent selection [59], this method uses vacuum filtration to transfer the solvent environment during purification.The assembly of CNTs and polymers was successively subjected to ultrasonic tip and high-speed centrifugation in toluene, tetrahydrofuran, and trichloroethane.Finally, s-CNTs with a purity exceeding 99.9999% were obtained, which satisfied the level required for chip manufacturing.
The aqueous two-phase separation method [60][61][62][63] effectively extracts single-chiral CNTs.The principle is that the assembly of chiral CNTs and dispersants can form different distributions in the two liquid phases owing to their different hydrophilicities.Fagan et al separated up to 10 types of chiral CNTs in a PEG/DX aqueous two-phase system with mixed surfactants, and the diameters obtained were less than 1 nm [64].The result of the study showed that surfactant concentration significantly affected the separation result.For the SDS/SC combination, maintaining a constant concentration of SC and increasing the concentration of SDS can facilitate the separation of metal/semiconductor CNTs.This group used the same method to separate s-CNTs with diameters exceeding 1.3 nm in 2015 [65].
In addition, aqueous two-phase systems can be used in conjunction with DNA as a dispersant (figure 7).Ao et al systematically screened more than 300 DNA sequences and separated 23 types of single chiral CNTs, which included almost all chiral ranges [66].However, the abovementioned studies did not quantitatively analyze the purity of the separated singlechiral CNTs or s-CNTs.Based on a literature review of studies pertaining to digital supports, the maximum purity of s-CNTs achieved by an aqueous two-phase system was 99.56%.
Based on previous reports and actual results achieved in recent years, purification based on polymers has gradually become the mainstream method [67] and satisfies the manufacturing standards for CNT-based chips.However, for highly scaled CNT transistors, controlling the single chirality of CNTs remains challenging [68].In the future, new types of conjugated polymers must be identified and the purification process must be optimized.Additionally, the progress of the related equipment should be considered.
In addition to purifying s-CNTs during the preparation and dispersion processes, some effective auxiliary methods can be used to further improve the purity of CNTs after they are placed on a substrate.
Rogers et al evaporated a thermosensitive adhesive spincoated on the surface of mixed CNTs via Joule and microwave heating, which exposed the metallic CNTs underneath, and directly removed them via dry etching [69,70], as shown in figure 8.The authors reported that this method improved the purity of s-CNTs to a certain degree.However, in some cases, metallic and semiconductor CNTs aggregated to form bundles, and the thickness of the thermosensitive adhesive was not completely uniform; therefore, the metallic CNTs will not be completely removed.
In future research based on commercial high-purity s-CNTs, these purification methods should be enhanced using other innovative methods to maintain the performance advantages of CNT-based ICs.

Large-scale and regular assembly techniques of CNT arrays
To fabricate CNT-based ICs, disordered CNTs must be rearranged to be placed into aligned arrays on a wafer scale, with the density of the CNTs satisfying certain requirements.IBM researchers proposed densifying CNTs to more than 125 tubes•µm −1 and controlling their inter-tube pitch to 5 ∼ 10 nm to achieve state performances better than those of Si-based transistors [72].
High-density aligned CNTs can be prepared via CVD, where the lattice of the selected specific substrate promotes directional growth [73].However, according to recent studies [74][75][76], this method fails to achieve the high purity and density required for CNT-based chip manufacturing.Meanwhile, solution methods dominate material preparation.This is because it allows ultrahigh-purity semiconductor CNTs to be directly used for alignment and specific assembly methods to be used based on the solution environment.Moreover, the solution method achieves a more effective arrangement, thus enabling a density of >125 tubes•µm −1 or even 400 tubes•µm −1 [71] of CNTs.Currently, the solution method is the mainstream method for the large-scale assembly of CNTs, including the Langmuir-Blodgett (L-B) and Langmuir-Schaefer (L-S) methods [77], the pull-up assembly of two-liquid phases [78,79], templateinduced self-assembly [80][81][82], evaporation-driven assembly [83,84], and vacuum filtration [85][86][87].The first three methods have progressed significantly in recent years, and CNT alignment can reach the wafer scale through process optimization.
L-B and L-S assemblies are film-assisted methods based on aqueous two-phase systems.When amphiphilic molecules dissolved in a volatile solvent are spread on the water surface, a Langmuir film composed of a single molecular layer can be obtained under the surface tension of water, which can then be transferred via vertical dip-coating or horizontal self-evaporation.This is also the basis for distinguishing the L-B and L-S methods.Clearly, the L-B method is suitable for the assembly of large quantities of CNTs.The key is to ensure the stable dispersion of CNTs in organic solvents and the application of an appropriate lateral force.Li et al [77] used pmpv to modify CNTs noncovalently, thus realizing the solubility of CNTs in 1,2-dichloroethane solutions and the successful construction of a Langmuir thin film on a water subphase.
In 2014, Cao et al used the L-S method to arrange CNTs [71], where a more stable horizontal transfer was achieved using the aligned arrays formed (figure 9).This study focused on the noncovalent modification of pmpv; however, prior to its use, s-CNTs were purified using SDS and DGU.The results show that the density of CNTs can reach more than 500 tubes•µm −1 and the degree of aligned arrays can be controlled within 17 • with the entire wafer covered with CNTs.This packing density is more than three times higher than the standard value of 125 tubes•µm −1 proposed by IBM researchers, which is overly exaggerated.However, it directly results in an unreasonable distribution of intertube spacing, with a van der Waals gap of only 0.2 nm remaining between the CNTs.The screening effect among neighboring CNTs was magnified, which caused the transistor performance to deteriorate.The on/off ratio was only approximately 10 3 , and the on-state current was 120 µA•µm −1 .
Although the L-B assembly enables ultrahigh intensity, it does not offer a reasonable intertube pitch distribution.Furthermore, its 'film forming before transfer' mechanism results in a highly unstable assembly; thus, this assembly method should be further improved.Herein, a similar assembly method is described, namely, the pull-up assembly of two liquid phases, which can be considered as an extension of the L-B method.The pull-up assembly was first used in the 'dose control, floating evaporative self-assembly (FESA)' strategy proposed by Arnold's group from the University of Wisconsin [89].Researchers applied a chloroform solvent containing s-CNTs inks to an L-B trough sequentially and simultaneously withdrew the target substrate from the surface of the water at a low rate.Each aliquot of ink spread rapidly across the water surface, which was then confined and retrieved at the ink/water/substrate contact line.The restricted CNTs were aligned in arrays via tangential flows, which resulted in a packing density of approximately 50 tubes•µm −1 and a linear angle not exceeding 14 • .However, because the ink in the FESA was discontinuous, the stripes of the aligned CNTs were separated by randomly oriented components, which hindered a complete coverage of CNTs.
Compared with the L-B method, the pull-up assembly does not require the application of an axial force to ensure the alignment of CNTs.In this method, several different factors contribute to the linear arrangement of CNTs.The limitation of the interface and the relative motion between the substrate and liquid are key factors that enable more parameters to be controlled to improve the alignment effect.Hence, the researchers from Arnold's group investigated the FESA method more thoroughly [88].They discussed the effects of the ambient temperature, ink concentration, and flow rate on the alignment, as well as used a more effective pull-up process for the two substrates.A pair of parallel target substrates and barriers were used to form a channel that for guiding and controlling the continuous flow of ink more effectively.Finally, an alignment of nanotubes with a linear density exceeding 100 tubes•µm −1 on the entire wafer was realized (figure 10).
Furthermore, the pull-up assembly of the two liquid phases is not limited to this dynamic ink-dropping method.Peng's group [58] developed the 'dimension-limited self-alignment (DLSA)' method, where well-aligned CNT arrays (within alignment of 9 degrees) were prepared with a tunable density of 100-200 tubes•µm −1 .In this method, trichloroethane and 2-butene-1,4-diol (C 4 H 8 O 2 ) were selected as the liquid phases of the lower and upper layers, respectively.Hydrogen bonds can be formed at the liquid-liquid interface, which restricts the nanotubes to the interface region such that they can be assembled in alignment along the contact line when the substrate is pulled out.During this procedure, the relatively static liquid phases continuously supply nanotubes to the contact line between the liquid phase and the substrate, which realizes a full coverage on the target substrate (figure 11).
In general, the alignment results achieved by the pull-up assembly of the two liquid phases satisfy the requirements of CNT-based chips, based on both the size and packing density of the CNTs.However, this method depends significantly on the type of dip-coating device used.To realize a practical transformation from the laboratory to the assembly line, the stability of the pull-up technique must be ensured, which involves the development of relevant high-precision equipment.
Another method to align CNTs on a large scale is via template-induced self-assembly, whose principle is to functionally modify nanotubes or target substrates to form strong intermolecular interactions between them.Under these conditions, the CNTs in the solution are adsorbed onto the template, whereas the patterned structures guide them to form a regular arrangement.During this process, the size resolution formed via patterning and the adsorption promotion formed by functional modification are critical, as they will directly affect the density and order of nanotubes deposition.
In earlier studies, researchers mainly modified the substrate, particularly the oxidation medium layer related to the manufacturing of electronic devices.Liu et al formed hydrophilichydrophobic functional layers arranged alternately on a silicon dioxide (SiO 2 ) substrate using -CH 3 and -NH 2 terminal groups [91].When the substrate was immersed in a DMF solution containing CNTs, the nanotubes deposited spontaneously on the hydrophilic surface via interactions.Meanwhile, Bardecker et al modified the substrate surface of Al 2 O 3 and HfO 2 with alkylphosphonic acids [92,93].They realized the selective deposition of CNTs via micro-imprinting and lithography.However, an ideal alignment of nanotubes was not achieved in these earlier studies owing to the limitations of the patterning resolution.
In 2013, Park et al [90] reported a selective deposition method based on ion exchange (figure 12).Functional modifications were performed on the CNTs and periodic HfO 2 trenches using SDS and 4-(N-hydroxycarboxamido)-1-methylpyridinium iodide.A strong electrostatic effect occurred between the Na + in SDS and I -in the self-assembled monolayer, which resulted in the selective deposition of nanotubes on the modified trenches.Compared with previous methods, the above mentioned method achieved a better assembly, where significant improvements were indicated in the packing density (1 × 10 9 cm −2 ) and alignment angle (within 30 • ).However, the 70 nm-wide trenches used did not match the diameters of the nanotubes, which were only approximately 1.7 nm.This restricted the spatial movement of the nanotubes significantly, which caused the aggregation and winding of some nanotubes into bundles in the trenches.
Theoretically, depending on the intermolecular interactions, template-induced assembly can enable the accurate manipulation of individual CNTs to achieve periodic arrays with a constant tube pitch.The aim of this technique is to reduce the pitch to the nanometer scale to satisfy the performance improvement requirements of CNT-based chips.However, constructing templates that match the size of a single nanotube is not trivial, and the existing challenges associated with ultrahigh-resolution lithographic patterning and functional modification are significant.
Sun et al [94] attempted to overcome these challenges using the DNA technique (figure 13).The assembly of CNTs was guided by only 2 nm-wide trenches produced by DNA brick crystals.The combination of DNA hybridization and electrostatic repulsion allowed the deposition of some nanotubes aligned with the trenches, whereas other nanotubes were repulsed and formed evenly spaced CNT arrays.Such small nanotrenches can spatially confine the individual nanotubes, which implies that the inter-CNT pitch can be decreased to 10 nm with an angular deviation of less than 2 • .The assembly results obtained in this study were favorable and demonstrated the unique advantages of template-induced selfassembly on a molecular scale.Defects could only be formed in the alignment area.In fact, maintaining this highly ordered alignment in an entire wafer measuring 0.35 cm 2 , which is the current achievement, is difficult.
Template-induced self-assembly offers flexibility and controllable inter-CNT pitches.This method guides the arrangement of CNTs on the designed trajectory and arbitrarily plans the alignment orientation.Individual CNTs can be isolated to the greatest extent possible to avoid bundling caused by overcrowded spaces.Nanomaterials can exhibit unique characteristics on a macroscale, which is beneficial for the improvement of IC performance.Therefore, ultrahigh-resolution processing patterns that can radiate to an entire substrate are necessary, and electron beam lithography and thermal probe lithography [95,96] are excellent techniques to be considered in this regard.

Manufacturing technology of CNT-based ICs
To improve the purity of s-CNTs and the quality of alignment arrays, the semiconductor device manufacturing technique and basic conditions allow the multiscale fabrication of CNT-based ICs, which is beneficial to the manufacture of high-performance CNT-based ICs that are comparable to or better than Si-based chips.The fabrication of CNT-based ICs is based on regular arrays of s-CNTs with a large area, an ultrahigh density, and high purity [97,98].
A state-of-the-art CNT FET with a 5 nm gate length has been reported by Peng's group in 2017 (figure 14) [23].Notably, it is the world's smallest CNT-based transistor with a working efficiency three times that of commercial Si transistors at the same node; however, its energy consumption is approximately 1/4 that of commercial Si transistors.Its comprehensive performance exceeds approximately 10 times that of Si transistors and is approaching the theoretical limit.
In addition to material preparation, complementary metaloxide-semiconductor (CMOS) circuits with symmetric performance and highly efficient top-gate structures must be studied for the integration of CNT FETs.Unlike Si-based CMOS, CNT CMOS can be constructed in a doping-free manner.That is, p-type and n-type CNT FETs are formed with high and low work function metals respectively.
In 2009, Peng's group realized P-type transistors using Pd contacts and N-type transistors using Sc contacts, with symmetrically matched properties [33].Based on these device studies, they used DLSA-prepared, wafer-scale CNT arrays to construct hundreds of top-gate, five-stage ring oscillators (RO) that exhibit an oscillating frequency of >8 GHz (figure 15) [58].In addition, this group fabricated a radio frequency (RF) chip based on high-density CNT arrays, which achieved current-gain and power-gain cutoff frequencies of up to 540 GHz and 306 GHz, respectively (figure 16) [99].Notably, its performance was superior to that of Si-based transistors with similar characteristic lengths.
VLSI systems have higher requirements for device stability and homogeneity.For CNT VLSI systems, it is necessary to fabricate CNT films with better density and purity.The world's first CNT-based computer prototype was built by Shulaker et al in 2013 [100].The entire computer was constructed on a 4 inch wafer.Each wafer contained 194 dies, each die contained five computer chips, each computer chip contained 178 CNT FETs, and each CNT FET contained 10 ∼ 200 CNTs.This working prototype was based on the von Neumann architecture, and the calculation component was connected to the external memory cells through external interconnection lines.The yield of the subsystems (such as the Dlatch) was between 80% and 90%, and the working frequency was 1 kHz (figure 17).In this computer, there is a maximum of seven-stages of cascaded logic consisting only of p-type transistors, demonstrating the complex digital system of this prototype.
In terms of the manufacturing process and performance of ICs, s-CNT arrays as the basis of this prototype were directly produced via CVD, which rendered it difficult to ensure the ultrahigh purity of CNTs; hence, researchers can only use longer channels to avoid the effects of a few metallic CNTs.Furthermore, proven CNT CMOS technology did not appear in this research.This indicates that many issues remain in the manufacturing and performance improvement of CNT-based ICs.
To further improve the electrical performance of CNTbased ICs, Hills et al and Adino Semiconductor conduct manufacturing research on overcoming nanoscale imperfections at macroscopic scales across full wafer substrates.They systematically developed a manufacturing methodology adapted to CNT-based VLSI, called MMC.It mainly consists of cleaning, combined doping, and logic circuit design technology.It aims to compensate for the material and manufacturing defects of CNTs and to form an air-stable, VLSI-compatible CNT CMOS system.Notably, this group used high-quality CNTs purified by the solution method, which confirms the technological breakthroughs achieved by the solution method in recent years.In 2019, the research team developed an overall CNT-based IC manufacturing process based on the existing commercial silicon chip manufacturing process and then developed the world's first universal modern CNT microprocessor RV16X-NANO [101].Details regarding the architecture are shown in figure 18.
Based on the RISC-V open-source architecture, a 16-bit microprocessor can process 16-bit data and addresses by executing standard 32-bit instructions.In the test, it successfully executed the classic 'Hello, World!' program.This process involves 14 000 CMOS CNT FETs, and the circuit is implemented through metal contacts with different work functions and electrical doping.This processor is based on a   Although the microprocessor can fully demonstrate the potential of CNT-based VLSI circuits for industrialization, it can be further improved.The operating speed of the designed circuits is currently at the megahertz level, which is the same level as that of Si chips 30 years ago, i.e. not on par with the superior performance of CNT-based ICs.This is attributable to the state of CNTs in the channels, considering that the latest purification and assembly techniques have not been applied in the manufacturing of CNT-based ICs.Owing to the disorder and low-purity channel state discovered, designers set the transistor channel length to 1 µm.In this case, the potential barrier caused by the overlap between the CNTs resulted in a significant performance loss.
In the future, the upgrading of CNT-based chips will inevitably be achieved by continuously scaling the size of CNT FETs, which is consistent with the route of Si-based chips.This requires the development of more advanced materials and manufacturing technologies, especially the purification and assembly of CNTs.In detail, it is necessary to optimize the quality of CNTs at low cost to make them more suitable for highly scaled transistor cells.In addition, the research and development of individual technique is no longer sufficient; combined, compatible techniques are the foundation for building VLSI.

Conclusion and prospect
Currently, the development of CNT-based chip manufacturing technology has indicated significant achievements; however, main obstacles must be broken through before s-CNTs can be industrialized.To surpass the performance of Si-based chips, CNT-based chip technology should be further developed as follows: (1) the preparation of high-quality and high-yield s-CNTs.In this respect, the solution method is preferred.The purity of s-CNTs prepared using the polymer purification method exceeds the 99.999 9% standard required for large-scale ICs.Moreover, for the same technology node, the state performance of CNT-based FETs surpasses that of Sibased FETs.However, this ultrahigh purity was achieved at the expense of production yield.Although an increase in the number of process steps improves the quality, it also significantly increases the manufacturing cost, which does not provide a competitive advantage.In the future, the development of CNTbased technology should be low cost.(2) Reliable large-scale fabrication of aligned CNT arrays.High performance CNTbased transistors impose strict requirements on the arrangement of CNTs in the channel, that is, to achieve a high density (>125 tube•µm −1 ) while ensuring reasonable spacing (5 nm).To manufacture ICs, hundreds of billions of CNTs must be arranged in a highly ordered manner on a macro scale.Existing methods of DNA and pull-up assemblies satisfy these requirements; however, the repeatability and stability must be improved.(3) Establishment of technological process standards for CNT-based ICs.We think that this section is based on overcoming material challenges and forming a uniform technological process to achieve device homogeneity and stability preparation.Currently, the manufacturing process for highly integrated CNT FETs is not consistent in many works, especially the unique cleaning, CMOS doping, and electrode contact process steps of CNTs.In the future, new technologies need to be broken through to apply to smaller CNT FET nodes, such as CNT-BNNT heterostructure nanotube [102] and high k gate dielectric materials [103], to solve the contact and gate control issues of extremely scaled devices.
In general, the existing CNT preparation technology shows that CNT-based integrated circuits (ICs) are suitable for preliminary industrialization.However, building a new CNTbased semiconductor ecological chain presents significant challenges.Academics and various industries must continue to address the remaining problems.In the next 15 years, we believe that CNT-based VLSI technology will have a bright prospect.

Figure 1 .
Figure 1.Comparison of Si and CNT FET.(a) Transistor technology comparison of Si and CNT FET roadmaps.(a) Reprinted from [20], Copyright © 2014 Elsevier Ltd.(b) Energy vs. performance of current FinFET and future CNT FET technologies.Reprinted with permission from [30].Copyright (2014) American Chemical Society.

Figure 2 .
Figure 2. Schematic illustration of a CNT FET modeled for 5 nm technology node.(a) Side view of a device showing CNTs between the source and drain.The gate will be located either around each CNT or on top of the array (omitted herein for clarity).(b) Top view of a device showing multiple CNTs between the contacts.The key dimensions are the gate pitch and CNT pitch.(a) and (b) Reprinted with permission from [30].Copyright (2014) American Chemical Society.(c) Progress of CNT transistor technology.Reproduced from [32], with permission from Springer Nature.

Figure 4 .
Figure 4. Sorting of single-walled carbon nanotubes by nonlinear density-gradient ultracentrifugation (DGU).(a) Distinct colored bands are layers enriched in different CNT species.(b) Near-infrared absorbance spectra of the marked colored layers.(c) Photoluminescence spectra of 10 separated fractions.(d) Centrifuge tube showing resolved pairs of enantiomer bands sorted from HiPco CNTs via nonlinear DGU using a single surfactant (sodium cholate).(e) Density profiles of DGU medium for linear and nonlinear initial gradients.(f) Densities of sodium cholate-suspended CNT species as a function of CNT diameter.Reproduced from [49], with permission from Springer Nature.

Figure 5 .
Figure 5. Highly selective dispersion of single-walled carbon nanotubes with aromatic polymers and photoluminescence excitation maps of various polymer-CNT samples in toluene solutions.(a) Maps for polymers PFO, (b) PFH, (c) PFO-P, and (d) PFO-BT.Reproduced from [50], with permission from Springer Nature.

Figure 7 .
Figure 7. DNA-controlled partition of carbon nanotubes in polymer aqueous two-phase systems.(a) Flowchart for aqueous two-phase separation of DNA-CNTs.(b) Schematic illustration of the poly-(ethylene glycol) (PEG)/polyacrylamide (PAM) system, in which the top phase is PEG-rich and the bottom phase is PAM-rich.(c) Partition of various DNA-CNTs in the PEG/PAM system.(d) Absorbance spectra of the highly purified (7,3) nanotubes obtained by aqueous two-phase systems.Reprinted with permission from [66].Copyright (2014) American Chemical Society.

Figure 8 .
Figure 8. Process for exploiting thermocapillary effect in purification of arrays of CNTs.(a) Schematic illustration and (b) corresponding AFM images of various stages of the process applied to an array of five metallic CNTs and three semiconductor CNTs.Reproduced from [69], with permission from Springer Nature.

Figure 9 .
Figure 9. Assembly and microscopic characterizations of full-coverage aligned arrays of semiconducting single-walled carbon nanotubes.(a) Schematic illustration of the Langmuir-Schaefer assembly process.(b) SEM, (c) AFM, and (d) top-view TEM images of aligned nanotube arrays transferred onto solid substrates.Reproduced from [71], with permission from Springer Nature.

Figure 11 .
Figure 11.Preparation and characterization of CNT arrays.(a)-(d) Illustrations showing the process of preparing a wafer-scale CNT arrays.(e) Dip-coating setup used for coating CNTs on a 4-inch silicon wafer.(f)-(h) SEM images showing an as-deposited CNT array.(i) Cross-section TEM image of a CNT array.From [58].Reprinted with permission from AAAS.

Figure 12 .
Figure 12.Selective placement of carbon nanotubes by an ion-exchange process.(a) Schematic illustration of CNTs placement on surface monolayer.(b) SEM image of nanotubes deposited on an open HfO 2 area.(c) AFM (phase) image of CNTs selectively deposited on an array of HfO 2 trenches.(d) SEM image of CNTs selectively placed and well-aligned in an array of 70 nm-wide HfO 2 trenches with a 200 nm pitch.(e) SEM image of CNTs selectively placed in an array of short and narrow trenches with a 200 nm pitch in the x-direction and a 500 nm pitch in the y-direction, corresponding to a density of 10 9 sites•cm −2 .(f) Plots of angular alignment of individual nanotubes vs. length of the nanotube for the trenches.Reproduced from [90], with permission from Springer Nature.

Figure 13 .
Figure 13.Precise pitch-scaling of carbon nanotube arrays within three-dimensional DNA nanotrenches.From left to right: (a) and (d) show the designs; (b) and (e) show zoomed-in TEM images along x and z projection directions, respectively; (c) and (f) (left) show liquid-mode AFM images along x and z projection directions; (c) and (f) (right) show height profiles for DNA template ((a)-(c)) and the assembled CNT array ((d)-(f)).From [94].Reprinted with permission from AAAS.

Figure 14 .
Figure 14.Structure and performance of 5 nm CNT FETs.(a) Top: TEM image of a normal Pd-contacted CNT FET with a gate length of 5 nm.Bottom: SEM image of a graphene-contacted CNT FET with a channel length of 5 nm before the deposition of the top gate electrode.(b) Schematic diagram showing the structure of a GC CNT FET.(c) Schematic band diagrams of the graphene-contacted CNT FET in its on-state (top) and off-state (bottom).(d) and (e) Transfer characteristics of three typical GC CNT FETs.From [23].Reprinted with permission from AAAS.

Figure 15 .
Figure 15.Structure and characteristics of CNT array-based ring oscillators.(a) Optical image of batch-fabricated CNT five-stage ROs.(b) and (c) False-colored SEM images of an RO.(d) Power spectra of 65 CNT ROs.(e) Power spectrum from the champion RO.(f) Benchmarking of the stage delay of champion ROs.From [58].Reprinted with permission from AAAS.

Figure 16 .
Figure 16.Performance characteristics of CNT radio frequency transistors based on aligned carbon nanotubes arrays with high density.(a) SEM image showing a two-finger transistor with channel length L ch = 95 nm and Lg = 50 nm.(b) Transfer curve (left) and output curves (right) of a 50 nm-Lg transistor on a quartz substrate.(c) Schematic of a two-tone measurement setup.V G equals Vgs.(d) SEM image showing a typical six-finger transistor for an amplifier.(e) Output power versus input power curves and the fundamental term and third-order term of the two-tone test.Reproduced from [99], with permission from Springer Nature.

Figure 17 .
Figure 17.CNT computer and its results.(a) Top: final 4-inch wafer after all fabrication processes.Bottom: scanning electron microscope (SEM) image of a CNT transistor.(b) SEM of an entire CNT computer.(c) Measured characterization (current-voltage) curves of a typical CNT transistor.(d) Measured outputs from 40 different arithmetic units.Reproduced from [100], with permission from Springer Nature.

Figure 18 .
Figure 18.RV16X-NANO.(a) Image of completed RV16X-NANO 150 mm wafer.(b) Image of fabricated RV16X-NANO chip.(c) Three-dimensional scale-rendered schematic illustration of the RV16X-NANO physical layout.(d) Schematic illustration, characteristics, and experimental results of CNT FET CMOS fabricated using metal interface engineering crossed with electrostatic doping (MIXED).Reproduced from[101], with permission from Springer Nature.