CMOS-compatible neuromorphic devices for neuromorphic perception and computing: a review

Neuromorphic computing is a brain-inspired computing paradigm that aims to construct efficient, low-power, and adaptive computing systems by emulating the information processing mechanisms of biological neural systems. At the core of neuromorphic computing are neuromorphic devices that mimic the functions and dynamics of neurons and synapses, enabling the hardware implementation of artificial neural networks. Various types of neuromorphic devices have been proposed based on different physical mechanisms such as resistive switching devices and electric-double-layer transistors. These devices have demonstrated a range of neuromorphic functions such as multistate storage, spike-timing-dependent plasticity, dynamic filtering, etc. To achieve high performance neuromorphic computing systems, it is essential to fabricate neuromorphic devices compatible with the complementary metal oxide semiconductor (CMOS) manufacturing process. This improves the device’s reliability and stability and is favorable for achieving neuromorphic chips with higher integration density and low power consumption. This review summarizes CMOS-compatible neuromorphic devices and discusses their emulation of synaptic and neuronal functions as well as their applications in neuromorphic perception and computing. We highlight challenges and opportunities for further development of CMOS-compatible neuromorphic devices and systems.


Introduction
In recent decades, the integrated circuit industry has been experiencing rapid growth driven by technological advancements and demand, leading to the emergence of new technologies such as big data, artificial intelligence, and 5G [1,2]. Efficiently and quickly processing massive data calculations is a key challenge for these technologies. Traditional computing technologies face two major bottlenecks: the separation of computing and storage units under the von Neumann architecture, resulting in significant time and energy waste on data bus transmission; and the impending end of Moore's Law as device sizes approach physical limits [3][4][5]. Integrated circuit technology is now entering the post-Moore era and various technological approaches are being proposed to continue its development. These include system-on-chip technology that integrates multiple functions into a single chip, chiplet integration technology that greatly improves the economic benefits of continuing Moore's Law, the development of thirdgeneration semiconductors such as SiC, photonic chips, and non-Von computing paradigms.
Neuromorphic computing is a representative of non-Von computing that has been recognized by the International Semiconductor Industry Association as the most promising technology in the post-Moore era [6][7][8][9]. Compared with quantum computing, neuromorphic computing has clearer development prospects and more mature technological implementations. The core of neuromorphic computing is to construct corresponding computational theories, device structures, chip architectures, and application models and algorithms by mimicking the information processing modes of biological neural systems [10]. At present, some researchers are trying to develop brain-inspired devices based on complementary metal oxide semiconductor (CMOS) technology, such as IBM's TrueNorth chip [11], Intel's Loihi chip [12], etc. These chips adopt the neuromorphic core architecture, using CMOS transistors to simulate the functions of neurons and synapses and to realize large-scale spiking neural networks (SNNs) [13]. Although CMOS devices have successfully simulated neurons and synapses, they also have obvious drawbacks. For instance, the voltage modality of CMOS transistors diverges from the current modality of neurons, rendering them arduous to emulate the dynamic attributes of synapses and neurons such as plasticity, nonlinearity, hysteresis, etc. Moreover, the power consumption and heat dissipation of CMOS devices escalate with the increase of integration degree, which are incommensurable with the high efficiency and low consumption of the human brain. Consequently, the development of novel devices is paramount for the advancement of neuromorphic computing. At present, various devices have been developed to realize brain-inspired computing, represented by resistive switching devices and neuromorphic transistors [14][15][16][17][18]. In terms of device functions, neurons, and synaptic behaviors have been successfully simulated. Various synaptic devices have been widely verified as hardware accelerators for artificial neural networks (ANNs), and biological sensing functions have been further developed [19][20][21]. In terms of material systems, devices constructed from various materials, ranging from inorganic to organic, conventional to quantum, and bulk to low-dimensional materials, exhibit distinct neuromorphic characteristics based on their dimensional properties and material compositions [22]. To adapt to the development requirements of the post-Moore era, the manufacture of neuromorphic devices should be as compatible as feasible with the existing mainstream CMOS integrated circuit technology. Due to the maturity and widespread use, the development of neuromorphic devices utilizing CMOS technology holds significant implications. The use of CMOS technology for large-scale production of neuromorphic devices preserves the key characteristics of neuromorphic computing. Additionally, it ensures compatibility and integration with existing CMOS circuits, facilitating the development of more advanced and intelligent artificial intelligence systems.
This review surveys recent advances in neuromorphic devices that are compatible with CMOS manufacturing technology and their applications. The discussion is organized into five sections, as shown in figure 1 [23]. The first section examines the emulation of various forms of biological synaptic plasticity using different types of synaptic devices. The second section focuses on the emulation of biological neuronal functions. The third and fourth sections discuss the applications of artificial perception and neuromorphic computing. The final section provides a summary and outlook on the topics discussed.

Artificial synapses
Various life functions of living organisms are controlled by an intricate network of neurons and synapses. A biological synapse is a contact structure where the impulse of one neuron is transferred to another neuron. It is a crucial part of information transmission. The signal-integrating function of biological synapses can be modulated by altering the connection strength (i.e. synaptic weight) between neurons, a process termed synaptic plasticity [24][25][26]. Short-term plasticity (STP) and long-term plasticity (LTP) are two different forms of synaptic plasticity. STP refers to the variability in synaptic transmission efficiency that occurs within a short period. It can result in short-term potentiation (STP), such as excitatory postsynaptic current (EPSC) and paired-pulse facilitation (PPF), or short-term depression. On the other hand, LTP refers to a long-lasting increase in synaptic transmission efficiency for an extended period. LTP is often associated with learning and memory processes and is achieved by activity patterns between presynaptic and postsynaptic neurons. Spiketiming-dependent plasticity (STDP) and spike-rate-dependent plasticity (SRDP) are two common mechanisms of synaptic plasticity. However, STDP focuses on the temporal order of activity between presynaptic and postsynaptic neurons, while SRDP emphasizes the frequency of activity in presynaptic neurons [27]. At present, a variety of synaptic plasticity has been extensively simulated by various neuromorphic devices.
The resistive switching device (also known as a memristor) proposed by Chua is widely researched [28]. In 2010, Lu et al introduced the simulation of synaptic plasticity using a memristive device, which sparked a surge of research in neuromorphic computing [29]. The conductivity of this device can be altered, allowing it to switch between multiple states and exhibit either volatility or non-volatility, which simulates STP or LTP in artificial synapses. In addition to their biosimilarity, memristive devices possess potential advantages over conventional CMOS devices in terms of scalability, storage density, and energy consumption. The development of CMOS-compatible resistive switching device materials and their processing with standard CMOS technology is a future trend and an effective way to obtain low-cost brain-like chips. Currently, various material systems are used for resistive switching devices, including binary metal oxides and their dopants, perovskite materials, chalcogenide compounds, and organic materials. Among them, oxide materials such as HfO x , TaO x , AlO x , TiO x , WO x , ZrO x , etc are extensively studied because of their compatibility with traditional CMOS processes, which makes them closer to the industrial production index.
Recently, research has been conducted on synaptic devices made of materials such as HfO x and TaO x , to explore their potential for neuromorphic applications. Spiga and colleagues proposed an artificial synapse based on an HfO 2 memristive device [30]. This device can gradually change its conductance in response to appropriate electrical stimuli. By applying a sequence of spikes, the device exhibits gradual potentiation and depression of synaptic characteristics. Moreover, the device can implement the STDP learning rule by adjusting the delay time between the two spikes. In another study, Wang et al proposed diffusive resistive devices using materials such as MgO:Ag, Si x N y :Ag, and HfO x :Ag [31]. These devices exhibit dynamical properties that are equivalent to Ca 2+ , and the PPF, SRDP, and STDP have been experimentally verified (figures 2(a)-(d)). Additionally, Chen et al reported an Ag/HfO 2 /Pt resistive switching device to demonstrate biological synaptic behavior, such as STP and LTP, potentiation/depression, and the STDP learning rule [32]. Lately, Kim et al proposed a TiN/ZrO x /Pt structure to demonstrate synaptic characteristics. They realized EPSC, PPF, potentiation/depression, and STDP using this structure [33]. The performance of oxide-resistive switching devices can be effectively improved by introducing impurities or inserting barrier layers [34]. Ryu and Kim presented a Pt/TaO x /HfO 2 /TiN stack device [35]. By adjusting the oxygen vacancies in the material, up to 60 conductive states are obtained. Mahata et al developed an HfO 2 /Al 2 O 3 structure on an ITO substrate to demonstrate synaptic characteristics, and the potentiation/depression and STDP rule were realized under identical pulse trains [36]. Oh et al proposed a ferroelectric synapse device based on HfZrO x . They obtained 32 levels of remnant polarization state by optimizing the pulse condition using this device [37]. It is worth mentioning that ferroelectric random-access memory (FeRAM) based on HfZrO has attracted widespread interest from researchers. FeRAM can control the redistribution of  [31], with permission from Springer Nature. (e) Bidirectional tunable conductance characteristics. Reprinted from [43], with the permission of AIP Publishing. (f) The device structure for a neuromorphic system. Reprinted with permission from [44]. Copyright (2020) American Chemical Society. (g) Schematic diagram of the n-Si/HfO 2 /WO 3 /Ag structure. (h) Potentiation and depression characteristics. [ interface charge carriers by manipulating the polarization field, thereby modulating the height or width of the interface potential barrier between the ferroelectric layer and the electrode. This achieves continuous and tunable device resistance. Compared with traditional resistive switching devices based on conductive filaments, FeRAM demonstrates stable polarization states, excellent non-volatility, and low power consumption. This makes it a strong candidate for future data storage and computing [38,39]. Currently, several studies have successfully implemented STDP learning rules using FeRAM devices [38,40,41]. In addition, HfZrO-based memcapacitors can also serve as synaptic devices. A ferroelectric memcapacitor with moderate remnant polarization, which serves as a memcapacitive synapse, was demonstrated by Zhu et al [42]. This device shows more than 64 weight states and requires very low energy to update the weight. The memcapacitive synapse based on HfZrO x is promising for the constructing of neuromorphic systems with high energy efficiency.
Resistive switching devices with asymmetric and nonlinear conductance tuning characteristics can reduce the accuracy of computation [47,48]. To enhance the linearity of conductance updating, Woo et al and Bao et al demonstrated that this can be realized by introducing AlO x in HfO 2 and TaO x devices, respectively [48,49]. Furthermore, Liu et al demonstrated a bidirectional tunable conductance characteristic in an HfO 2 /TiO x bilayer structure using ultra-short pulse trains [43]. The use of optimal pulse amplitude conditions can lead to almost linear conductance updates, which are a crucial factor in improving neuromorphic computing as depicted in figure 2(e). The sneak path problem of crossbar structures is another serious issue. To address this problem, Jang et al proposed a one-transistor two-memristor synaptic structure (figure 2(f)) [44]. This structure demonstrates greater linearity and symmetry in conductance modulation than individual devices, as well as being more resilient to the sneak path problem. In recent years, WO x has attracted considerable attention for electronic applications because of its adjustable bandgap and established deposition techniques [50]. WO xbased resistive devices have shown robust reliability and analog switching characteristics. For instance, Liu et al proposed an n-Si/HfO 2 /WO 3 /Ag structure with excellent synaptic characteristics. They showed EPSC, PPF, and potentiation/depression using this structure as shown in figures 2(g) and (h) [45]. The use of silicon-based materials has advantages for CMOS compatibility. Ma et al recently demonstrated a picoJoule resistive device based on atomically thin SiO x (figure 2(i)) with extreme CMOS compatibility and good conductance-updating linearity [46]. This design strategy has the potential to develop large-scale neuromorphic computing systems.
Magnetic random-access memory (MRAM) is a nonvolatile two-terminal device that stores data using magnetic materials. The resistance between the two ferromagnetic layers in MRAM changes with the relative orientations of their magnetizations. By applying an external magnetic field or spin-transfer torque (STT) current, the magnetization direction can be altered, which changes the resistance state. Compared with MRAM, STT-RAM achieves higher density, lower cost, and lower power consumption. Additionally, compared with traditional resistive switching devices and FeRAM, STT-RAM exhibits better durability due to its unique spin-based mechanism. Kulkarni et al proposed a hardware accelerator for neural networks based on STT-RAM. They used STT-RAM crossbar arrays as the synaptic core for neural networks. This accelerator successfully emulates the brain's time-based signal encoding and processing mechanism [51]. STT-RAM has potential advantages for low-power neuromorphic computing. However, it also faces significant challenges. The write process of STT-RAM is inherently stochastic, resulting in a wide variation of actual write times, which can lead to high error rates. Therefore, this aspect requires more attention and investigation [52].
Although synaptic devices with a two-terminal structure offer a simple design and high integration advantages when used in crossbar arrays, they have some issues such as crosstalk, sneak path currents, and nonlinear current-voltage characteristics [53]. Although these problems can be solved in different ways, they tend to increase circuit complexity and manufacturing costs. In contrast, three-terminal devices used for arrays can conduct read operations without any sneak path current. This is because programming and read operations are not influenced by the states of unselected devices. Additionally, transistor-based synaptic devices provide the advantage of parallel computing and memory. For example, floating gate transistors, ferroelectric transistors, charge-traptransistors, and electric-double-layer (EDL) transistors have been used as synaptic devices [5,54,55]. The input of the synapse can be a gate voltage or other signal sources, such as light, and the channel current serves as the post-synapse. The transport of carriers in these devices resembles the flow of neurotransmitters.
Due to their stable storage capacity, floating gate transistors have been extensively utilized to replicate synaptic behavior. They provide virtual analog tuning of synaptic weights, consume low power, and have high compatibility with CMOS technology. This solution is particularly advantageous because it allows the creation of artificial synaptic arrays directly from the mainstream nonvolatile memory technologies with minor adjustments to the array design [56]. Malavena et al demonstrated the operation of a common ground double-polysilicon array [57]. They implemented STDP learning rules using a simple pulse scheme. This is a crucial step in developing largescale neuromorphic systems using mainstream technologies. IGZO, a ternary oxide semiconductor consisting of indium, gallium, and zinc, has received extensive attention from the scientific and industrial communities due to its large-area, low-temperature fabrication, and excellent electrical properties. It has been successfully applied on a large scale for next-generation display drivers. In addition to their significant application value for display driver technology, IGZO devices also have promising prospects for neuromorphic applications [24,[58][59][60][61]. In neuromorphic applications, IGZO devices exhibit low power consumption, high transparency, as well as good chemical and thermal stability. This makes them an ideal material choice. In 2009, Wan's group first developed an IGZO double-layer transistor with a solid-state electrolyte as the gate dielectric [62]. Subsequently, researchers have extensively reported on IGZO neuromorphic devices based on the EDL effect and electrochemical doping effect. He et al reported a low-temperature processed IGZO-based floating gate transistor with Al 2 O 3 /ITO/Al 2 O 3 gate dielectric stacks for neuromorphic computing [63]. The transistor's channel conductance is adjusted by electron direct tunneling. As depicted in figures 3(a)-(c), the application of negative and positive electrical pulse stimuli to the gate of the transistor can induce weight potentiation and depression, respectively. He et al also suggested an IGZO transistor that uses Al 2 O 3 gate dielectrics deposited by low-temperature atomic layer deposition to mimic LTP and long-term depression (LTD) [64]. EDL transistors based on solid-state gate dielectrics have also been extensively researched. Ke et al proposed a photoelectronic transistor based on amorphous IGZO to mimic synaptic plasticity [65]. They used a SiO 2 electrolyte film as the gate dielectric film, and they simulated light-induced STP, which included EPSC, PPF, and high-pass temporal filtering. Yang et al reported a physical reservoir computing system based on an EDL IGZO transistor [66]. Figures 3(d) and (e) demonstrate that the device's temporal response effectively mimics the temporal nonlinearity and STP properties. This shortterm dynamic is favorable for reservoir computing simulation and has the potential to facilitate the advancement of high-performance RC hardware for future machine learning applications.
Synaptic transistors based on the charge-trapping mechanism are also promising candidates due to their excellent CMOS compatibility and product-level reliability. The chargetrapping transistor (CTT) holds an advantage for LTP characteristics because the charges stored in the charge-trapping layer are not easily escaped. This makes it favorable for  [69]. Utilizing the high trap density and shallow trap energy levels of TaO x , this device achieved linear and symmetric LTP and LTD characteristics with over 6-bit weight modulation capability. Park et al introduced a synaptic transistor utilizing IGZO as the device channel and trap layer [70]. IGZO simplified the manufacturing complexity and improved the charge detrapping efficiency. The device successfully simulated various plasticity, including EPSC, inhibitory postsynaptic current (IPSC), LTP, and LTD. Additionally, under an incremental voltage scheme, it exhibited linear and durable weight modulation ability. The charge-trapping mechanism also impedes STP simulation. Hence, some researchers focus on utilizing CTT to achieve STP characteristics [71]. Yu et al reported a highly scalable and three-dimensional (3D) structured leaky charge-trap fin-shaped field effect transistor that they fabricated using 100% CMOS-compatible materials and processes [72]. They successfully emulated various synaptic plasticity, including EPSC, IPSC, and PPF. Moreover, it achieved up to five synaptic learning rules, including STDP and SRDP, with extremely low power consumption.
Ferroelectric transistors have the advantage of lower write voltage and faster operation speed than floating gate devices. This makes them ideal for neuromorphic applications. HfO 2 thin film doped with various elements has promising ferroelectric properties and has more compatible with CMOS. This enables better dimensional scaling than perovskite ferroelectrics. Recently, researchers have made progress in simulating synaptic plasticity using HfO 2 -based ferroelectric transistors. Jerry et al proposed a 10 nm thick HfZrO-based ferroelectric transistor that simulates synaptic plasticity by controlling local polarization with an electric field. The FeFET synapse demonstrates nearly identical conductance for potentiation and depression when incremental amplitude pulses in a pseudo-crossbar array stimulate it [73]. Kim et al reported a FeFET with a structure of HfZrO/IZTO, as shown in figure 3(f) [67]. The conductance can be precisely controlled by adjusting the polarization of the HfZrO film. By optimizing pulse conditions, linear and symmetric conductance changes are demonstrated, and conductance values for more than 60 states are obtained. Additionally, the potential scalability of HfO x -based ferroelectrics could offer advantages for 3D memory applications. A recent study by Kim et al showcased an innovative 3D NAND array that used HfZrO ferroelectrics and a nanoscale vertical FeFET as a memory cell. By utilizing incremental pulse schemes, they achieved linear and symmetric potentiation and depression characteristics, as shown in figures 3(g)-(i) [68]. This research provides a practical method for realizing high-performance and efficient neuromorphic hardware systems through the vertical stacking of computation components.

Artificial neurons
Neurons are the basic units of biological information processing. They have three main components: soma, axon, and dendrite. Neurons encode external stimuli as spike signals and propagate them along the dendrite to its body, where it is integrated with inputs from other neurons. If a spike potential exceeds a certain threshold, its body generates an action potential and sends it out through the axon [74]. Artificial neurons aim to mimic the integration and firing functions of biological neurons. However, conventional CMOS devices lack the dynamic characteristics of neurons and require complex circuits with dozens of transistors to simulate them [75]. Various neuron models have been developed to describe how artificial neurons emulate action potential generation in circuits, such as biophysical models and phenomenological models. Biophysical models use variable resistors to simulate the changes in ion channels and the electrophysiological state of the neuron membrane, such as the Hodgkin-Huxley (H-H) model. Phenomenological models use simple mathematical abstractions to simulate the input-output behavior of biological neurons, such as the leaky-integrate-and-fire (LIF) model.
Currently, resistive switching devices with threshold switching (TS) properties have garnered significant interest in simulating neurons. Among them, TS devices based on conductive filaments and Mott transition mechanisms are most likely to be employed in the large-scale construction of neuron circuits. Mott transition-based TS devices, such as NbO x and VO x resistive switching devices, possess high uniformity, high durability, and ultrafast transition speed, which are vital for neuronal circuit applications. Compared to VO x , NbO x has better CMOS process compatibility. Picket et al designed an artificial neuron using two Pt/Nb 2 O 5 /Pt TS devices following the H-H model [76]. As shown in figure 4(a), two NbO 2 TS devices act as Na + and K + ion channels in this circuit, respectively, and each of them has a parallel capacitor.
Similar to the sodium and potassium channels in the H-H model, the two channels are energized with opposite polarity voltages and are coupled to each other through a load resistor. This circuit can achieve various neuron functions such as an all-or-nothing spiking of an action potential. Figure 4(b) illustrates the scanning electron micrograph and current-voltage curve of the NbO 2 TS device. The circuit exhibits an all-ornothing response, as shown in figure 4(c), where signal gain occurs only when the signal surpasses the threshold signal. Neuromorphic systems can benefit from the use of TS devices with a filamentary mechanism due to their low leakage current and small operation voltage [77]. Wang et al reported a diffusion memristive device to realize the LIF process in neurons [78]. As shown in figure 4(d), when an input pulse arrives, the capacitance in the circuit starts to charge. When the voltage reaches the threshold, Ag + channels form at both ends of the device, causing it to switch to a low-resistance configuration and discharge the capacitor (firing). Capacitance and resistance have different effects on the integration and firing processes of the circuit, with smaller capacitance leading to faster integration and increased resistance slowing down the accumulation of charges, as shown in figure 4(e). Wang et al also demonstrated a fully integrated resistive switching device neural network chip (figure 4(f)).
Zhang et al published a study on a hybrid resistive switching device-CMOS LIF spiking neuron [79]. The firing behavior was emulated using the TS property, and the tunable threshold of transistors could achieve the plasticity of neurons, as shown in figure 4(g). Moreover, they demonstrated in-situ Hebbian learning capability by constructing a fully hardwarebased SNN. This work proposed a novel neuron design that reduced the complexity and area of CMOS circuits while preserving the essential functionality and plasticity of neurons. This design also facilitated high-density integration and low-energy consumption. Furthermore, the system supported in-situ learning, which is closer to the working mechanism of biological neural systems and has great potential for applications such as edge computing. Zhang et al demonstrated a LIF model based on a TS device with a TiN/HfO 2 /InGaZnO 4 /Si structure [80]. Hua et al reported an Ag/HfO 2 TS oscillatory neuron that achieved low-power operation [81]. This design is conducive to the integration with other resistive switching devices or CMOS devices and the construction of more complex neural networks.
By controlling the ferroelectric domain flipping dynamics, it is possible to simulate multiple neuronal models using ferroelectric materials. Cao et al presented an anti-ferroelectric FET (anti-FET) neuron based on the inherent polarization and depolarization of HfZrO [82]. The intrinsic accumulated polarization and spontaneous depolarization of HfZrO films enabled the implementation of the LIF behavior of neurons, eliminating the need for external capacitors and reset circuits. Figures 5(a) and (b) illustrate the volatility characteristics exhibited by anti-ferroelectric materials and the typical transport characteristics of anti-FeFET. In figures 5(c) and (d), the drain current demonstrates reproducible LIF behavior with a continuous pulse applied. This anti-FeFET neuron is CMOScompatible and provides a reference for the application of ferroelectric devices in the field of neuromorphic computing. Based on the charge-trapping mechanism, a CTT device can also be used to simulate neuronal behavior. Park et al reported a device based on an Al 2 O 3 /Si 3 N 4 (A/N) bilayer to emulate the behavior of a LIF neuron [83]. Due to its rapid charge emission characteristics, when its accumulated charge reaches a threshold, it generated a spike. This approach demonstrates the potential of CTT devices in reproducing neuronal behavior. Furthermore, by introducing HfO 2 and SiO 2 layers, this device can also be used as a synaptic element.
Due to the captivating physical properties and nonlinear dynamics, spintronic devices present remarkable potential for neuromorphic computing [87]. Creating CMOS-compatible spintronic neurons could be a viable alternative to conventional computing technology in the future. Wang et al have presented a novel and dependable single spin-orbit torque (SOT) neuron with LIF and self-reset capabilities, which are depicted in figure 5(e) [84]. This work systematically reports the utilization of a CMOS-compatible magnetic multilayer stack based on unique lithography and etching optimization techniques. In a vertical magnetic anisotropy magnetic tunnel junction Ta/SAF/W/CoFeB/MgO/CoFeB/W/Ru/Ta system, they proposed a SOT and internal built-in magnetic field (H built-in ) co-driven mechanism to control the DW motion. The neuron functions are generated by the cooperative interaction between SOT and the H built-in in magnetic tunnel junctions. SOT can propel the domain wall to move toward the right when the applied current density is large enough, while synthetic H built-in propels the domain wall toward the left without any additional current application. Thus, the LIF can be realized by controlling the domain wall velocity driven by SOT, as shown in figure 5(f). It is provided a high-speed, highendurance, and low-power neuron device for the field of neuromorphic computing, demonstrating the huge potential based on DW motion, and offering new physical mechanisms and technical approaches for the construction and optimization of computing systems based on spintronic devices. Recently, this team also presented a new artificial spintronic neuron that can mimic the biological behaviors of LIF and self-reset (LIFT) characteristics. Figures 5(g) and (h) illustrate the LIF and LIFT characteristics, respectively. Using a synthetic antiferromagnetic heterostructure to control the magnetic domain wall motion by Joule heating, which enables the device to fire spikes with a high rate and low energy consumption [85]. These results show a novel way of implementing bio-inspired spiking neurons with spintronic devices that have advantages over traditional CMOS or emerging nonvolatile memory technologies.
In biological systems, dendrites also play a critical role in the processing of information in neural networks [88]. Dendrites can nonlinearly integrate postsynaptic signals and eliminate insignificant background information [89,90]. Traditional ANNs often neglect some functions that are important for enhancing the network's flexibility and reducing the system's power consumption. Therefore, Li et al proposed a scalable memristive device technology that experimentally implemented a complete ANN, including synapses, dendrites, and soma [86]. Figure 5(i) shows the electrical performance of the artificial dendrite, which has a high similarity with the nonlinear characteristics of biological dendrites ( figure 5(j)). The team also built a network system using three types of resistive switching devices to evaluate the computational functions of artificial dendrites, as shown in figures 5(k) and (l). The neural network achieved higher accuracy in recognition tasks while maintaining low power consumption, which was three orders of magnitude lower than traditional central processing units. This work demonstrated the feasibility and advantages of using resistive switching devices to realize artificial dendrites. The developed neuromorphic dendritic device is CMOScompatible, and its rich dynamic characteristics reproduce the nonlinear filtering, integration, and processing of time information of biological dendrites. Artificial dendrites not only achieved compact circuit structures but also simulated the information processing mechanisms of biological dendrites, improving the network's energy efficiency. This result has important implications for building high energy efficiency, high accuracy, and high flexibility artificial networks in the future.

Artificial perception
The human perception system is a highly efficient parallel computing system that can simultaneously receive and process data from multiple sources and offer advantages such as low power consumption, high compatibility, and high plasticity [91]. Artificial perception systems are an emerging field that draws on expertise from multiple engineering and scientific disciplines. The difference between neuromorphic perception systems and traditional computing systems is that they use hybrid analog/digital components instead of Boolean logic and clock operations [92]. Traditional perception systems employ a range of devices to sense, convert, and transmit signals from the external environment. However, as the volume of data being generated continues to grow exponentially, these systems are increasingly challenged by issues such as highpower consumption. To address these challenges, researchers are developing artificial perception systems based on emerging synaptic devices that can perform parallel distributed computing and reduce data redundancy and transmission. This can save energy and bandwidth, lower power consumption and latency, and enhance compatibility and conformability with biological systems [92]. Artificial perception systems can also fuse and process multimodal information, such as tactile, visual, and auditory signals, which is crucial for improving environmental perception and understanding, as well as security and efficiency. Moreover, the integration of artificial perception systems with CMOS technology can offer additional benefits, such as reduced cost, increased density, and improved reliability.
Tactile perception is a crucial aspect of human sensory experience. Through the sense of touch, humans can perceive the world around them and gather direct information about the interactions between their skin and external objects. Tactile perception plays a vital role in many aspects of human life, including object recognition, manipulation, and social interaction. It allows us to perceive properties such as texture, temperature, and pressure. Nociceptors are special sensory neurons that respond to harmful or excessive stimuli and send warnings to the central nervous system to reduce potential damage to the body. Nociceptors do not respond to all stimuli, but only to those that exceed a threshold value, and they exhibit features such as no adaptation and sensitization [93]. Yoon et al presented an artificial nociceptor based on a Pt/SiO x :Ag/Ag/Pt resistive switching device, which showed critical dynamics characteristics, as illustrated in figure 6(a) [93]. They achieved normal and abnormal states of the artificial nociceptor by applying voltage stimuli, as shown in figure 6(b). Moreover, they integrated the artificial nociceptor into an artificial sensory alarm system to verify the feasibility of the system. This work proposed a nociceptor that could simulate the functions and features of biological nociceptors, which could provide an effective self-protection mechanism for bionic robots and enhance their adaptability to environmental changes. Similarly, Liu et al demonstrated an Ag/SiC/Pt structure to construct an artificial nociceptor [94]. The characteristics of a nociceptor, such as 'threshold,' 'inadaptation,' and 'relaxation,' have been emulated in this device. This allows for enhanced adaptability of the system in response to changes in the environment. Recently, Shi and colleagues illustrated an artificial spiking thermoreceptor (AST) using an Ag/TaO x /AlO x /ITO resistive switching device, which achieved thermal perception akin to that of humans [95]. The AST can detect external thermal signals and convert them into a sequence of spikes that resemble the biological thermoreceptor.
Multimodal perception in the tactile system refers to the integration of information from different sensory modalities, such as shape, humidity, temperature, etc, that can improve the accuracy of object recognition and reduce the risk of bodily injury. Multimodal perception differs from unimodal perception, which relies on a single sensory modality. Zhu et al proposed a multimode-fused spiking neuron (MFSN) to achieve human-like multimodal perception and object classification, as shown in figure 6(c) [96]. As illustrated in figure 6(d), the MFSN combined a pressure sensor and an NbO x TS device, which could sense pressure and temperature information, respectively. The MFSN could transform pressure and temperature information into a single spike sequence, and also recover pressure and temperature information by decoupling the output signals. They also verified the capability of tactile pattern recognition using a miniature array and realized object classification using a larger-scale simulated array. Duan et al reported an artificial neuron composed of a sensor and volatile resistive switching device for multimodal perception of haptic and temperature. This artificial neuron can sense different pressures and convert them into spike trains, while also perceiving temperature through the metal-insulator transition of the material [100]. In addition, Han et al demonstrated a multimodal sensing device capable of simultaneously receiving visual and thermal stimulation signals [101]. Wang et al reported a multi-mode MXene-ZnO memristive device that simulates the unique environmental adaptation behavior of the human eye by combining light sensing and relative humidity sensing [102]. Recently, Wan et al proposed a dualmode artificial sensory neuron that achieves fusion perception of visual and haptic [103]. These works demonstrated the feasibility of using neuromorphic devices for multimodal perception, enhancing the flexibility and efficiency of information processing. The human perception system is a complex and multifunctional neural system, and significant progress has been made in exploring these multimodal sensing systems. However, further efforts are required to achieve complete human-like sensory capabilities. Continued development of biologically adaptive and efficient multimodal sensing systems holds significant importance for the future advancement of human-machine interaction and biomimetic robotics.
Vision is a major method through which numerous organisms collect information regarding their external environment. This has motivated scientists to develop biomimetic visual systems that use electronic devices to imitate the abilities of natural vision. Biomimetic visual systems aim to replicate the structure and function of biological visual systems to achieve more efficient and effective artificial vision. The potential of biomimetic visual systems to revolutionize a broad range of fields, such as robotics, autonomous vehicles, and medical imaging, has been recognized. By simulating the abilities of natural vision, these systems offer the possibility of more precise and dependable visual perception for various applications. Traditional artificial vision systems rely on external sensors to convert light signals into electrical signals for processing, as their core units are not directly responsive to light stimuli. Therefore, it is desirable to develop artificial vision systems that integrate perception, storage, and computation. Zhou et al proposed a photoelectric vision system based on MoO x resistive switching device, as shown in figure 6(e) [97]. The device exhibits non-volatile behavior and tunable weight characteristics, enabling image perception, storage, and preprocessing functions. They constructed a photoelectric array and realized a simple and efficient artificial vision system that can perform image perception and processing without an external power supply or control circuit. This simplifies the circuitry of artificial vision systems and reduces the system power consumption. This work provides potential contributions to the advancement of artificial vision systems and edge computing. Chen et al presented a resistive switching device-based vision system that is sensitive to ultraviolet light [104]. The system utilizes the resistance change state to memorize the distribution of ultraviolet light and exhibits high retention characteristics and repeatable programming characteristics. Biological vision systems can convert optical signals into spike signals before processing visual images, which have the advantages of high throughput and ultra-low power consumption. Recently, Chen et al proposed a biologically realistic photoelectric spiking neuron to achieve visual perception, as shown in figure 6(f) [98]. The neuron consists of a photodetector, a TaO x spike encoder device, and a neuromorphic transistor network, where the TaO x device can encode light signals into electrical spike signals and input them into the transistor network for classification and recognition. The generated spikes are similar to those of real biological neurons and can mimic the distancedependent effect and eye fatigue phenomenon in biological vision systems. The system can adjust the threshold and gain of the encoder according to different distances of light stimuli, thereby improving the recognition rate of depth perception. This is a very innovative and valuable work that has made important progress in the design and application of photoelectric spiking neurons. This work provides a new technical solution for bio-inspired artificial perception or robotic systems, and also provides a new platform for further studying the principles and functions of biological vision systems.
Auditory is vital for humans, as it enables us to comprehend language, communicate, explore our surroundings, and stay alert to potential threats. In the biological nervous system, sound localization is crucial for foraging and avoiding predators. To address this, He et al reported an artificial neural system that uses capacitively coupled gate electrodes to emulate the left and right ears (PREN1 and PREN2) and connect to the processing unit (POSTN1 and POSTN2) via the chitosan electrolyte's lateral capacitive coupling effect, enabling sound localization [105]. When sound arrives from different directions, POSTN1 and POSTN2 respond differently, allowing the network to determine the sound's azimuth angle. Zhong et al developed an oscillation neuron based on NbO x to mimic direction selectivity and sound localization [106]. The spiking performance of artificial neurons is highly adjustable, particularly affected by time differences between different inputs, enabling them to emulate perception functionalities that rely on spatiotemporal processing. More recently, Gao et al developed a neuromorphic algorithm and architecture that can process the complete sound signals received by both ears and achieve online learning of sound source localization on a 1K analog resistive switching devices array (TiN/TaO y /HfO x /TiN), as shown in figure 6(g) [99]. The algorithm and architecture refer to the structure and function of neurons and synapses in the biological brain and use a multithreshold-update scheme that can effectively solve the problems of nonlinearity, heterogeneity, and drift in the array. The artificial perception system based on neural morphic devices enables the acquisition, analysis, and processing of various sensory signals, including light, sound, temperature, and pressure, from complex environments by emulating human abilities such as vision, hearing, and touch. It is a key technology for achieving intelligent robots, virtual reality, and other applications in the future. The combination of artificial perception and neuromorphic devices offers broad applications and prospects. On one hand, neuromorphic devices can provide a hardware platform better suited for artificial perception tasks. For instance, using dedicated artificial synapse devices, it is possible to achieve rapid, low-latency, and low-power image recognition, object detection, scene understanding, and other visual information acquisition and processing tasks. Combining one or more neuromorphic devices enables the fusion and collaborative processing of multimodal information. For example, the combination of visual and tactile information can facilitate precise object grasping. The adaptive learning capability of neuromorphic devices allows artificial perception systems to learn and optimize based on environmental feedback and reward signals, leading to more intelligent decision-making, which is significant for intelligent control systems and human-machine interaction. Furthermore, flexible perception systems can adapt to curved surfaces, dynamic deformations, mechanical stress, and temperature changes by leveraging the characteristics of flexible devices [107][108][109]. This promotes biocompatibility and enables interaction with biological signals. Additionally, the integration of neuromorphic devices and artificial perception systems can drive the development of brain-machine interfaces and human-machine integration. Efficient interaction between the human brain and computers can be achieved by perceiving brain signals, enabling a wide range of applications such as augmented reality, brain-computer control, and rehabilitation therapy. On the other hand, the exploration and implementation of these applications face numerous challenges. Designing perception systems with biological realism, programmability, and scalability; developing algorithms and coding strategies suitable for artificial perception systems; and evaluating and validating the actual performance and effectiveness of various neuromorphic devices in artificial perception systems are among the challenges that need to be overcome. The integration of artificial perception systems and neuromorphic devices is a forward-looking and innovative research direction. Through interdisciplinary collaboration and continuous exploration, it not only provides people with more intelligent, convenient, and secure services but also offers new insights and approaches for revealing the mechanisms of the human brain.

Neuromorphic computing
Neuromorphic computing involves the use of analog, digital, or hybrid circuits and software algorithms to emulate biological neural networks. This approach seeks to mimic the structure and function of the human brain to achieve more efficient and effective computing. As a core technology in the field of artificial intelligence, neural networks have found widespread application in areas, such as image recognition, speech recognition, and natural language processing. Several popular and effective neural network architectures include convolutional neural networks (CNNs), deep neural networks (DNNs), and SNNs. These architectures differ in their structures and algorithms, each with its strengths and limitations for specific application scenarios. For instance, CNNs are primarily used for image recognition and processing tasks. They employ a hierarchical structure with multiple layers of convolutional filters to extract features from input data. DNNs are commonly employed in speech recognition and computer vision. They consist of multiple layers of interconnected nodes that can learn complex relationships between input data and desired outputs. SNNs, on the other hand, more closely mimic the operation of human brain neurons. They use spikes or pulses to transmit information between neurons and can learn through changes in synaptic strength. Each of these architectures has its advantages and limitations. CNNs are well-suited for tasks involving spatially correlated data such as images, but can require significant computational resources. DNNs can learn complex relationships between inputs and outputs but can be difficult to train due to their large number of parameters. SNNs offer the potential for more energy-efficient computing but are still an active area of research with many challenges to overcome.
In the realm of machine learning, particular requirements must be met by neuromorphic devices for both inference and training. During inference, synapse arrays store weights and perform parallel multiply-and-accumulate (MAC) operations on a massive scale. As such, these devices must have good retention characteristics, and high-precision polymorphism is not a strict requirement. Training processes necessitate the updating of each node in the weight matrix, thereby requiring good endurance, speed, and energy efficiency. As DNNs are widely used in the field of artificial intelligence, improving the training efficiency and energy performance of DNNs becomes an important issue. A promising solution is analog in-memory computing based on crossbar arrays of resistive switching devices, which can use the resistance state to store and process the weights and activation values of neural networks, thereby achieving high-speed and low-power neural network computation. However, due to the challenges in engineering and circuit integration of resistive switching device characteristics, the ability to perform in situ learning on large-scale multi-layer neural networks is still difficult. Li et al constructed a multi-layer neural network by monolithically integrating hafnium oxide-based resistive switching devices and transistor arrays on a silicon chip, as depicted in figure 7(a) [110]. They adopted an online learning algorithm that updates the weights of neural networks by adjusting the voltage pulses of resistive switching devices and used transistors to control the read-write operations of resistive switching devices and the implementation of activation functions. They experimentally demonstrated the capability of in situ learning on largescale multi-layer neural networks, and achieved competitive classification accuracy on a standard machine learning dataset, as illustrated in figures 7(b) and (c). This work provides references and insights for further optimizing the device characteristics and circuit design of resistive switching devices, improving the scale and performance of neural networks, and exploring more complex learning algorithms and application scenarios.
CNNs have revolutionized image processing tasks such as image recognition and object detection. However, computing CNNs involves numerous sliding convolutional operations, and efficient parallel computing units that support MAC calculations are crucial. Resistive switching arrays can perform parallel in-memory MAC operations by applying Ohm's law for multiplication and Kirchhoff's law for accumulation [114]. This analogue in-memory computing can enhance speed and energy efficiency, but challenges remain with resistive switching device-based CNN hardware such as non-uniform crossbar arrays, conductance drift, device state locking, and slow convolution times [115,116]. To overcome these difficulties, Yao et al proposed a fully hardware-implemented CNN to perform matrix-vector multiplication (MVM), which is a crucial operation in CNNs, as illustrated in figures 7(d)-(g) [111]. This work is highly significant and promising for neuromorphic computing. The use of resistive switching devices as hardware accelerators has been an active area of research, and this work represents a major step forward in this field. This is a significant contribution to the field of AI and hardware design, as it provides a pathway for developing more energyefficient and sustainable AI systems. Although MVM is feasible in a fully integrated resistive switching device in-memory computing system, the current hardware design cannot satisfy the simultaneous application requirements of high energy efficiency, versatility, and accuracy. Currently, the reported results are achieved through software emulation based on characterized device data [117,118], which tends to overestimate accuracies due to incomplete modeling of hardware non-idealities. Therefore, it is critical to design a hardware system with high energy efficiency, support for different network structures, and accuracy comparable to software results for the practical application of in-memory computing chips. To address this challenge, they also proposed a resistive switching device-based system depicted in figures 7(h) and (i) [112]. This collaborative optimization solution significantly enhances the performance, efficiency, and versatility of edge devices, enabling the deployment of cloud tasks at the edge. The successful testing and demonstration of these chips have strongly demonstrated the feasibility of resistive switching device-based in-memory computing architecture.
Currently, the bulk of existing systems that utilize resistive switching devices are built using conventional 2D crossbar arrays. Nevertheless, their uncomplicated interconnections are inadequate for effectively implementing the complete topology of more intricate structures within ANNs. Consequently, a radical revolution in architecture design is imperative. This shift requires the formulation of fresh design tactics and technical methods to augment the programmability and flexibility of device arrays, thereby enabling more astute and effective computation [113]. Although 2D crossbar arrays can alleviate the problem of sneak paths by adding transistors as selection devices, this solution cannot be applied in 3D circuits. To address this limitation, Lin et al developed a prototype 3D array with specially designed connections that use 'localized connections' to connect resistive switching devices with only a few nearby devices, as shown in figure 7(j) [113]. This unique design strategy effectively suppresses most sneak paths and enables large-scale array operation, making it capable of performing parallel convolution kernel operations in CNNs. The utilization of 3D design endows a significant level of functional intricacy, surpassing the capacity of increasing packing density in traditional 2D architectures, thereby paving a crucial path towards employing resistive switching devices for neuromorphic computing. Recently, Huo et al demonstrated a new approach for integrating computation and memory functions using a 3D resistive memory array, which is an important step towards achieving more intelligent and efficient computing systems [119]. The unit structure, as shown in figure 8(a), adopts a stacked structure of 3D resistive memory and peripheral computing circuits, which enables integrated storage and computing functions based on a 3D vertical resistive memory array. The use of a 3D design allows for greater functional complexity, which is crucial for implementing the full topology of complex structures in ANNs. Additionally, the proposed anti-drift multibit analogue input-weight multiplication scheme addresses some of the limitations of conventional input schemes and has the potential to significantly improve the performance of memristive device-based systems, as shown in figure 8(b). The present study offers distinctive technical benefits for 3D neural network computing, which holds significant potential for the realm of edge intelligent computing. The integration of memory and computing achieved through this work can significantly broaden the scope of its development and application.
Arrays of three-terminal devices can achieve precise conductance modulation due to the separation of programming and reading terminals [122]. Ferroelectric transistors offer precise modulation by controlling the polarization state and have other beneficial characteristics. These properties make them suitable for implementing kernel weights in convolution operations within ferroelectric transistor arrays. Kim et al recently proposed a HfZrO x ferroelectric transistor synaptic array [123]. The channel conductance can be linearly adjusted by altering the transistor's polarization state. Moreover, by selectively controlling polarization, the device array can achieve parallel programming operations for columns and rows. The array can be trained to execute kernel weights and convolution operations using these features of the device. It demonstrated a recognition accuracy of over 90% in subsequent image recognition tasks. This study has significant implications for advancing neural morphology computing through ferroelectric transistors. In addition, Kim et al proposed a 3D ferroelectric NAND array that uses vertical ferroelectric transistors as storage units [68]. The array showed an accuracy of 93.8% in recognition tasks on handwritten datasets.
As previously discussed, to train DNNs effectively using synaptic arrays, it is crucial to precisely align weight modifications in training algorithms with the memory hardware's characteristics. The conductance modification used for weight modulation must be symmetrical for positive and negative stimuli and possess high accuracy with minimal cycle-to-cycle fluctuations. Failure to do so can have a significant impact on training accuracy [124]. The channel conductance of electrochemical synaptic transistors can be precisely adjusted by regulating electrochemical intercalation reactions using a bias applied to individual gate terminals. Unfortunately, the current demonstrations of electrochemical transistors are hindered by their lack of compatibility with silicon CMOS technology. In many electrochemical devices, liquid or organic polymer electrolytes are commonly used [125]. Although these devices exhibit good performance, it is challenging to integrate them into circuits as synaptic units that offer the reliability needed for neuromorphic applications, and they frequently only function under controlled environments. Cui et al recently introduced an all-solid-state electromechanical chemical transistor that mimics biological synaptic function via reversible ion insertion and extraction. The device's structure is illustrated in figure 8(c) [120]. Furthermore, they established a pseudocross array that can execute parallel simulation programming and MVM, as demonstrated in figure 8(d).
Since 2D materials were first included in the International Roadmap for Devices and Systems as transistor channel materials, the semiconductor industry has been focused on using the exceptional electronic properties of 2D materials to manufacture advanced electronic circuits. 2D semiconductors, particularly represented by transition-metal dichalcogenides, are considered highly promising channel materials. After over a decade of development, 2D semiconductors have demonstrated strong potential in sub-1 nm technology nodes as well as the low-temperature 3D back-end of line integration [126]. Additionally, devices based on 2D semiconductors have found extensive applications in simulating neurons and synaptic plasticity, opening up new avenues for neuromorphic computing. Recently, Ning et al reported a tunable duplex device structure based on a MoS 2 ferroelectric FET [127]. The proposed novel in-memory computing architecture can achieve in situ machine learning, which means performing both training and inference at edge computing. This can avoid the data transfer and processing bottleneck in the traditional cloud-edge separated model, and improve data security, realtime, and bandwidth. The authors used the advantages of 2D materials to construct a duplex device structure that realizes efficient integration of memory and computation. This architecture can simulate the synaptic and neuronal functions in neural networks, and show high accuracy in a complex task. They also demonstrated the high energy efficiency and scalability of this architecture, providing a powerful candidate for achieving general edge intelligence. Currently, most research based on 2D materials neuromorphic devices has been constrained to producing and examining individual large-scale devices on non-functional SiO 2 /Si substrates. Most recently, Zhu et al presented 2D/CMOS hybrid microchips for neuromorphic applications, as depicted in figure 8(e) [121].
To integrate 2D materials into microelectronic products and memristive applications, the researchers transferred a multilayer hexagonal boron nitride (h-BN) sheet onto the backend-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node. By utilizing CMOS transistors, they can control the currents across the h-BN memristors with exceptional precision. Additionally, they demonstrated the construction of logic gates and measured the STDP rule suitable for implementing SNN, as illustrated in figure 8(f). This technological breakthrough represents a significant advancement in the readiness level of this field. The successful production of high-density hybrid 2D/CMOS chips with high performance and technological maturity marks a substantial advancement in this field.

Conclusion and perspectives
This review has examined recent advances in neuromorphic devices, including their emulation of biological synapses and neurons and their applications in neuromorphic computing. These devices, compatible with CMOS fabrication technology, hold great potential for development and could significantly impact and innovate the design and development of brain-like chips in the future. The continued development of neuromorphic devices and systems using CMOS technology offers several clear advantages. Firstly, ultra-low power consumption: CMOS technology is renowned for its low power consumption, and neuromorphic devices processed using this technology exhibit satisfactory power consumption performance, further improving computational efficiency. Secondly, high-density integration: neuromorphic devices compatible with CMOS technology can utilize existing integrated circuit processes and equipment to achieve high-density, highly integrated designs, and more complex neuromorphic computing. Thirdly, high reliability: neuromorphic devices compatible with CMOS technology can exhibit high stability and reliability and operate stably for extended periods to achieve reliable computing. Fourthly, strong scalability: neuromorphic devices compatible with CMOS technology can be upgraded and expanded using existing processes to achieve more advanced functions and provide greater development potential for neuromorphic computing. Finally, low production cost: neuromorphic devices compatible with CMOS technology can be mass-produced using existing production processes, reducing production costs and promoting widespread application.
Neuromorphic devices or systems that are compatible with CMOS technology have potential applications in various fields such as robotics, the Internet of Things, biomedicine, security, education, etc. In each field, neuromorphic devices or systems can offer specific advantages. For instance, robotics can enable more natural human-computer interaction, more flexible action control, and more intelligent environmental perception and decision-making. In the Internet of Things, they can enable more efficient data processing and transmission, more energy-efficient device management, and more secure information encryption and authentication. In biomedicine, However, different application fields also pose different technical challenges and constraints for neuromorphic devices or systems that are compatible with CMOS technology. For example, in robotics, they need to be fast, precise, and sensitive to cope with complex and dynamic environments and tasks. In the Internet of Things, they need to be low-power, low-cost, and low-latency to cope with large-scale distributed networks and devices. In biomedicine, they need to be biocompatible, stable, and safe to cope with physiological conditions and medical standards both inside and outside the human body. Undoubtedly, the scientific and engineering challenges associated with this endeavor are formidable. From a biological standpoint, our current understanding of brain neural networks remains rudimentary. The development of neuromorphic devices necessitates breakthroughs in various natural sciences, including neuroscience, mathematical simulation, and chemistry/physics. Achieving these breakthroughs will require deep integration of multiple disciplines, including materials science, chemical engineering, medicine, computer science, and engineering. From an engineering perspective, the challenges primarily lie at the device level. Currently, device characteristics exhibit significant variations in terms of timescales, dynamics, and technological maturity, which increase the difficulty of selection, optimization, and iteration. Two-terminal switch devices, represented by resistive random-access memory (RRAM), demonstrate high potential for applications. For instance, RRAM crossbar arrays can seamlessly integrate with CMOS circuits, offering advantages in large-scale data analysis and computation, such as high integration density and read/write speed. The higher endurance and data retention characteristics of RRAM provide reliable data storage and computation. Additionally, the programmability and flexibility exhibited by RRAM make it more advantageous than traditional devices in implementing neuron and synapse models. However, challenges also exist. The resistance state variation in RRAM exhibits a certain degree of randomnesses, such as ion migration or oxidation/reduction processes, leading to performance disparities among devices and reliability challenges. This implies the need for more complex circuits and algorithms to compensate for this randomness. In this regard, spin electronic devices exhibit outstanding stability and reliability, but their low dynamic range remains a major technical barrier to the widespread application of such devices. Furthermore, RRAM's performance and reliability may be sensitive to temperature variations, as changes in device resistance state and data retention capability may be affected in high-temperature environments. Despite the advantages of RRAM in CMOS compatibility, it is still in its early stages compared to traditional memory technologies, and addressing manufacturing costs and supply chain challenges is necessary for commercialization and large-scale applications. Neuromorphic transistors with multiple weight-adjustment surpass RRAM in plasticity, and their fast switching speed makes them suitable for real-time data processing and edge computing tasks. Additionally, these devices exhibit excellent power efficiency. However, achieving consistency and repeatability among transistors in large-scale manufacturing processes, as well as implementing heat dissipation design and power management, may pose challenges. Furthermore, achieving high-density integration is also a significant issue, which requires considering the balance between various device aspects such as size, speed, and stability, while also addressing the adjustability and flexibility of devices to meet application requirements. Table 1 provides a comparison of various device types, each with its advantages and disadvantages in terms of power, performance, and area (PPA) metrics.
These PPA metrics mean different things in different applications. For example, in applications that require realtime processing of large amounts of data, such as image recognition or natural language processing, performance and power are more important than area. In applications that require embedded or portable systems, such as wearable devices or smart sensors, power, and area are more important than performance. Therefore, choosing the appropriate device for neuromorphic computing depends on the application scenario and the trade-offs between PPA metrics. Although hardwarebased neuromorphic computing offers many advantages, software simulation is currently still a low-cost solution because it does not require hardware design, manufacturing, and testing, and maybe a more suitable choice in some cases. Certainly, the drawbacks of software simulation are also evident. The speed of software simulation heavily relies on the processing capability and resources of the computer, and it is challenging to achieve large-scale parallel computing, limiting the overall system performance. Although hardware-based simulation has disadvantages such as high development and deployment costs and limited flexibility, these circuits and architectures are highly optimized, enabling highly parallelized and efficient computation. The low power consumption exhibited by hardware systems is particularly beneficial for applications in mobile devices, embedded systems, or energy-constrained environments. Additionally, hardware-based implementations can provide real-time responsiveness and processing capabilities, which surpass software simulation in this aspect. Therefore, when choosing the implementation approach, it is necessary to consider application requirements, resource constraints, and implementation costs comprehensively.
Despite the significant challenges posed by science and engineering, the development of neuromorphic devices and systems based on CMOS technology remains a promising direction for advancing AI and brain science. The development of neuromorphic devices that conform to CMOS technology offers numerous advantages for the advancement of neuromorphic computing. It is essential to thoroughly evaluate the actual performance, stability, and reliability of these devices, as well as their integration with other computing technologies. A comprehensive selection of the most suitable technical approach is necessary. We hope that this review will provide valuable insights and perspectives for researchers interested in this field.