Manufacturing of graphene based synaptic devices for optoelectronic applications

Neuromorphic computing systems can perform memory and computing tasks in parallel on artificial synaptic devices through simulating synaptic functions, which is promising for breaking the conventional von Neumann bottlenecks at hardware level. Artificial optoelectronic synapses enable the synergistic coupling between optical and electrical signals in synaptic modulation, which opens up an innovative path for effective neuromorphic systems. With the advantages of high mobility, optical transparency, ultrawideband tunability, and environmental stability, graphene has attracted tremendous interest for electronic and optoelectronic applications. Recent progress highlights the significance of implementing graphene into artificial synaptic devices. Herein, to better understand the potential of graphene-based synaptic devices, the fabrication technologies of graphene are first presented. Then, the roles of graphene in various synaptic devices are demonstrated. Furthermore, their typical optoelectronic applications in neuromorphic systems are reviewed. Finally, outlooks for development of synaptic devices based on graphene are proposed. This review will provide a comprehensive understanding of graphene fabrication technologies and graphene-based synaptic device for optoelectronic applications, also present an outlook for development of graphene-based synaptic device in future neuromorphic systems.

These authors contributed equally to this work. * Author to whom any correspondence should be addressed.
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Introduction
Artificial intelligence (AI) and the internet of things technology have sharply increased the demand for computility improvement, big data accessibility and training modes evolution [1][2][3]. The traditional computers are facing the challenges of high energy consumption and low computational efficiency due to limitation of von Neumann configuration. Therefore, it necessitates the exploration of novel computing architectures to tackle such technological contradiction. The biological brain can conduct parallelizing data storage and processing, which enables effective execution of complicated tasks such as recognition and classification. Specifically, the implementation of intelligent functionalities in human brain relies on the complex networks that composed of ∼10 11 neurons and ∼10 15 synapses, each of which acts as a computation and memory block [4,5]. The information that one neuron can transmit to the next is permitted by neurotransmitter flow inside synapses that regulate the signal strength (namely synaptic weight). The highly interconnected network architecture endows the brain with energy-efficient (∼10 fJ per synaptic event) and error-tolerant computing capability, especially for learning, perception, and judgment. Thus, neuromorphic computing is a promising way to break von Neumann bottleneck and access efficient parallel computing technology. As a hardware support, devices and circuits that mimic the functionalities of biological synapses are urgent for the development of future computing [6,7].
With the discovery of novel memory mechanisms and architectures, various artificial synaptic devices have been successively demonstrated, such as two-terminal memristors based on redox-active, phase-change or ferroelectric materials, and the devices with three-terminal transistor architectures [8,9]. The mature complementary metal-oxide-semiconductor (CMOS) processing technique allows the construction of large-scale networks of memristive devices; however, the execution of data processing and storage are still depended on electrical signals through metal wiring, which is unconducive for the implementation of high-performance neural networks [10]. Specifically, utilizing metal wiring for each connection is impractical in an electronic system that possesses an interconnection scale comparable to the biological neurons' connectivity, since each neuron is massively connected to 10 3 -10 4 other neurons in the brain [11]. In addition, the metal wire connections suffer from high attenuation and generate more Joule heat as a function of total wire length [12,13]. Therefore, the electrical-only operation mode restricts the multiplicity of the artificial synaptic systems.
Fortunately, introducing photonic circuits to construct optoelectronic neuromorphic computing architectures can reenforce the interconnectivity, operational linearity, and diversity of applications owing to their unique advantages of large optical bandwidth, high interference-resistance, minimized signal delay and power loss [14]. The optical signals in the systems can play the roles as input, modulator, and output of the optoelectronic synaptic devices. Particularly, to a certain extent, the light-to-electricity signal conversion in the optoelectronic synaptic devices is analogous to biological visualperception systems that incorporate visual sensing, signal transfer, and pattern memory/recognition [15][16][17]. Thereby, researchers have been vigorously committed to the development of optoelectronic synapses and the optoelectronic synaptic behavior emulation. Notably, the implementation of optoelectronic synaptic devices relies on a unique light-matter interaction, which requires desirable functional material and rational device architecture. The common design principles in traditional optoelectronic devices (e.g. photodetector, photodiode, and solar cell) can be adapted for the development of optoelectronic synaptic devices, while appropriate changes have to be made since the device needs to possess memory functionality [18]. Thus, exploration of ideal materials and device architecture is predominant in optoelectronic synaptic devices [19].
Graphene, a honeycomb-like monolayer that consists of sp 2 hybridized carbon, has been extensively investigated for optoelectronic applications, owing to its robust stability, high carrier mobility and excellent optical transparency [20,21]. Besides, the properties of graphene can be tailored through various physical or chemical treatments, such as cutting graphene into nanoribbons and quantum dots (QDs), doping heteroatoms into graphene, and constructing van der Waals (vdWs) heterostructures [22][23][24]. Thus, graphene can construct material systems with a wide range of electronic, optical, and optoelectronic properties, which can be employed to play various roles in diverse optoelectronic applications. Moreover, blooming in processing technology allows wafer-scale growth of single crystal graphene (SCG), realization of graphene nanopatterning, and uniform transfer of graphene, providing vital technical support for the fabrication and integration of graphene devices [25][26][27][28].
In this review, we focus on the recent progress in manufacturing graphene-based synaptic devices and their applications in optoelectronics. First, a general introduction of graphene structure/property and processing technologies, including synthesis, patterning, and transfer methods toward devices fabrication and integration is carried out. The common issues in each processing technologies and their impact on the optoelectronic properties are also systematically discussed. Then, the working principles of synaptic devices based on graphene are surveyed to unveil the roles of graphene in the devices. Moreover, innovative applications of graphene-based optoelectronic synaptic devices in neuromorphic systems are reviewed and discussed. Finally, conclusions and prospects for future multifunctional neuromorphic optoelectronic systems of graphene-based synaptic devices are presented. Figure 1 illustrates the overview of this review article.

Materials
Graphene usually exhibits a degenerated performance rather than intrinsic one due to the introduction of structural disorder during the synthesis and processing procedure. In this chapter, we briefly introduce the structure and property of graphene. Then, advanced manufacturing technologies related to graphene integration, including the synthesis of large area single crystal, on-chip transfer and patterning, are comprehensively reviewed.

Structure and property
Graphene is the first isolated honeycomb-like, single-atomthick, sp 2 -hybridized two-dimensional (2D) carbon crystal, which has drawn tremendous attention since 2004 [29]. Owing to the unique crystal structure, graphene exhibits a gapless energy band and a semimetal behavior, which possess conical energy bands that are centrally intersected at Dirac point [30]. Thus, graphene highlights the applications in electronic and optoelectronic fields due to its ultrawideband tunability, excellent electron mobility (>15 000 cm 2 V −1 s −1 ), environmental robustness and outstanding mechanical flexibility [31,32]. In addition, zero-bandgap nature also offers a versatile platform for modulation of chemical potential or Fermi level via chemical or physical doping, promoting efficient dynamic tuning of its electrical, optical, and optoelectrical performance [33][34][35]. Moreover, chip-level integration of graphene-based devices features small footprint, low energy consumption, strong scalability, and large-scale producibility. Implementing integrated devices based on graphene requires comprehensive manufacturing technologies, which are crucial for achieving excellent performance and high reproducibility.
With the atomically thin nature, the properties and device performances are highly depended on the disorder in graphene material, including both intrinsic disorder originating from crystalline defects and extrinsic disorder resulting from the environmental condition [36,37]. In particular, the general fabrication process involves synthesis, transfer, and patterning, each of which could introduce structural disorder into graphene (figure 2(a)) [38]. The intrinsic disorder in graphene is dominated by synthesis process, including vacancies, substitutions, edges and grain boundaries [37]. Notably, grain boundaries are common problems in preparation of large-area SCG monolayer and predominant to their properties, especially, charge conductivity in electronics [39]. The extrinsic disorders such as contamination, strain/crack, roughness/wrinkle, and oxidation usually come from graphene transfer process. Such disorder can play various roles to affect multiple properties, such as changing the electrostatic potential, scattering the charge carriers, altering the local electronic band structure, and acting as recombination centers for excitons [37,40]. Moreover, patterning processing could tailor the 2D graphene into lower-dimensional materials such as 1D graphene nanoribbon (GNR) and 0D graphene QDs. The lateral quantum confinement effect together with atomically thin nature endows low-dimensional graphene with various useful electronic properties, including tunable bandgap, localized spin and topological edges states (figure 2(b)) [22,41]. Thus, patterning graphene could not only benefit large-scale integration, but also bring new opportunities for graphenebased devices. The contaminations and other graphene heterostructures could induce n-type or p-type doping to graphene. Rational design of graphene heterostructures can offer an excellent platform for exploiting the full potential of graphene for broad applications.

Synthesis
Synthesizing high-quality graphene materials with large-area and controllable thickness is an essential prerequisite for their large-scale integration. Graphene was first found and obtained by adhesive tape-assisted mechanical exfoliation. Till now, this method can provide best graphene flakes concerning purity, defects, mobility and optoelectronic properties. Besides, many efforts have been made to produce high quality graphene, such as liquid phase exfoliation [42], chemical vapor deposition (CVD) [43], annealing of carboncontaining substrates [44], and reduction of graphene oxide [45]. Although various optoelectronic devices have proposed diverse requirements for functionality of graphene, the graphene synthesis technologies are generally moving towards high yield, controllable morphology, and large area. In this section, we focus on the synthesis methods toward large-area SCG that are potential for scalable and industrial applications.

Layer-engineered exfoliation (LEE).
Mechanical exfoliation represents peeling off a few layers from bulk graphite by means of adhesive films (scotch tape [46], metal film [47]). The modified scotch tape approach enables the preparation of monolayer and few-layer graphene flakes with the lateral size up to hundreds of micrometers. In a typical process, the oxygen plasma cleaning of substrate and extra heat treatment facilitate uniform contact area at the interface between the graphene and substrate, resulting in large area, high-quality but random thickness graphene [46]. Recently, LEE technique has been developed to provide thicknesscontrollable graphene with lateral size up to millimeter-scale. As depicted in the schematic diagram in figure 3(a), to perform LEE process, a certain metal film is firstly deposited on the bulk graphene to form a metal/graphite contact, followed by typical poly(methyl methacrylate) (PMMA)-assisted exfoliation method. The metal films act as stressor to give different tensile stress on graphite owing to the difference in lattice mismatch at metal/graphite interface. The different binding energy between metal film and graphene (γ M-Gr ) Figure 3. Common processing techniques for large-scale single crystal graphene preparation. (a) Schematic diagram of layer-engineered exfoliation, in which the binding energy of graphite/metal determines the thickness exfoliated graphene. (b) Illustration of controllable growth of single crystal graphene (SCG) from a single graphene seed. (c) Controllable growth of centimeter-sized graphene by local feeding strategy. Reproduced from [54], with permission from Springer Nature. (d) Illustration of controllable growth of SCG from seamless merged graphene domain. (e) Low-energy electron diffraction (LEED) confirming the single-crystal structure of graphene grown on H-Ge (110). From [51]. Reprinted with permission from AAAS. leads to various spalling depth during the exfoliation. For example, the Au film on graphite generates a moderate binding energy at Au/graphene interface (γ M-Gr = 30 meV atom -1 ), which is slightly higher than that between graphene-graphene (γ Gr-Gr = 21-25 meV atom -1 ). This small difference in binding energy determines shallow spalling depth and allows the cleavage of a large-area graphene monolayer. Importantly, such graphene monolayer can be obtained from the same bulk graphite by repeating the LEE operation. Moreover, the metals (Pd, Ni, Co) possessing high γ M-Gr enable successful exfoliation of thicker multilayer graphene, which can be employed to exfoliate multigraphene of bilayer, 8 nm-thick, and 20 nm-thick, respectively. Therefore, the LEE approach, as a mechanical exfoliation method, has exhibited immense potential in industrial-scale process for graphene products fabrication.

CVD.
CVD is considered as a powerful tool for the large-area growth of graphene, which has been successfully achieved on various surfaces such as transition metal substrate [26,[48][49][50], sapphire [25], germanium [51], hexagonal boron nitride [52], silicon [53]. However, conventional CVD methods usually produce polycrystalline films with considerable grain boundaries, which lead to a degradation of electronic and optoelectronic properties. Moreover, CVD preparation of SCG film suffers from high-cost and poor scalability, while long growth time (from hours to days) or high-priced singlecrystalline catalytic substrates are required for a wafer-scale film. To achieve scalable and controllable preparation of SCG, extensive works have been done in the engineering of the growth substrates. Two common strategies have been adopted in the CVD growth of SCG, including controllable growth of a single crystal nucleus and seamless merging of unidirectional multiple graphene islands.
Strictly controlling the growth of a single crystal nucleus could promote the formation of SCG, for example, wafer-scale SCG films have been prepared on a polycrystalline Cu/Ni alloy using a local control of carbon feeding (figure 3(b)) [54,55]. In this strategy, a quartz nozzle was applied to feed carbon source (methane flow), which can restrict the carbon supersaturation in one tiny area on Cu/Ni alloy substrate. Thus, on the entire substrate, only one single nucleus formed and grew rapidly owing to the optimized alloy-induced isothermal segregation that facilitated SCG formation (figure 3(c)). The optimized Cu 85 Ni 15 alloy surface allowed the synthesis of an centimeter-size monolayer SCG within ∼2.5 h [54]. Also, introducing trace oxygen (in the range of 10 −2 -10 −6 atomic %) on Cu foil has also been proved as an effective approach to limit the nucleation density and prepare centimeter-scale SCG. However, the synthesis of one-centimeter-sized SCG domains costs ∼12 h [56]. Therefore, the main challenges in preparation of SCG by growth of a single nucleus are lying on the graphene size and growth efficiency, hence hindering their commercial-level manufacturability.
To overcome these challenges, an alternative strategy to achieve continuous SCG film can be described as seamless merging of unidirectional growth of multiple graphene domains (figure 3(d)) [48,51]. Therefore, simultaneous growth of multiple domains can lead to a great reduction of the growth time, which can prepare submeter-size SCG film within a few minutes. For this strategy, the key challenge lies in the design and engineering of the appropriate single crystal substrates which needs to meet two key functions: one is the capability to form unidirectional graphene crystal seeds and retain the orientation during grow-up; and the other is the elimination of possible atomic position mismatch in adjacent graphene islands. For example, Lee et al [51] demonstrated a wafer-scale growth of wrinkle-free SCG monolayer on H-terminated Ge (110) surface. H-terminated Ge (110) surface features anisotropic two-fold geometry, facilitating the nucleation of unidirectional aligned multiple graphene seeds (figure 3(e)). Owing to the high barrier of graphene rotation, the multiple seeds can retain the perfect aligned edges and grow up to form graphene islands. Notably, atomic position mismatch may exist at the edges of two adjacent graphene islands before merging, which may form a non-tilt grain boundary in the graphene layer. With the extremely weak adhesion between the graphene islands and underlying Hterminated Ge surface, the possible atomic position mismatch can be automatically corrected during coalesce of the islands to yield SCG monolayer. Besides, some specific metallic surfaces possess appropriate carbon solubility, minor lattice mismatch between metallic surface and graphene, small percentage of misoriented graphene islands, and weakly coupling with graphene due to the nearly liquid state of metallic surface at CVD growth temperature. These factors are beneficial for the merging of graphene islands to form large area SCG. To reduce the costs, metal substrate, for example Cu, has been utilized as catalyst for millimeter-sized SCG growth [57]. The melting and subsequent solidification process provide an ultra-smooth Cu surface that restrict the nucleation of graphene and promote its growth to form large area crystals. Interestingly, a layertunable AB-stacked SCG films can be achieved on Cu/Ni (111) alloy with optimized Ni content [50].

Transfer of graphene
Ideal transfer techniques enable intact and clean transfer of large-area graphene onto various substrates, which bridge the gap between large-area high-quality graphene growth and ultimate high-performance device fabrication [27,58]. Although high-quality graphene can be obtained by CVD growth on metals or exfoliation from bulk materials, various defects such as wrinkles, cracks and impurities are usually introduced into the graphene during the transfer process, inhibiting the performance of the graphene in electronic and optoelectronic devices including carrier mobility, contact resistance, and endurability [40]. Therefore, efficient transfer methods that endow transferred graphene with high uniformity, integrity, and cleanliness are highly desired. Briefly, transfer of CVD graphene onto the target substrate involves three major steps: (i) depositing supporting layer on graphene surface; (ii) separating graphene from growth substrate; (iii) releasing graphene onto target substrate and removing supporting layer (figure 4(a)) [59]. In the past two decades, diverse strategies have been developed to optimize these three steps of transfer methods.

Deposition of supporting layer.
Atomically thin graphene is unable to retain large-area self-supporting, thus, a supporting layer is usually adopted to protect graphene from structural damage during the transfer process [60,61]. Presently, polymer thin films are widely applied as the supporting layer for transferring graphene. The criteria of polymer selection include: (i) sufficient mechanical strength and suitable flexibility; (ii) good adhesion with graphene and transfer medium; (iii) high resistance for chemical solution during the transfer process; (iv) completely removable without residues. PMMA has emerged as the most commonly used supporting layer for CVD-grown graphene transfer since 2008 (figure 4(b)) [59]. In a typical process, PMMA film, as a supporting layer, is first spin-coated onto graphene/metal-foil stack. Then, PMMA/graphene/metal-foil stack is transferred to the etchant solution such as FeCl 3 , HCl, HNO 3 , Fe(NO 3 ) 3 , or CuCl 2 , until the end of metal etching process. Subsequently, the PMMA/graphene stack is thoroughly cleaned with ultrapure water and positioned onto the desired substrate, followed by dissolving PMMA supporting layer with acetone. However, simple solvent washing cannot completely remove PMMA, whereas the residues of PMMA cause random doping and electrical performance deterioration in transferred graphene. The enhanced post-treatments have been demonstrated to reduce PMMA residues. For instance, exposing PMMA to UV irradiation can cleave their side-chain and thus weakened its adhesion with underlying graphene, resulting in less PMMA residues on graphene surface [62]. An intense condition with high temperature and pressure can significantly improve the solubility of PMMA [63]. Moreover, optimized organic solvent also plays important role to reduce the PMMA residues, where acetic acid performs better than acetone in some cases [64]. Post thermal annealing under vacuum after solvent washing can further decrease the polymer residues, but may introduce defects and substrate doping in graphene [65]. To perform cleaner graphene transfer, various alternatives to PMMA have been developed, including small molecules thin film (cyclododecane [66], pentacene [67], rosin [68], etc) and noble metal/polymer bilayer (Au [69], Ni [70], etc) (figures 4(c) and (d)). Moreover, the thermal release tape is a special supporting layer (or transfer medium), which offers tunable adhesion to facilitate separation of graphene from growth substrate and release graphene onto desired substrate.

Separating graphene from growth substrate.
The separating graphene from growth substrate can be achieved by aforementioned chemical etching process. Chemical etching offers a relatively mild process to delaminate graphene from the growth substrate, which can minimize the damage to graphene and maximize the integrity of graphene during the delamination (figure 4(e)). Since Cu and Ni are the mostly adopted substrates for graphene growth, the corresponding etchants are generally composed of FeCl 3 , HCl, HNO 3 , Fe(NO 3 ) 3 , CuCl 2 , Na 2 S 2 O 8 , and (NH 4 ) 2 S 2 O 8 . The strong oxidant like S 2 O 8 2− could oxidize PMMA layer, resulting in cracks generation in graphene/PMMA stack and degradation in graphene quality. FeCl 3 solution can conduct a mild etching of substrate but react with PMMA to leave intractable PMMA residues [71]. Moreover, one major issue in etching transfer is the metal/metal oxide residues that are probably originated from incomplete etching of substrate and/or residual etchant. The residual Cu and Fe still exceeds 10 13 atoms cm −2 even after thorough cleaning, which can alter the electronic properties of graphene and pollute other components in the device-based integration system [72]. Besides, etching method is a non-environmentally friendly method that could consume enormous metal substrate and generate a large quantity of liquid pollution in large-scale production.
Therefore, etching-free methods are preferable alternatives for clean graphene transfer, which enable separating graphene from growth substrate and maintaining substrate integrity. Generally, a considerable adhesion between graphene and growth substrate probably produces cracks in graphene during the separation and thus hinders the intact detachment of graphene. To facilitate high-quality etching-free transfer, the principal idea is weakening the interaction between graphene and growth substrate. Particularly, water intercalation or interfacial bubble generation have attracted intense interest (figure 4(f)). Etchant-free bubbling transfer methods can introduce bubbles at the graphene/growth-substrate interface, where the bubbles act as an external force to exfoliate graphene and promote delamination. The bubbles can be generated through chemical reaction. For example, a mixture system of NH 4 OH + H 2 O 2 + H 2 O has been developed to separate graphene from substrate via etching-free process [73]. The rapid decomposition of H 2 O 2 at 80 • C can generate massive oxygen bubbles. The as-produced oxygen bubbles diffuse into graphene/substrate interface, leading to gradual detachment and consequent complete separation of graphene. In addition, an electrochemical bubbling transfer can also enable the graphene delamination. In a typical electrolytic cell with aqueous electrolyte, graphene on the conductive growth substrate works as cathode while inert electrode (e.g. Pt) is used as anode. The water electrolysis can produce hydrogen bubbles at the interface between graphene and growth substrate, thus, delaminate graphene from growth metal substrate [74,75]. Certainly, electrochemical bubbling method can achieve highefficiency, low-cost, environmental-friendly transfer, as well as reuse of growth substrate, but, is unapplicable for insulating substrate. In addition, water molecules can intercalate into the interface between hydrophilic substrate and hydrophobic graphene, generating strong capillary force that can dynamically separate graphene from growth substrate (figure 4(g)) [76]. This simple process can almost completely eliminate the damage from chemical treatment. Since the water intercalation is a kinetic and thermodynamic process, hot water can accelerate the graphene lift-off. Moreover, the oxidation of metal substate benefits for improving its hydrophilicity and weakening the interaction between growth substrate and graphene [77]. Similarly, alkali solution also can induce hydroxyl ions on metal substrate to facilitate the detachment of graphene [78].

Transfer onto the target substrate.
Successful releasing of graphene onto the target substrate after delamination can retain high structural integrity of graphene, which requires a uniform and strong binding between graphene and target substrate (rigid and flexible substrate). In the cases of rigid substrates (e.g. silicon, glass, mica), pretreatment with oxygen plasma can greatly improve the cleanness and surface energy of substrate, which is beneficial for the formation of highquality contacts between substrates and graphene. However, the plasma-induced p-doping in graphene could alter the electronic properties of graphene. Moreover, when placing graphene onto target substrate, a certain amount of water or air could be trapped at graphene/substrate interface, which can cause wrinkle and structural crack in graphene. To avoid water trapping, one can use hydrophilic target substrate together with heating treatment for evaporating water, also, can use volatile liquids with low surface tension to replace water (figure 3(h)) [79,80]. To reduce air trapping, redeposition of supporting layer (like PMMA) after placing PMMA/graphene on target substrate has been demonstrated as an executable approach (figure 3(i)) [58]. For the flexible polymer substrate, a continuous transfer strategy, called roll-to-roll transfer, has been developed for meters-scale graphene, which can realize large-area conformal contact with the flexible target substrate (figure 3(j)) [81,82]. However, the transferred graphene usually possesses a relatively large surface roughness, partially hindering its application in optoelectronic devices. The transfer process usually ends with the removal of the polymeric support layer by solvent washing together with post-annealing. The utilization and removal of other kinds of support layers are discussed in the previous section. Notably, some transfer mediums such as thermal release tape and PDMS stamps are powerful tools to assist the transfer process.

Graphene patterning
The patterning of graphene can achieve the fabrication of graphene array for large-scale integration, and the nanostructures engineering of graphene for low dimensional graphene-based materials (e.g. graphene QDs, GNR) [22,83]. To obtain patterned graphene, various techniques have been proposed, which can be classified as bottom-up and top-down strategies. Bottom-up methods mainly include chemical reaction synthesis and CVD on patterned substrates. The former represents the molecular assembly of carbon-rich polyphenylenes through chemical engineering process, which mainly include polymerization, polycondensation, and cycloaddition reactions [24]. Till now, various nanographene and GNRs have been obtained by bottom-up molecular covalent assembly, which exhibits large surface areas, tunable pore sizes, tailorable chemical structures, and flexible chemical functionalities. On the other hand, the latter one, CVD on patterned substrates, represents the atomic assemble of carbon on the selected region on the pre-patterned substrates such as patterned metal substrate [84][85][86] and nanopatterned sapphire substrate [87]. Therefore, the bottom-up methods emphasize the need for precision synthesis in producing but hardly achieve wafer-scale arrangement. On the contrary, top-down methods represent the physical processing techniques that mainly involve selective etching or cutting of large-area graphene, which is compatible to the wafer-scale integration techniques. Over the past few decades, various nanomaterials, such as inorganic nanoparticles, nanowires, organic polymers, have been applied as masks for selective etching of graphene. Alternatively, a focused high energy laser can achieve patterning through direct writing without masks. Herein, we discuss two mostly adopted top-down methods for patterning graphene on chips, namely lithography and direct writing.

Lithography.
Lithography can replicate patterns to underlying substrates, which implements the manufacturing of low-dimensional structures/arrays in the micrometer/nanometer scale. Typically, Lithography-based patterning process involves 'mask' construction, selective etching, removal of 'mask'. Till now, various types of 'masks' have emerged such as photoresists, nanospheres, nanowires, colloids, and DNA [88]. Although almost all these lithographical approaches can be used for patterning graphene materials, the mainstream techniques, electron beam lithography (EBL) and photolithography, provides a promising way to promote the industrial scale manufacturing of graphene-based devices. The lithography patterning methods can be classified as (1) etching patterning and (2) lift-off patterning.
A typical process for etching patterning with the assist of lithography is illustrated in figure 5(a). A resist layer is first deposited onto a substrate-supported graphene by spin coating, then patterned via lithography. In general, EBL can provide high patterning resolution but require long exposure times, while photolithography, especially extreme ultraviolet lithography, can achieve sufficient resolution with high patterning efficiency that meets the needs of industrial scale and largevolume production. Subsequently, the graphene without the protection of resist is etched away by reactive ion etching, thus, replicating the pattern of the resist onto graphene after the removal of resist.
On the other hand, the typical lift-off patterning process is depicted in figure 5(b). Firstly, a resist layer is first casted on a bare substrate, and then patterned via EBL or photolithography. Subsequently, a polymer-supported graphene is transferred onto the substrate with patterned resist. Afterwards, graphene on the photoresist can be lifted off by solvent immersion together with ultrasonication, while graphene that fully in contact with substrate remains. This method has been broadly utilized for defining metal electrodes in microelectronic fabrication, which requires the material to form strong adhesion with both of resist and substrate. Therefore, pre-transfer treatment such as plasma cleaning of the substrate, or post-transfer treatment such as the heating treatment, are beneficial to the successful implementation of lift-off method.

Direct-writing.
Laser is known as 'the fastest knife, the most accurate ruler and the brightest light'. Laser writing represents a powerful patterning technique with high reliability, executability, and scalability, which has been broadly utilized to carve 2D and 3D geometric pattern in bulk materials, as well as pattern the 2D materials [60]. Laser writing can directly achieve the goals of controllable thinning and patterning of graphene in one step without the use of masks and chemical reagents [37]. A schematic illustration of direct laser writing is demonstrated in figure 5(c). Laser can be applied at the selective position on the graphene through continuous or pulsed irradiation, where the graphene under the irradiation can be thinned and completely removed due to the laser-induced photothermal accumulation or other complex light-matter interactions [89]. The high energy process may cause local oxidation of graphene to form graphene oxide component [90]. Theoretically, the patterning resolution is dominated by the spot size of the laser beam. However, the localized heat may diffuse to the surrounding area, thus expand ablation boundaries and reduce the resolution of patterning. To tackle this problem, femtosecond laser writing has been developed, in which the ultrashort pulse duration and extremely high peak intensity can minimize the possible heat diffusion and improve the patterning accuracy [91].

Fabrication of graphene-based heterostructure
Construction of graphene-based heterostructures is extremely important for the fabrication of graphene devices, especially optoelectronic devices. In general, two primary strategies have been proposed for heterostructure preparation, namely, transfer-assisted methods and direct-growth methods. The transfer of graphene onto other materials or transfer 2D materials onto graphene can refer to the discussion in section 2.3. For transferring 0D and 1D nanomaterials onto graphene, the facile solution process is usually adopted, such as spincoating, drop-casting, inkjet manufacturing, and spray coating, but the as-prepared nanomaterial layer usually exhibits relatively poor uniformity. Besides, the transfer of nanomaterials with preformed ordered structure (e.g. array, superlattice) can improve the quality of the transfer [92,93]. On the contrary, the transfer-free methods avoid the complex and costly transfer process, meanwhile, eliminate the possible damage and contamination for better interface. For instance, the direct CVD growth of graphene to form heterostructure has been demonstrated on, for example, Ge [51], SiO 2 [94], ZrO 2 [95], SrTiO 3 [96], hBN [97,98]. Moreover, various materials, such as bulk semiconductor (e.g. GaAs, GaN), oxide thin films (SrTiO 3 ), 2D materials (hBN) and nanowires (e.g., ZnO, InAs), can be epitaxially grown on graphene [23,99]. The direct growth also can be employed in solution process for constructing heterostructures (e.g. perovskite/graphene) [100]. These direct growth methods enables scale-up manufacturing of graphene-based heterostructures. However, the unknown influence of the growth process on graphene and graphene interface needs further study.

Graphene-based synaptic devices
In biological neural networks, the information that one neuron (presynaptic neuron) can pass to the next (postsynaptic neuron) is permitted by neurotransmitter flux that regulate the signal intensity inside synaptic cleft, where the modulation of connection strength or amplitude between these two neurons (i.e. synaptic weight) enables synaptic plasticity to achieve various functionalities such as memory, learning and processing [101,102]. Mimicking the information processing in human brain forms the basis for the development of neuromorphic applications with low energy consumption and high functionality. The key to configurate an artificial neuromorphic system is to develop synaptic components with regulatable weight. To emulate synaptic plasticity, artificial synaptic devices can perform regulation of specific physical parameters under external stimuli, where the conductance (or resistance) is the common parameter with high accessibility and compatibility with integrated circuit technology. Thus, after applying presynaptic spikes, the synaptic devices will yield a variation of postsynaptic current (PSC), including inhibitory (IPSC) or excitatory (EPSC), which can further mimic the synaptic plasticity such as short-term plasticity (STP), long-term plasticity (LTP), spike-rate-dependent plasticity (SRDP), spike-timing-dependent plasticity (STDP), and STP to LTP transition [103]. Owing to unique electronic/optical properties and atomic thickness feature, graphene presents a broad platform for developing synaptic devices with various structures. The graphene-based synaptic devices response to the light stimulation due to unique light-matter interaction, which can emulate various light-induced synaptic plasticity. In this section, we will briefly introduce the device structure of graphene-based synaptic devices, two main photoresponse mechanisms (i.e. photogating and photo-desorption effect), and the emulation of synaptic plasticity by optical spikes.

Device structures
3.1.1. Two-terminal memristors. The memristor with typical metal-insulator-metal configuration has drawn great research interests since its small cell size facilitate the high-density 3D stacking integration. Till now, diverse materials and underlying switching mechanism for memristors have been extensively studied. In general, resistive switching in memristors usually involves electrochemical redox reaction along with the ion migration, which can lead to the formation and breaking of conductive filament or regulation of the interfacial barrier ( figure 6(a)) [104]. Based on the type of migrating species, memristor can be categorized as cation type, anion type and dual ionic type devices. A cation type device usually possesses an active metal electrode (Ag, Cu, etc) that can general mobile cations to construct metallic filament under electric field [15,[105][106][107], while an anion type device involves the generation/migration of anion vacancies (oxygen, halogen, etc) and subsequent formation of conductive vacancy filament in the insulating layer [108][109][110]. In some cases, both cation and anion migration can be observed, which synergistically facilitate the forming and rupture of filament during the resistive switching. Based on the holding time of the conductive filament, resistive switching behaviors are classified as nonvolatile memory switching and volatile threshold switching. Volatile threshold devices lose low resistive state immediately after external electrical field removal and return to high resistive state. On the contrary, nonvolatile memory devices hold the conductive filaments and maintain the low resistive state for relatively long time. Thus, systematic analysis and engineering of conductive filament plays a decisive role in the performance optimization of memristor.
Graphene features excellent impermeability and high electronic conductivity, which have been used as active layer, electrode or functional layer in the memristive devices. As shown in figure 6(b), Standley et al [111] reported a nonvolatile memory device based on graphene with a nanogap, in which the nanogap was generated via electrical breakdown. The resistive switching behavior could be attributed to the formation and rupture of atomic-level carbon chains across the nanogap under a voltage sweep. The rigid carbon chains endow the devices with high endurability and long state retention. Moreover, a series of carbon atomic chains could lead to a tunable conductance in the devices, which has been confirmed by the step-like conductance I/V curve. Besides, such nanogap-graphene can be used as nanoelectrodes for memristor devices [112].
The location and geometry of the conductive filament in memristor highly relies on the contact at the electrode/insulator interface. A sharp point contact between electrode and insulator can usually guide the formation of rigid narrow filament, benefiting for stability, uniformity, and power efficiency. Lee et al demonstrated a resistive memory composed of Graphene/HfO x /TiN, where graphene formed an edge contact with HfO x layer with contact width of 0.3 nm [113]. As shown in figure 6(c), compared with the 5 nm-width Pt electrode, edge-contacted 0.3 nm-width graphene electrode provides a great platform for efficient ion storage/transmission, thus results in lower power consumption. Moreover, graphene could retain high conductivity when the thickness close to the physical-limit (single-atom thickness), which is a predominant electrode candidate for ultrahigh-density 3D stacking integration.
Additionally, the perfect graphene features excellent impermeability, which can be utilized as an interface layer to block ionic transport. On the other hand, the defective graphene enables selective permeability, which can centralize or decentralize the ion migration in the memristive device [114][115][116]. As shown in figure 6(d), Ta 2 O 5 -based memristors exhibited a tunable resistive switching behavior with an inserting layer of porous graphene, where a series of controlled pore sizes could be defined by patterning techniques. The porous graphene with small pore size can significantly reduce the conductance in both low resistance state and high resistance state of the device, since the small pore size can centralize the oxygen migration and induce slim oxygen vacancy filament formation. In another work, defective graphene has been applied to regulate the Ag cation transfer in the memristor as shown in figure 6(e). The atomic discrete defects in graphene can further restrict the ion migration and modulate the quantity and diameter of the conductive filaments, thus, lead to highly stable resistive switching, even under high working compliance current.

Synaptic transistors.
Cross-bar architecture enables facile integration of two-terminal memristor into high-density arrays, however, a coupled component (for example, selector) for each cell is usually necessary to avoid the leakage current and cross-talk during large-scale operation. Moreover, two-terminal memristor is unable to process writing and reading simultaneously, thus, having difficulty to replicate natural synaptic behavior. Fortunately, a transistor-based synaptic device can provide an effective solution, where the channel acts as a weight storage unit and the gate electrode plays the role of an induction protocol unit to tune the weight through spiking. In addition, synaptic transistor possesses advantages during the operation in terms of stability and controllability. More importantly, the exposed channel can response to the external stimulus such as light, heat, force, exhibiting fascinating potential in multimodal synaptic emulation [12,117]. Notably, atomically thin graphene features susceptible charge carrier transfer ability according to the external environment, which offer enormous opportunities for developing high-performance sensory synaptic transistors. Generally, the synaptic transistors can be categorized as charge trapping, floating gate, and electrolyte gate with doping or redox mechanisms.

Charge trapping synaptic transistors.
Charge trapping and detrapping can take place at the defect region in graphene and its adjacent materials or interfaces, as well as extraneous adsorbed molecules on graphene [118]. As shown in figure 7(a), Schranghamer et al [119] proposed a graphene-based synaptic transistor with amorphous Al 2 O 3 dielectric. The amorphous oxide dielectric possesses a large number of surface dangling-bonds, which can provide effective charge trapping sites. Thus, the device exhibits multi-level (>16) nonvolatile conductance states through gate voltage tuning ( figure 7(b)). Moreover, the conductance states can be configurable through applied drain voltage pulses of different magnitudes, indicating a capability for multiterminal (gate and drain) operation. However, charge trapping is usually introduced by random defects or environmental changes, which has great uncontrollability, thus affecting the robustness and durability of devices.

Floating-gate synaptic transistors.
Floating-gate transistor involves a charge trapping layer (floating gate) that embedded in the dielectric layer close to the channel, where tunneling-assisted charges interchange between floating gate and channel can achieve the regulation of channel conductance [120]. However, floating-gate memory devices usually require large operation voltage pulses, which lead to high energy consumption and limit their applications in neuromorphic computing. Optimizing the configuration of floating-gate transistor can significantly improve the memory performance. Jang et al [121] fabricated a transparent flexible nano-floating gate transistor memory device, in which graphene is employed as active channel with gold nanoparticle (Au NP) charge trap elements (figure 7(c)). The optimization of Au NP size and tunneling dielectric thickness can provide an enhanced programmable memory performance, endowing the device with a large memory window, fast switching time, robustness and stability (figure 7(d)). In 2021, Frydendahl and his colleagues demonstrated that graphene-based floating-gate synaptic transistor can be implemented with CMOS memory [122]. In addition, owing to the stable electron affinity, high charge storage capacity, and high density of states, graphene, especially multilayer graphene, is also an excellent material for trapping charges, which can be adopted as floating-gate in synaptic transistors, especially in 2D synaptic devices. Liu et al [123] displayed an ultra-fast flash memory based on MoS 2 /hBN/graphene heterostructure, where multilayer graphene served as floating gate (figure 6(e)). vdWs contact in MoS 2 /hBN/graphene heterostructure provides an atomic-level flat interface for efficient Fowler-Nordheim tunneling through hBN dielectric, which lead to an excellent memory performance with ultrafast operation speed (∼20 ns) and large on/off ratio (∼10 6 ) (figure 6(f)). Such a short operation time facilitates the construction of neuromorphic devices with high-speed computing capabilities.

Electrolyte-gated synaptic transistors.
As the synaptic weight in biological synapse is dominated by the ionic calcium dynamics, the electrolyte-gated synaptic transistors present an advantageous platform for biomimicry synaptic devices [124]. The ions migration in the electrolyte can modulate the channel conductance to realize synaptic weight updating via doping or redox reaction [125,126]. For conventional electrolyte-gated synaptic transistor with oxide channel, the ions (e.g. proton, lithium) can diffuse into amorphous oxide channel to form a permanent doping, leading to a unreversible and asymmetrical response to the external stimuli. Graphene provides a possible solution for improving reversibility and symmetry of synaptic weight updating owing to its high ionic impermeability. Moreover, the highly biocompatible graphene can be directly integrated with biological tissue to perform biocompatible neuromorphic computing. Recently, Kireev et al [127] fabricated a graphene-based artificial synaptic electrolyte-gated transistors with Nafion film as electrolyte-gate ( figure 7(g)). Nafion can serve as a store of proton/water clusters, in which proton-concentrated clusters can slightly move away or close to the graphene channel under the current pulse. The migration of protons can regulate the capacitance of electrical double layer, thus, modulate the conductivity of graphene channel ( figure 7(h)). As shown in figure 7(i), the channel conductance demonstrates a symmetrical, reversible, and scalable response to the gate pulses stimuli, highlighting the advantage of covalent crystalline characteristic. Moreover, the water content in Nafion is predominant to the kinetics of the proton movement, which can tune the synaptic plasticity in terms of retention time and power consumption (down to 50 aJ µm 2 ). Similarly, graphenebased transistor with ferroelectric dielectric can also be adopted to develop artificial synapse [128]. The composite of ion liquid/salt and polymer can also act as efficient electrolyte gate to perform emulation of synaptic functions [129,130]. Moreover, in the case of electrolyte-gated transistor with sidegate configuration, the diffusion of ions into interlayer gaps of multilayer-graphene has been proposed to modulate the electrical conductance [131].
Compared with 2D morphology, graphene tends to present in 1D form (GNRs) or 0D form (graphene QDs) for future high density integration systems. The nanoribbon with the size of tens of lattice length is promising for high-density integration and low power consumption. However, to the best of our knowledge, GNR-based synaptic device has not been experimentally demonstrated, but theoretically proposed to build nonlinear leaky integrate-and-fire spiking neuron [132]. Graphene QDs can be applied as charge trapping layer in synaptic devices [133,134]. For example, Xu et al [134] reported an electronic synapse with Al 2 O 3 /graphene QDs/Al 2 O 3 structure. The atomically thin graphene QDs with lateral size of ∼15 nm that confined between ultrathin Al 2 O 3 films play the role of electron traps, modulating the Fowler-Nordheim tunneling-dominated electron transport in the device. This ultrathin electronic synapse exhibits a low power consumption of <0.16 nJ/spike with high yield of >95% and performance reproducibility.
Inspired by highly interconnected neural networks in biobrain, the development of synaptic device integration towards 2D or even 3D neuromorphic system is inevitable [135]. The dissimilarity of synaptic device structures leads to the difference in terms of integration and functionality. In general, the two-terminal memristors possess simpler analog structure of biological synapse than synaptic transistors, which enable massive integration of synapses through cross-bar array that benefit for an efficient architecture and operation. For synaptic transistors, the multiple spatiotemporal signals can be input through source or gate electrodes to enable highcomplexity information processing. Thus, synaptic transistors can be expanded to multi-gated synaptic transistors to mimic complex synaptic behaviors, especially dynamic synapses, of which plasticity can be regulated within dynamic range and thus adapted for learning. Tian et al [136] proposed an artificial dynamic synapse based on dual-gated twisted bilayer graphene synaptic transistor. Owing to the ambipolar characteristic of graphene transistor, the carrier type in graphene  [123], with permission from Springer Nature. (g) Schematic of graphene synaptic device based on electrolyte-gate (Nafion). (h) Schematic of operation mechanism in electrolyte-gate graphene synaptic device, where the proton in Nafion can migrate under gate voltage stimuli. (i) Reversible conductance variation depending on the periodical gate stimuli. Reproduced from [127], with permission from Springer Nature. channel (n-channel or p-channel) can be switched by applying appropriate bottom gate voltage. The p-channel graphene synaptic transistor can be defined as inhibitory synapse, since the interfacial charge trapping/detrapping after applying positive voltage pulse from top gate can induce p-doping to graphene channel, leading to reduction in conductance of p-channel graphene transistor. On the contrary, n-channel graphene synaptic transistor behaves as excitatory synapse. Therefore, dynamic reconfiguration of synaptic plasticity could be achieved in a single multi-gate ambipolar synaptic device through a constant gate modulation. Instead of applying constant gate voltage, Chen et al [128] demonstrated reconfigured synapse based on an ambipolar graphene-ferroelectric synaptic transistor using the polarization switching of ferroelectric gate dielectric. In addition to ambipolar transistor, Bu et al [8] successfully realized dynamic reconfigurable artificial synapse based on a single-polarity synaptic transistor through the coupling of ferroelectric polarization switching in ferroelectric poly(vinylidene fluoride-trifluoroethylenechlorofluoroethylene) dielectric and charge trapping in poly (N-vinylcarbazole) dielectric.
In addition, the unique structure of synaptic transistors facilitates the introduction of external stimuli, which can act as presynaptic source or neuromodulator to regulate the synaptic weight, so-called stimulus-sensory synaptic transistors. Incorporating sensing functions (e.g. five basic human senses: touch, sight, hearing, smell and taste) into synaptic devices is a requisite for fashioning artificial perceptual intelligent systems [137,138]. For example, Chen et al integrated a piezoelectric nanogenerator (PENG) with an electrolyte-gated graphene synaptic transistor to construct an artificial tactile synapse. Importantly, approximate 80% of external information is obtained through visual perception systems in human body. The optoelectronic synaptic devices enable the combination of light-sensing functions and sensing signal processing, which can emulate visual perception function of the retina and other intelligent systems. Therefore, we will discuss the graphene based optoelectronic synaptic devices in the following section.

Photogating effect and photo-induced adsorption/desorption effect
The unique light-matter interactions endow graphene with diverse optoelectronic properties, including photovoltaic effect, photo-thermoelectric effect, photogating effect, bolometric effect, and others [139,140]. At present, the vast majority of semiconductor synaptic optoelectronic devices can achieve the emulation of excitatory postsynaptic behaviors through optical spike stimulation and inhibitory postsynaptic behaviors through electric spike stimulation, however, the emulation of light-induced synaptic inhibitory is rare [102,141]. Fortunately, rational utilization of photogating effect and photo-induced adsorption/desorption effect can address this issue.
Photogating effect refers to the light-induced modulation of carrier density and thus the conductance of graphene. There are two main cases. On one hand, electron-hole carrier pairs can be generated in graphene with light illumination. The electrons, for example, could be partially trapped at defective sites of graphene or nearby materials while the holes as counterpart could regulate the channel conductance to mimic synaptic plasticity [142]. On the other hand, electron-hole pairs are generated in materials (molecules, QDs, nanowire, 2D materials, or bulk materials) or traps near graphene ( figure 8(a)). Then, with the guidance of band alignment between graphene and nearby materials, one type of carrier would be driven into graphene by the internal electric field while the other type of carrier remains in the nearby materials or traps ( figure 8(b)). The trapped charges can modulate the carrier transport behavior in graphene channel due to the gate effect ( figure 8(c)). Graphene possesses low charge generation efficiency because of the zero-bandgap feature. Therefore, integrating nanomaterials with graphene to form heterostructures can open up a new paradigm for optoelectronic applications [23]. The inherent inert surface of graphene facilitates the vdWs interaction with other dimensional materials, whereas the vdWs gap could generate extra barrier for carrier transfer. Growing nanomaterials from graphene lattice could eliminate the vdWs gap for improving photoresponsivity and thus enable high performance photonic synapse for recognition tasks [100]. In addition, incorporation of more than one materials with graphene could endow the synaptic device with synergistic advantages to achieve multi-functionalities. For instance, pyrenyl graphdiyne (Pyr-GDY) features an absorption peak at 450 nm while PbS QDs (∼4.1 nm) exhibit strong absorption at 980 nm. Owing to unique band alignment in Pyr-GDY/graphene/PbS QDs heterostructure, Pyr-GDY reduces the conductivity of graphene under 450 nm illumination while PbS QDs enhances the channel conductance with the illumination of 980 nm due to their opposite photogating effects to graphene [143].
Photo-induced adsorption/desorption: oxygen and moisture usually induce p-type doping in graphene at ambient condition, where the Fermi level of graphene shifts blow the Dirac point of graphene ( figure 8(d)). With the illumination of UV light, the oxygen molecules that adsorbed on the graphene surface will be released in the way of O 2− (ads) → e − + O 2 (gas), which regulate the Fermi level to close to Dirac point and thus cause a reduction of p-type conductivity in graphene (figures 8(e) and (f)). Accordingly, Yang et al [144] reported an optoelectronic device based on Bi 2 O 2 Se/graphene hybrid structures, where the red light illuminated on Bi 2 O 2 Se can govern the positive photoresponse to mimic synaptic excitatory and UV light interacted with graphene dominate the negative photoresponse to trigger inhibitory postsynaptic behaviors. Besides, incorporation of nanomaterials with graphene has been demonstrated to regulate the light-induced oxygen adsorption and desorption, which also enables all-optically controlled synaptic devices [145].

Synaptic plasticity
Compared with conventional electrical spikes, utilizing optical spikes as presynaptic stimuli can overcome several limitations in terms of bandwidth, speed, crosstalk and robustness. Such synaptic devices are known as optoelectronic or photonic synapses, which can emulate various synaptic plasticity by light spike stimulation. Figure 9(a) illustrates the schematic diagram of synapse in biological neural network and electrical circuit of artificial optoelectronic synapse. In graphenebased optoelectronic synaptic devices, the unique light-matter interaction of graphene and their heterostructures offer a great platform for conductance modulation and subsequent synaptic plasticity emulation. For example, Hou et al [143] fabricated a optoelectronic synapse based on Pyr-GDY/graphene/PbS QDs heterostructure to perform optical spike operation. In this graphene-based synaptic device, an optical spike of 980 nm can trigger EPSC while 450 nm optical stimuli can induce IPSC due to the selective hole doping and electron doping of p-channel graphene by synergetic effect of predesigned photosensitizers (Pyr-GDY and PbS QDs) ( figure 9(b)). Paired pulse facilitation (PPF) is a typical form of STP on the hundreds of milliseconds scale to realize the functionalities of recognition and temporary information processing. As shown in figure 9(c), when the device is stimulated by two successive pulses with a certain time interval of ∆t, the ∆PSC evoked by second pulse (A2) may change from that evoked by the first pulse (A1), where the ratio of A2/A1 is defined as pairedpulse ratio (PPR). PPF refers to that PPR > 1 in synaptic behavior, while paired pulse depression (PPD) is defined as PPR < 1. Therefore, the device exhibits PPF behavior for both of EPSC and IPSC owing to the accumulation of the trapped charges in heterostructures. Moreover, the PPF index, defined as A2/A1 × 100%, demonstrates a gradual decrease along with increasing time intervals (∆t) ( figure 9(d)). Thus, the numbers and intervals of 980 nm/450 nm spikes can modulate the charge trapping in the heterostructure channel, and subsequently regulate the EPSC/IPSC of the device, which are also known as spike-number-dependent plasticity (SNDP) and SRDP. Figure 9(e) demonstrates the SNDP characteristics of the device. The EPSC exhibits a rapid change at the beginning and successive saturation trend when the spikes numbers gradually increase from 1 to 200, which can be regarded as an emulation of learning in biological brain [146]. IPSC demonstrates gradual decay as the increase of spikes number in a similar trend, which can represent a biological forgetting behavior [124,145]. SRDP refers to that the frequency of excitation and inhibition spikes can significantly modulate the synaptic plasticity, which indicates that cognitive ability can be improved by high-repetition training [147]. As shown in figure 9(f), the EPSCs and IPSCs show a larger change for both excitation and inhibition with the stimulation of higher spike frequency. LTP, including long-term potentiation/depression (LTP/LTD), is vital for memory and learning. As shown in figure 9(g), the conductance of the device can be gradually and reversely tuned by excitation and inhibition spike trains, which indicates an excellent LTP/LTD performance. The ideal LTP/LTD curve usually require multi-level conductance states, high linearity/symmetry, stability/cyclic repeatability, which facilitate the processing of frequencybased signals and improve the recognition accuracy in further neuromorphic applications. Moreover, the maximum conductance (G max ) and minimum conductance (G min ) define the conductance range, which can determine the energy consumption and mapping contrast of the devices [148]. Besides, STDP indicates that relative timing of spikes can dominate the synaptic strength. The symmetric STDP relates to associative learning while the asymmetric STDP associate with sequence learning [149,150]. Moreover, the transition from short-term memory to long-term memory is usually simulated by regulation of the light spike with long pulse duration, large pulse number, or high pulse intensity [151].

Optoelectronic synaptic applications
Beyond the electrical signals, optical stimuli offer a unique contact-free way to emulate biological synaptic functions in optoelectronic synaptic devices, facilitating the progress of multifunctional and high intelligent neuromorphic systems [152,153]. Owing to the unique optoelectronic properties and atomically thin structure, graphene can provide a unique platform for designing synaptic devices for optoelectronic applications, especially, in neuromorphic computing [154]. In addition to the high stability at room temperature and wafer-scale manufacturing capability, graphene features high ambipolar field effect mobility, which facilitates high-speed electrical signal communication and tunable functionality for neuromorphic computing. The high optical damage threshold makes it reliable in the application of photonics and optoelectronics. Moreover, graphene has atomical level thickness and unique electronic structure, of which properties are susceptible to external light stimulus, indicating strong light-induced modulation in graphene-based optoelectronic synaptic device. Furthermore, graphene is highly compatible with various materials to form graphene-based heterostructures, which endow graphene with unprecedented and designable optoelectronic properties to cope with diverse requirements in optoelectronic neuromorphic applications. Table 1 categorizes the recent graphene-based optoelectronic synaptic devices with the terms of device structure, materials, light parameters, synaptic functions and applications.
In this section, we review the recent advances of optoelectronic neuromorphic applications in graphene-based synaptic devices, including logic operation, neuromorphic visual system, and associative learning.

Logic computing
Human brain can effectively execute complex computing task in synergetic mode of parallel and sequential way through neural networks. Thus, as the foundation of the computation, logic functions is predominant in artificial synaptic emulation, which can significantly improve the date processing ability for neuromorphic computing. In electronic circuits, logical operations involve the gain of multiple input signals and subsequent yield of an output signal according to a given logical relationship. Recently, logic operation in optoelectronic synaptic devices have attracted enormous attention, since the optical input features robustness, broad bandwidth, high transmission speed and low crosstalk, which can break the limitation of metal wiring in terms of high-density integration and Joule heats. Several simple logic functions, such as OR, AND, NOR, and NAND, have been demonstrated in graphene-based optoelectronic synaptic devices.
Yang et al [144] have realized logic operations with alloptical inputs by an optoelectronic devices with serially connected Bi 2 O 2 Se/Graphene channel (figure 10(a)). As shown in figure 10(b), positive photoconductivity is dominated by the carrier injection of photoconductive and bolometric effects in Bi 2 O 2 Se under 635 nm illumination. On the contrary, negative photoconductivity in graphene under 365 nm light can be attributed to the photo-induced gas desorption (mostly oxygen) from the graphene surface, where the removal of oxygen molecules can lead to a reduced p-type doping in graphene and thus decrease in p-type channel conductivity ( figure 10(c)). Thus, Bi 2 O 2 Se/graphene hybrid structure based optoelectronic devices exhibited two photoresponse modes, positive photoconductivity at 635 nm and negative photoconductivity at 365 nm with appropriate illumination power. By applying appropriate light pulse stimuli, the optoelectronic device can exhibit excitatory and inhibitory post synaptic current, which can further perform PPF and PPD ( figure 10(d)). As shown in figure 10(e), to perform the logic 'OR', the optical spikes (525 and 635 nm) are assigned as inputs, where the light on and off represents the logic '1' and '0', respectively. Meanwhile, the output logic '1' and '0' is determined by the output current, in which the current exceed the threshold value of 2 µA is defined as '1'. After the dynamic optical input with the configurations of '00', '01', '10' and '11', the device shows an output  [160] current of 1.4, 2.2, 2.2, and 2.4 µA, correspondingly, indicating a successful demonstration of logic 'OR'. Additionally, the realization of logic 'AND' needs the assistance of extra modulation input of illumination at 365 nm, since the illumination at 365 nm can suppress the overall current and tune the current off-set to match with the logic output definition (threshold current of 2 µA). Except for hybrid series channels, bidirectional photoresponse can be also achieved by the optoelectronic device with the channel composed of pyrenyl graphdiyne/graphene/PbS QD heterostructure [143]. For optoelectronic synaptic devices, utilization of unique light-matter interaction endows the devices with bidirectional photoresponse, highlighting substantial promise for the neuromorphic computing.

Neuromorphic visual system
The human visual system mainly consists of biological retina and human brain. Retina enables the conversion of optical information into neural actions for vision generation, and human brain can further process the visual signals to realize memory and recognition tasks in a complex environment. Inspired by human visual system, an artificial visual system usually involves a combination of image sensor, memory and processing unit for executing complicated image-processing task. However, such a discrete configuration leads to significant requirements of storage space and energy consumption. Fortunately, optoelectronic synaptic devices enable the integration of optical sensing, signal memory and processing functions, which can open a way for highly efficient artificial visual system. Owing to the unique optoelectronic properties of graphene and graphene-based heterostructure, graphene exhibits outstanding potential in constructing optoelectronic synaptic devices for neuromorphic visual system [100]. Figure 11(a) demonstrates a typical working process of biological visual system, which involves visible information receiving and conversion into neural actions in retina, and signal memory and processing in human brain. To emulate the basic sensing-memory-processing functions, Hou et al [143] fabricated a 7 × 6 pixels optical synaptic device array based on graphdiyne/graphene/PbS heterostructure. To perform visual perception, 150 successive optical training pulses have been applied to the cells in the letter image 'G' area of the array ( figure 11(b)). The corresponding synaptic device cells demonstrate LTP after training, where image 'G' is captured by the optical synapse array and retained for over 1000 s, indicating the realization of real-time image perception and simultaneously memorization. In addition, to investigate the image distinction of the optical synapse array, the letter image 'O' as a reference is input to the array, which generates a nonvolatile conductance update in corresponding array cells. The overall conductance states will be submitted to a pre-defined function. Later, a unknown image 'S' input can induce nonvolatile conductance in the area out of image 'O' and change the result of the function, implying a failure of matching between the reference and the unknown image ( figure 11(c)). Moreover, modulation of photogenerated carriers' separation and transfer can strengthen the visual memory. Han et al [151] demonstrated a real-time visual sensing and memory behavior on 2 × 2 pixels synaptic array based on graphene/hBN/CsPbBr 3 QDs. The thin hBN layer acts as a barrier to modulate the photogenerated carrier transfer between graphene and CsPbBr 3 QDs, which can significantly improve the PPF index to strengthen visual memory due to the rate-limiting effect.
Besides the simple image distinction, the biological visual system can efficiently and correctly catch important information in complex environment, owing to advanced working mechanism and information processing abilities. Visual attention mechanism allows brain focusing on important information and ignoring unimportant information, facilitating the efficient multi-target recognition. Chen et al [157] designed an floating-gate transistor with ReS 2 /hBN/graphene heterojunction, where ReS 2 , hBN, and graphene was employed as semiconductor channel, dielectric, and charge trapping layer, respectively. The device can achieve light-tunable synaptic plasticity under optical stimuli and electrical synaptic plasticity by applying gate voltage. Thus, the visual attention can be regulated by an interference signal from gate voltage stimulus. With slight interference of gate spike (amplitude of 0.1 V), the device exhibits a stable visual information with PSC of ∼12 nA, indicating attention stabilization ( figure 12(a)). As the amplitude of the interference spikes increases to 0.2 V, the PSC shows a considerable vibration but approximately return to ∼12 nA, representing attention fluctuation. To simulate attention distraction, an intense gate spikes with large amplitude of 10 V is applied to the synaptic device, leading to a considerable decay of PSC ( figure 12(b)). After receiving the visual signal with salient-based attention again, as shown in figure 12(c), the stored visual information can be reinforced by successive stimulation of optical spikes (0.11 nW µm −2 ). Figure 12(d) illustrates the normalized conductance mapping of synaptic array that store visual information of '2' under various attention state. Using the mapping as input for recognition simulation, the recognition probabilities under attention stabilization, fluctuation, distraction, and salient-based attention are 98.23%, 98.19%, 1%, and 99.12% respectively. The results indicate that distraction of attention can reduce the capability of visual information storage, leading to a significant decrease in recognition ability. However, salient-based attention behavior can reinforce visual information to enhance the recognition probability. To verify the visual attention mechanism, a single layer perceptron artificial neural network (ANN) has been introduced to construct a neuromorphic visual system for multi-target recognition. The neuromorphic visual system can identify the targets of '8', '2' and '6' in turn by modulating the attention among these three objects, where the most salient target can be recognized first (figures 12(e) and (f)). Therefore, optoelectronic synaptic devices with floating gate configuration exhibit great potential to conduct overloaded visual information efficiently in the artificial visual system.
Multimodal interaction/coupling with visual system can significantly improve the perception and recognition in human brain, which is of great interest for neuromorphic visual systems. Recently, Yu et al [160] proposed an optoelectronic transistor coupled with a triboelectric nanogenerator (TENG) to emulate mechano-photonic artificial synapse. The synaptic plasticity is dominated by the charge carriers (electrons and holes) transfer/exchange in graphene/MoS 2 heterostructure under optical stimuli. The displacement of TENG can regulate the gate electric field and thus tune the conductance and plasticity of the mechano-optoelectronic transistor. Such a synergistic effect of light pulses and mechanical displacement can significantly improve the image recognition accuracy. The maximum recognition accuracy based on ANNs algorithm enhances from 37% to 54% when the displacement of TENG (representing mechanical stimuli) increases from 0.5 to 1.5 mm. Moreover, the recognition accuracy can be significantly improved from 54% to 92% by increasing training samples. Thus, multimodal artificial synapse is advantageous to strengthen neuromorphic visual system and facilitate the development of interactive AI. In addition, graphene can be employed to fabricate TENG, indicating the potential for all-graphene-based on self-powered artificial synaptic devices [161].

Associative learning
Associative learning is used to describe the learning process that occurs when two or more stimuli-induced central excitations in the human brain are connected. It indicates that a link between conditioned stimuli and unconditioned stimuli will be developed by repeated pairings of stimuli. Pavlov's dog experiment is a common illustration of a classical conditioning reflex. Typically, bells and food feeding are chosen as the unconditioned and conditioned stimuli for salivation, respectively. Salivation is first triggered merely by feeding, namely unconditioned response. After repeated training, the bell alone could cause a conditioned response to salivation if the bell and feeding are associated. Thus, conditioned responses can be developed through associative learning.
The classical Pavlov conditioning has been demonstrated by graphene-based electrolyte-gate transistor with light modulation [142]. The LTP of the synaptic device can be regulated by a blue light stimulus owing to the effective trapping of photo-generated electrons in graphene ( figure 13(a)). To perform Pavlov conditioning, the gate voltage pulses (5 Hz) with the amplitude of −3 V and −0.5 are, respectively, defined as unconditioned stimulus (food) and neutral stimulus (bell ring), while a threshold current of 0.42 mA is used to determine the salivation response. As shown in figure 13(b), EPSC is lower than the threshold after applying 'bell ring', indicating a response of no salivation. On the contrary, when the device is stimulated by 'food', the EPSC exceeds the threshold, indicating an unconditioned salivation response. Subsequently, trained with 'food' and 'bell ring', the device exhibits the EPSCs over the threshold, causing a training salivation response. After training, the 'bell ring' alone can lead the response current close to the threshold but decay over time, indicating unstable conditioned learning that easy to be forgotten. On the contrary, when the light stimulus is applied to the device, the EPSCs exceed the threshold, producing a stable unconditioned salivation response ( figure 13(c)). This indicates that the light stimulus can induce an enhanced associative learning ability to the device, which is consistent with the principle of optogenetics.

Conclusions and outlook
In summary, we have reviewed the fabrication technologies of graphene, and discussed the roles of graphene in various synaptic devices, as well as their optoelectronic application in neuromorphic system. The recent advances highlight the unique advantages of graphene-based synaptic devices in optoelectronic application.
1) Graphene has excellent environmental stability and capability for wafer-scale synthesis, which are the important guarantee for the future large-scale integration of graphenebased synaptic devices. 2) Graphene features high ambipolar field effect mobility. The extremely high mobility facilitates the high-speed information communication in neuromorphic computing. The ambipolar characteristic endows graphene with multifunctionality, which can be adopted for mimicking dynamic reconfiguration in bio-synapse.
3) Using graphene to construct designable structures can realize diverse functions. The abundant nanomaterials with various optical and electrical properties can be integrated with graphene to form vdW heterostructures. Rational design of such heterostructures offers a great platform for optoelectronic application in neuromorphic systems.
Despite the advances, graphene-based synaptic devices are still facing some challenges. Future research on graphenebased synaptic devices could be further recommended from following aspects. 1) Graphene synaptic devices with diversified functions often need the help of graphene-based heterostructure, necessitating the development of industrial-scale graphene and its heterostructures. Currently, graphene-based heterostructures are mostly prepared through transfer approaches. However, challenges still remain in intact material transfer with minimized damage and interfacial contamination. In this regard, direct epitaxial growth methods could be favorable for high-quality heterostructures on hard substrates, which can avoid the risk of damage and contamination during the transfer process. Moreover, the inert surface and excellent mechanical properties of graphene endows graphene-based heterostructures with great potential in flexible device applications. Scale-up for devices fabrication on flexible substrates also have to be addressed in future works. Low-temperature compatible processing technologies (e.g. spin-coating, inkjet manufacturing, lowtemperature CVD) could potentially enable simple lab-onchips of graphene synaptic device. 2) Utilizing mature process technology, fabrication of a graphene-based synaptic device seems to be simple, but deep understanding of chemical/physical interaction at the atomic scale are rather limited. Graphene features atomical level thickness and unique electronic structure with Dirac point, of which properties are susceptible to the self-defects and environmental factors. Various forms of graphene (e.g. graphene oxide, GNR, and graphene-based heterostructure) exhibits distinguished electrical/optical properties, which change chemical/physical interaction on graphene and thus affect the performance of graphene-based synaptic devices. For example, the energy band alignment, exciton separation/transport, and decay time at the interface are decisive for graphene-based optoelectronic synaptic devices in terms of range, linearity and symmetry of synaptic weight update, as well as cycling endurance and energy consumption. Therefore, a comprehensive understanding of interfacial physical/ chemical mechanisms can guide the rational interfacial design for graphene-based synaptic devices. 3) Graphene synaptic devices exhibit great potential in the application of optoelectronic neuromorphic systems. However, these demonstrations are usually simulated by inputting the data from a single device into a neural network algorithm. A large-scale interconnection of synaptic devices into neuromorphic system is necessary. Lightinduced synaptic weight update enables multifunctionality in graphene-based optoelectronic synapse, while the realization of depressive plasticity with light needs synaptic transistor composed of complex heterostructure channel.
To simplify device structure, the development of multifunctional materials or new device architecture is critical to realize the light-induced potentiation/depression. Introducing more functional components could obtain unique neuromorphic applications. To reduce the electrical power consumption, self-powered concept have been proposed by introduction of photovoltaic component or TENG/PENG into the synaptic devices- [162]. Incorporation with biological/chemical sensing system could construct disposable smart point-of-care devices for disease diagnosis. Moreover, biocompatibility and flexibility endow graphene-based synaptic devices with great potential for biosensor systems, smart brain-machine interfaces, and artificial intelligent skin.