Comparative coherence between layered and traditional semiconductors: unique opportunities for heterogeneous integration

As Moore’s law deteriorates, the research and development of new materials system are crucial for transitioning into the post Moore era. Traditional semiconductor materials, such as silicon, have served as the cornerstone of modern technologies for over half a century. This has been due to extensive research and engineering on new techniques to continuously enrich silicon-based materials system and, subsequently, to develop better performed silicon-based devices. Meanwhile, in the emerging post Moore era, layered semiconductor materials, such as transition metal dichalcogenides (TMDs), have garnered considerable research interest due to their unique electronic and optoelectronic properties, which hold great promise for powering the new era of next generation electronics. As a result, techniques for engineering the properties of layered semiconductors have expanded the possibilities of layered semiconductor-based devices. However, there remain significant limitations in the synthesis and engineering of layered semiconductors, impeding the utilization of layered semiconductor-based devices for mass applications. As a practical alternative, heterogeneous integration between layered and traditional semiconductors provides valuable opportunities to combine the distinctive properties of layered semiconductors with well-developed traditional semiconductors materials system. Here, we provide an overview of the comparative coherence between layered and traditional semiconductors, starting with TMDs as the representation of layered semiconductors. We highlight the meaningful opportunities presented by the heterogeneous integration of layered semiconductors with traditional semiconductors, representing an optimal strategy poised to propel the emerging semiconductor research community and chip industry towards unprecedented advancements in the coming decades.


Introduction
The semiconductor industry has been developing for decades alongside the scaling of devices size and increasing density of transistors following the classical Moore's law. However, the extension of effective Moore's law has encountered contemporary manufacturing and physics challenges even with extensive innovation in devices structure, traditional semiconductor materials system, advanced process and system engineering. The most significant physical obstacles impeding the down-scaling of transistors are the short channel effects (SCEs) at several tens of nanometers channel length, and quantum tunneling at sub-10 nm channel lengths. Over the past two decades, the focus has been on developing several generations of specially designed materials systems and device structures to overcome the challenges associated with these issues. These advancements include high-κ metal gate MOSFETs, the currently commercially manufactured fin field effect transistors (FinFETs), and the state-of-art gate-all-around (GAA) MOSFETs. However, the further down-scaling of device sizes continues to be limited by the inherent 3D nature of traditional semiconductors. As device dimensions shrink to the nanometer scale, the properties of traditional semiconductors undergo dramatic changes, which may ultimately stop the further scaling of devices based on traditional semiconductor due to physical, technical and economic limitations.
Unlike traditional three-dimensional (3D) semiconductors, layered materials comprising two-dimensional (2D) atomic layers bring new opportunities. For example, graphene has attracted broad interest [1] since its introduction as the first freestanding 2D material [2]. However, the zero-bandgap nature of graphene hinders its application as a semiconductor material. Meanwhile, transition metal dichalcogenides (TMDs) with suitable bandgap and band structure have emerged as a new generation of layered semiconductor materials. Since the first demonstration of monolayer MoS 2 [3], numerous monolayer TMDs, including both semiconducting and metallic materials, have been developed, offering unlimited possibilities for TMD-based devices. Furthermore, various techniques have been developed to modulate the properties of TMDs, including phase engineering [4], defect engineering [5], and doping [6]. These advances have demonstrated the immense potential of TMD-based devices in extending Moore's law to the sub-1 nm scale [7]. Moreover, the direct bandgap nature of certain monolayer TMDs has attracted broad interest in their photoelectronic applications. Additionally, TMDs have exhibited novel properties, such as superconductivity [8], spin-orbit coupling [9], ferroelectricity [10], and ferromagnetism [11], which may initiate a new era of devices based on layered materials system with innovative principles.
Due to the 2D nature of layered materials system, lateral or vertical heterostructures based on layered materials bring even more opportunities. Heterostructures can be formed among layered materials either laterally via chemical bonds or vertically via van der Waals (vdW) interactions, enabling heterojunction devices based on layered materials [12,13]. Lateral chemical hetero-integrated junctions offer advantages such as atomically thin interline, mass production process based on chemical reactions, and unique benefits for electronic and optoelectronic devices. On the other hand, vdW heterostructures (vdWHs) can be composed of arbitrary layered materials, offering highly flexible stacking order and angles, as well as naturally atomically sharp interfaces. Many novel functional devices based on heterogeneous integration of layered materials systems have been demonstrated, such as interlayer exciton devices [14] and tunnel field effect transistors (TFETs) [15].
Despite the tremendous opportunities brought by layered semiconductors, challenges persist in the fine synthesis, device performance, industrial engineering of layered semiconductors, which hampers the widespread utilization of layered-semiconductor-based devices. In contrast, the synthesis, engineering, and patterning technologies of traditional semiconductors have progressively developed and matured over the past few decades. Due to the 2D nature of layered materials system, most processes used in 2D devices are compatible with silicon-based technologies. In addition, the extensive family of layered materials with various band structure, when combined with the well-established band structure of silicon offers a synergistic advantage through heterogeneous integration. Therefore, combining novel layered materials with well-developed traditional semiconductors is a reasonable pursuit and promising strategy for post-Moore era.
Thus, this review provides an overview of the comparative coherence between layered and traditional semiconductors, and explores the unique opportunities presented by the heterogeneous integration of layered semiconductor and traditional semiconductor for high-performance functional heterojunction devices and integrated circuits. We will first focus on TMDs as a representation of layered semiconductors, encompassing their fabrication and engineering techniques, as well as introducing the devices based on TMDs heterojunctions. Then, we will provide a comparative view between TMDs and traditional semiconductors, demonstrating the benefit of combining TMDs with traditional semiconductors. Finally, we will point out the emerging challenges and the significant potential of this integration strategy and evaluate the potential impact in post-Moore era.

Layered semiconductors and vdWHs
TMDs are a large family of layered materials exhibiting various electrical and optoelectronic properties. This variety of materials and properties enables the exploration of next-generation electronic and optoelectronic devices. Furthermore, the properties of TMDs can be modulated with various methods, including phase engineering, defect engineering, doping, and alloying. Modulation using these methods further extends the potential applications of these materials. Moreover, vdWHs can be formed by combining different types of layered materials to realize functional devices. This section summarizes the fundamental properties and engineering methods of TMDs, as well as the fabrication techniques of TMDs and TMD vdWHs, and introduces TMDs-based electronic and optoelectronic devices. Besides, elemental layered materials, such as black phosphorus (BP) exhibit increasing potential as high-quality electronic materials. The modulation methods, along with the fabrication techniques for both single materials and heterostructures, and potential device applications will be highlighted. TMDs are a family of materials sharing a standard chemical structure of 'MX 2 ', where 'M' represents a transition metal element, and 'X' represents a chalcogen element (i.e. S, Se, and Te). A wide range of TMDs has been experimentally researched [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31], as shown in figure 1(a).

Phase structure and phase engineering.
The basic structure of TMDs is a stack of monolayers where a metal atomic layer is sandwiched between two chalcogen atomic layers. The most common monolayer structures of TMDs can be categorized into three types: trigonal 2H, trigonal 1T, and orthorhombic 1T ′ . In the subsequent discussion of this article, unless otherwise specified, the word 'phase' is used to refer to the crystal structure type of TMDs mentioned above, i.e. 2H/1T/1T ′ , etc. Different stacking patterns of monolayers form various multilayer phase structures, as illustrated in figure 1(b). TMDs with distinct chemical compositions possess different thermodynamically stable phases under room temperature. For example, among VI B TMDs (excluding WTe 2 ), the 2H phase is stable, while the 1T phase can be stabilized as a metastable phase. In contrast, for WTe 2 , the orthorhombic T d weyl semimetal (WSM) phase is stable at room temperature [32]. Different phases of TMDs exhibit different properties. For example, 2H MoS 2 performs as a semiconductor, while 1T MoS 2 shows metal-like behavior due to its zero-band-gap nature, as shown in figure 1(c) [33]. The absence of inversion symmetry in the 3R and T d phases can also bring unique properties and allow for novel functions. Ferroelectric polarization perpendicular to the atomic plane has been reported in the 3R bilayer [10], as shown in figure 1(d) or a ferroelectricity-related photovoltaic effect [34]. Moreover, band splitting is predicted in the 3R phase [35]. For the T d phase, superconductivity [8] and WSM [36] behavior have been reported.
Phase engineering of TMDs is employed to modulate their properties and create hetero-phase junctions. The 2H-1T and 2H-1T ′ semiconducting-metallic hetero-phase junctions have attracted significant attention due to the good Ohmic contact between the 2H and 1T [37] or 1T ′ [38] phases. The phase transition mechanism between 2H and 1T phases can be described by an atom-plane-gliding model. The gliding of the chalcogenide plane results in the transition of a 2H monolayer into a 1T monolayer. Alternatively, the symmetry of the 2H monolayer is reversed with the gliding of the metal plane, as shown in figure 1(e) [ [43], and so on. Liu et al found that the 1T ′ phase can be stabilized with absorbed potassium atoms, as shown in figure 1(f) [44]. A patterned 2H-1T ′ phase transition can be induced using an alkali metal treatment process [33]. Furthermore, Cho et al reported a laser-induced 2H-1T ′ phase transition in MoTe 2 [38]. These post-growth phase transitions can be patterned to create a lateral hetero-phase junction. Figure 1(g) illustrates the fabrication of a transistor with a 2H channel and 1T contact using a patterned n-BuLi treatment, leading to good Ohmic contact behavior [37]. Using a similar technique, the fabrication of MoS 2 transistors with sub-10 nm 2H and 1T ′ channel lengths is possible, as depicted in figure 1(h) and (i) [33].
Over the past decade, tens of representative layered semiconductor with diverse phase properties have been extensively investigated, providing a wide range of alternatives for highquality layered semiconductor with stable phase and suitable band structure. Besides, non-semiconductor phases of layered semiconductor can be utilized as contacts, dielectrics, and interlayers to build high performance devices, thereby enhancing the technological advantages compared to single-phase silicon materials.

Defects and defect engineering.
Multiple defects are existing in intrinsic or doped layered TMDs, which can profoundly influence their properties. Figure 2(a) illustrates various point defects presented in TMDs, including vacancies and vacancy clusters, anti-sites, split interstitials, adatoms, interlayer interstitials, and substitutional atoms [45]. Additionally, line defects, including grain boundaries or edges, can also be observed in monolayer TMDs. Figure 2(b) exemplifies a one-dimensional grain boundary in monolayer MoS 2 composed of an array of dislocations [46]. Furthermore, nanophases have been observed in TMDs. As an example, figure 2(c) shows vacancy-related ferromagnetic 1T nanophases in 2H MoS 2 [11].
Through defect engineering, modulation of the properties of TMDs is possible. For example, chalcogen vacancies can provide n-type doping effect in certain TMDs. Defects also provide chemically active sites on the surface of TMDs, facilitating chemical sensing and catalysis. The focus of defect engineering in TMDs has primarily been on vacancies due to the excellent controllability and lower forming energy, especially for chalcogen vacancies [46]. Defects can be introduced in situ by controlling synthesis conditions. For example, by adding H 2 in the carrier gas, defects with controllable concentration can be introduced without damaging the crystal structure [47], as shown in figure 2(d). Furthermore, Jeong et al reported that a non-uniform source distribution results in S-vacancy-rich and W-vacancy-rich regions, demonstrating the effect of source supply on defect formation [48]. It is also reported that multiple defects, including vacancies, antisites, and grain boundaries, can be introduced during pulsed layer deposition (PLD) [ Defects in TMD lattices are typically charged to maintain electric neutrality, resulting in a doping effect such as n-doping induced by chalcogen vacancies [57]. Figure 2(f) shows that with Ar-plasma-treated contacts, the WSe 2 transistor shows improved n-type behavior and better contact with the electrode [54]. P-type doping was also achieved through defect tailoring, which can be attributed to the charged atom clusters fixed at point defects [53]. Defects on TMD layers serve as chemically active sites capable of absorbing molecules, which, in turn, act as sites for further modulation of the TMD properties. For instance, thiol groups can be tightly bounded to sulfur vacancies (V S ) on MoS 2 . Therefore, thiol molecules containing different functional groups can be used to modify the properties of V S -containing MoS 2 , as illustrated in figure 2(g) [58]. The chemical sensitivity of defects can also be harnessed for chemical sensing [59]. Chemically active defects can act as catalytic sites, providing opportunities for hydrogen evolution reaction catalyzation [60,61] or photocatalytic applications [51].
Methods to eliminate or passivate defects are crucial when defects are undesirable. One approach involves using a highly reactive chalcogen source during growth to increase the chalcogen chemical potential, thereby preventing in situ defect formation. For instance, using chalcogen monomers instead of sublimed chalcogens has been shown to be effective [62]. Chalcogen vacancies can also be eliminated post-growth [63] or passivated [64] through chemical methods. Figure 2(h) shows an adatom mechanism of chemical vacancy elimination.
Similar as silicon-based semiconductor materials, defect engineering is essential for controlling the electrical properties of layered semiconductors. Through extensive research on defect engineering, significant progress has been made in defects modulation. However, due to the atomic-thin nature of layered semiconductors, the selection of doping elements, precise control of dosage and compatible defect modulation process is significantly different from traditional semiconductors. Consequently, the research community and industry are actively working to address these challenges in order to facilitate hetero-integration.

Layer number engineering.
Layered materials can maintain their structure when they are thinned to the nanometer scale because there are no dangling bonds on the layer surface. Meanwhile, their properties vary with their thickness or layer number due to the quantum confinement effect. The absence of dangling bonds paired with thickness control allows for another degree of freedom in controlling the properties of layered semiconductors. Many TMDs possess a thickness-dependent bandgap [65,66]. Furthermore, typical semiconducting VI B TMDs exhibit indirect-to-direct bandgap transition as the number of layers is reduced [65,67]. Figure 2(i) shows the thickness-dependent bandgap structure of MoS 2 . The bandgap widening and indirect-to-direct bandgap transition when MoS 2 is thinned to a monolayer can be clearly identified [65].
Band alignment can be modulated by controlling layer numbers to achieve desired device properties. For example, a type-I band alignment can be formed in a monolayermultilayer lateral homojunction [68]. A patterned layercontrol process is necessary to form such a structure. Some patterned etching methods for top-down thickness control have been developed, including atomic layer etching [69][70][71][72]. Monolayer-like properties can also be obtained in BP and TMDs with intercalations of organic molecules due to the interlayer decoupling, without significant altering of the electronic structure which is inevitable during alkali metal intercalations [73,74].
Precise layer-control can also be achieved with bottomup strategies, for example, uniform bilayer nucleation was achieved by epitaxial growth on a sapphire substrate with a terrace-like morphology [75].
Thickness variation also affects defects. For example, it has recently been reported that by decreasing the number of layers of PtSSe, the formation energy of chalcogen vacancies and Pt vacancies decrease and increase, respectively, which is called as a thickness-dependent doping effect [76].
Different from silicon based traditional semiconductor with strong degradation under sub-10 nm dimension, layered semiconductor has stable atomic structure and strong layerdependent band structure even down to monolayer. Even for research community, monolayer layered semiconductor is the center focus, the semiconductor industry still has interests for bilayer or few layered semiconductors, or precisely layer control capability to stabilize the properties and wafer scale uniformity, which require extra efforts for the hetero-integration of layered semiconductor and traditional semiconductor.

Strain engineering.
Similarly, as silicon-based strain engineering for mobility enhancement, variation of the lattice parameters related to strain in TMDs can also cause bandgap modulation, providing the possibility to tune the electrical properties of TMDs by applying external stress. Tensile strain can cause direct-to-indirect bandgap transition in certain monolayer TMDs or reduce the bandgap. On the other hand, compressive stress increases bandgap and reduces mobility [65,77,78], as shown in figure 2(j), where uniform uniaxial strain can be introduced by transferring TMDs onto a flexible substrate [79].
Beside strain engineering for a single layered semiconductor, interface strain at the interface of heterostructure can cause bandgap structure variation, even a change in band alignment [80]. Observation of the exciton funneling effect is possible when there is a strain gradient in TMDs due to the bandgap modulation caused by strain [78,81]. However, compared with silicon-based strain engineering, a cost effective industrial level strain engineering for greatly improved materials properties is still lacking in the layered semiconductor field.
2.1.6. Doping and alloying. Controlled doping is a crucial process in traditional semiconductor properties modulation and devices manufacturing. In principles, the electric properties of layered semiconductors, including the bandgap structure and density of states, accordingly conductivity and carrier density can be tuned via doping. Figure 3(a) summarizes the widely used doping strategies in TMDs. Intrinsic doping is achieved through defect tailoring or substitutional doping. On the other hand, external doping can be performed through electrostatic doping and surface absorption.
As introduced in section 2.1.3, defects in TMDs can act as the source of the doping effect [53,54] or be modulated to allow more flexibility in achieving alternate doping effects [58]. Substitution atoms in TMDs can also be considered a kind of defect. Plentiful reports of both metal substitution  [94]. Copyright (2021) American Chemical Society. (f) PL spectra evolution in WS 2x Se 2−2x alloy with the variation of composition. The arrow refers to the composition variation from WSe 2 to WS 2 . (g) Doping effect transition in WS 2x Se 2−2x alloy with the variation of composition. The arrow refers to the composition variation from WSe 2 to WS 2 . Reprinted with permission from [95]. Copyright (2016) American Chemical Society. (h) Continuous bandgap variation until 0 bandgap in WxNb 1−x Se 2 alloy with the composition variation. Reproduced from [96], with permission from Springer Nature. (i) Mechanism nonvolatile floating-gate like light-assisted electrostatic doping, where n-type doping is illustrated as an example, while the p-type doping can be elucidated in a similar manner. From [99]. Reprinted with permission from AAAS. (j) Patterned surface charge transfer doping with a self-aligned oxide layer on WSe 2 channel. (k) Transfer curve before and after doping with a self-aligned oxide layer on WSe 2 channel. Reprinted with permission from [105]. Copyright (2021) American Chemical Society. (l) Schematic illustration of hybridization of phase engineering and surface charge transfer doping in a 2H-MoSe 2 transistor. Reprinted with permission from [107]. Copyright (2021) American Chemical Society.
(V [82,83], Nb [84][85][86], Mn [87], Re [83,88], Fe [89], etc) and chalcogen substitution (halogen and V A elements [90], C [91]) are available for consideration. Compared with cases in bulk materials, a high doping concentration is required in layered semiconductors due to the weak response of the dopant states to dopant concentration because of quantum confinement [6]. Achieving degenerate p-type doping is possible with a sufficiently high concentration of Nb substitution in MoS 2 which is naturally n-doped, as shown in figure 3(b) [84].
As substitution atoms are embedded in the lattice of TMDs, as shown in figure 3(c) [83], substitutional doping becomes chemically stable. However, most reported substitutional doping methods are achieved in situ during growth, which restricts the feasibility of patterned doping. Nevertheless, several patterned post-growth substitutional doping methods have been reported. For example, phosphorus substitution can be achieved with low-energy ion implantation in V S -containing MoS 2 [92]. Recently, a cation exchange method was developed to realize Sn doping in multiple TMDs [93].
With increasing substitution concentration, the substitution elements can take up a considerable proportion of the composition and thus form an alloy. Alloy formation allows continuous property control between two TMDs with a common lattice structure. Continuous band structure modulation can be achieved with either metal alloying [94], as shown in figures 3(d) and (e), or chalcogen alloying [95], as shown in figures 3(f) and (g). Alloys between semiconducting TMDs and metallic TMDs, for example, WS 2 and NbS 2 , allow continuous bandgap modulation toward a zero-bandgap state, as shown in figure 3(h) [96].
Doping can be externally achieved with an electric field; i.e. electrostatic doping. The simplest type of electrostatic doping is accomplished by applying a constant gate voltage [97]. However, such doping methods are volatile. Meanwhile, some non-volatile electrostatic doping methods have been developed. For example, methods that involve floating gates [98,99] or ferroelectric dielectrics [100]. Heterostructure formed by bandgap renormalization due to the electrostatic screening of different dielectrics have also been reported [101]. Figure 3(i) shows the mechanism of a light-assisted floating-gate-like non-volatile electrostatic doping method [99]. Electrostatic doping allows dynamic control of doping concentration at the cost of extra energy consumption and increased complexity in the device structure.
Surface charge transfer is another external doping method. For ultrathin layered semiconductors like TMDs, the surface charge transfer effect caused by the work function difference at interfaces can provide a sufficient doping effect. Such an effect is achieved through absorption or deposition of gaseous molecules [102], alkali metal [103], oxide dopants [104,105], or organic dopants [106,107]. Figures 3(j) and (k) shows a device with a self-aligned grown oxide dopant layer [105]. Figure 3(l) shows a transistor that introduces hybrid modulation of phase-engineered contacts and an organic surface charge transfer doped channel [107]. Surface charge transfer doping to BP was also reported [108]. Most surface charge transfer methods are easily patterned, while some suffer from chemical instability.
Even with extensive exploration for effective doping of layered semiconductors, mature doping type control, dosage control and doping activation effectiveness control strategies are still under exploration, which may require a novel process and doping strategy instead of ion implantation or thermal diffusion for silicon based traditional semiconductor.

Modulation of interlayer coupling.
For vdWHs, in addition to factors such as stacking mode and crystal phase, external field control of interlayer coupling provides a new degree of freedom for properties regulation. The variation of interlayer coupling can be effectively induced by fine adjustment of the component layer or interlayer electrostatic potential through an external electric field [109]. For example, by adjusting the bias voltage between the two layers, the interlayer coupling of the single layer WSe 2 /graphene heterojunction is significantly enhanced [110]. The stress field perpendicular to the heterojunction can also be adjusted to modulate the interlayer spacing and thus its interlayer coupling characteristics, with the advantage of continuously and reversibly modulation [111].

In-plane anisotropy.
Anisotropic layered materials have unique properties that vary depending on the direction due to broken symmetry, providing more flexibility in device designing. Layered epitaxial bismuthene exhibits anisotropic Seebeck coefficients that vary 2-5 times along different crystal directions. It also has a record-breaking absolute value of the Seebeck coefficient and high conductivity, providing potential for energy conversion applications [112]. In addition, V A group atomic layered materials (including phosphorene, arsenene, antimonene and bismuthene) have also attracted increasing attention. These materials have tunable mid-range bandgap and controllable stability, and are considered competitive candidates for next-generation high-speed and energy-efficient logic devices [113]. ReS 2 is a representative of anisotropic 2D sulfides, with strong in-plane anisotropy in electrical, optical, thermal properties, and the mechanical anisotropy [114]. Moreover, the elucidation of Raman modes and pressure response in ReS 2 and the progress in rapid analysis techniques for crystal orientation will also promote the design of emerging anisotropic nanodevices [115][116][117].

Synthesis methods of TMDs
Typical TMDs can be fabricated through either a top-down approach, such as exfoliation, or a bottom-up approach, such as chemical vapor deposition (CVD) or chemical vapor transport (CVT). On the other hand, the fabrication methods of TMD heterostructures include transfer and restack, step growth, and one-pot growth methods.

Exfoliation of layered materials.
Mechanical exfoliation [2,3] is the basic method used in preparing ultrathin TMD materials from a bulk source. Liquid phase exfoliation [118,119] is more efficient than mechanical exfoliation for getting few-layer or monolayer TMDs from a bulk source. Application of exfoliation methods to most types of layered materials maintains the properties of the pristine material and avoids the potential defects that may occur during transfer process of chemical synthesized layered materials. However, exfoliation methods are limited by their low efficiency, which may be improved by introducing automatic systems [120], and poor compatibility with the conventional semiconductor manufacturing processes due to the uncontrollable shapes of exfoliated flakes. As a result, exfoliation methods are basically only applicable for demonstration research in laboratories instead of industrial applications.

CVD growth.
Compared with top-down exfoliation methods, bottom-up synthesis methods are capable of patterning and are compatible with conventional semiconductor manufacturing processes. Thermal CVD is the most basic and common method for TMD growth and can be controlled Reprinted with permission from [123]. Copyright (2015) American Chemical Society. (b) Morphology of some typical CVD TMDs grown with NaCl or KI promoters. Reproduced from [16], with permission from Springer Nature. (c) CVD method with spin-coated liquid-phase precursor. Reproduced from [96], with permission from Springer Nature. (d) Schematic diagram of MoS 2 MOCVD setup. Reproduced from [126], with permission from Springer Nature. (e) MoS 2 vdW epitaxy on sapphire with matched lattice parameters. Reproduced from [128], with permission from Springer Nature. (f) Lateral epitaxial WS 2 /WSe 2 heterostructure. Reproduced from [138], with permission from Springer Nature. (g) Water-assisted transfer method which allows precise control of twist-angle. Reproduced from [145], with permission from Springer Nature. (h) Two-step CVD to form MoS 2 /WSe 2 or WSe 2 /MoSe 2 epitaxial vdWH on graphene. Reproduced from [146], with permission from Springer Nature. (i) Reactivity-controlled one-pot-grown NbS 2 -MoS 2 vdWH. The scale bars are 10 µm. Reprinted with permission from [148]. Copyright (2018) American Chemical Society. (j) MoS 2 -WS 2 vertical heterostructure formed using a PECVD method. Reprinted with permission from [150]. Copyright (2021) American Chemical Society.
in multiple ways. The most basic chalcogen sources used in CVD are sublimed solids. For cases where higher reactivity is desired, adopting chalcogen hydrides (such as H 2 S and H 2 Se) and monomers released from a metal chalcogenide source in low-temperature conditions [62] are demonstrated alternatives. Another control factor is the use of different carrier gases in specific reactions. Hydrogen gas (H 2 ) added to the carrier gas makes the reaction atmosphere more favorable towards reduction [121] and is useful in controlling defects [47]. Contrarily, O 2 in the carrier gas suppresses nucleation [122]. By varying the temperature and gas flow rates, the thickness of the layered TMD material can be reduced to the required specifications (figure 4(a)) [123]. Thickness control is achieved by lowering the temperature and increasing the flow rate; however, it promotes the formation of supersaturated precursors leading to a higher nucleation density on the substrate surface. Higher temperature also enhances the nucleation of grown WSe 2 , forming a multilayered structure. The most commonly used transition metal sources are transition metal oxides (TMOs). TMOs' moderate melting points and relative high feasibility in achieving thermal evaporation in the CVD process are useful properties leading to in situ pre-deposition growth. In cases where further lowering of TMOs' melting points is desirable, salts like NaCl or KI have been adopted as promoters [16] and aid in the formation of multiple types of monolayer TMDs such as MoS 2 , MoSe 2 , WS 2 , WSe 2 , NbS 2 , and NbSe 2 ( figure 4(b)). In addition to lowering the melting point by adding salt promoters, low-melting point precursors directly applied during the synthesis stage (such as the use of SnSe 2 growth with a SnI 2 source [124]) result in uniform and stable growth conditions. Compared with sublimed solid precursors, solution phase precursors, such as (NH 4 ) 2 MoO 4 , are used to synthesize large and uniform monolayers of MoSe 2 [125]. Such solution phase method can also be used to form large uniform monolayer Nb 1−x W x Se 2 alloy, as shown in figure 4(c) [96].
Compared with conventional thermal CVD, metal-organic CVD (MOCVD) results in a higher-quality final product under better-controlled growth conditions. However, this is often achieved with the use of highly toxic metal-organic reactants (e.g., metal carbonyls). Despite the drawback of using MOCVD, the highly desirable wafer-scale production of evenly doped MoS 2 and WS 2 [82,83,126] can be realized using this process (figure 4(d)) and, thus, it is important to discuss in this context.
Beyond controlling reaction itself, multiple materials have been developed as CVD substrates for TMDs directional or high reactive growth. Different from SiO 2 /Si substrates, sapphire [127,128] or mica [129] substrates are adopted where high-quality epitaxial growth is desired. For example, a Cplane sapphire wafer inherently forms a flat terrace along <10-10> on the substrate and favors the unidirectional growth of MoS 2 domains (figure 4(e)) [128]. The terrace on the substrate surface aligns the growing crystals, forming large single crystals. For example, Ma et al successfully formed epitaxial h-BN on Ni (111) terraces [130]. The epitaxial forming of h-BN on the Ni (111) terraces occurs due to the high reactivity of Ni and B, which forms Ni 23 B 6 . Graphene is also adaptive for the epitaxial growth of TMDs, acting as the growth substrate while can also be used as an electrode [131]. A recent study has shown that in the MOCVD WSe 2 synthesis process on graphene substrate, increasing the number of graphene layers would lead to better alignment between WSe 2 flakes and the graphene substrate, and the nucleation density of WSe 2 would increase. The nucleation density was also affected by surface ripples, defects, and multi-layer stacking order and twisting angle [132]. Moreover, TMD growth on metal substrates, such as Au [133], and flexible substrates, such as polyimide (PI) [134], are also being actively researched and developed. Recently, Kim et al introduced a confined-growth technique that achieved the precise control over layer-by-layer growth and wafer-scale controllability of layer numbers and crystallinity, enabling the fabrication of wafer-scale, singledomain 2D monolayer arrays and their heterostructures on a range of substrates with high precision [135].

Other TMDs synthesis methods.
Derived from CVD methods, CVT can also be used to grow high-quality bulk TMD crystals, including doped TMDs [84]. Atomic layer deposition (ALD) also provides another controllable wafer scale growth method. However, when using ALD, it is not easy to form uniform monolayers and large single crystals so far [136]. Furthermore, since as-deposited film from ALD contains many defects, a post-annealing process with a chalcogen source is required to improve film quality. PLD can be used to synthesize monolayers and bilayers of TMDs, but this process results in higher densities of defects [49]. Very recently, the improved molecular beam epitaxy (MBE) process has been used for wafer-level TMDs growth. Xia et al reported the growth of wafer-scale single-crystalline MSe 2 (M = Mo, W) monolayers by MBE at low temperatures (200 • C-400 • C) on nominally flat Au (111) substrates. The low temperature of MBE process was conducive to alignment of MSe 2 nucleation with Au surface, and brought advantages for epitaxial growth of single crystal TMD [137].

Fabrication of heterostructures composed of TMDs
The formation of heterostructures is necessary to realize many devices with various functions. Both lateral and vertical junctions can be formed between TMDs. The synthesis of WS 2 -WSe 2 and MoS 2 -MoSe 2 lateral heterostructures was demonstrated through step-growth (figure 4(f)) [138,139].
Step growth is required in the synthesis of lateral heterostructure TMDs. Conversely, vertical heterostructure TMDs can be fabricated using either step growth or mechanical stacking. Lateral heterostructures exhibit prominent advantages in optoelectronic properties, endowing extensive applications in developing photovoltaic devices. The layered structure and atomic thickness of TMDs allows for highly efficient omnidirectional light harvesting, which is vital for photovoltaic applications. In contrast, vertical heterostructures scatter and reflect light, which is undesirable in photovoltaic applications [12]. Nevertheless, vertical heterostructures attracted more attention as they can be easily fabricated by transferring and restacking layers. The lattice-match-free nature of the vdW interfaces and the flexible transfer methods allow the formation of heterostructures among arbitrary layered materials. Moreover, vertical heterostructures are well suited for devices based on the electron tunneling effect, due to their ease in forming vdW gaps with atomically sharp interfaces between the layers [140][141][142].
Vertical heterostructures between arbitrary layered materials can be formed using the transfer-and-stack method [127]. Nowadays, transfer methods can be divided into three types: solution-based transfer, non-solution-based transfer, and tearand-stack technique [143]. In these ways, researchers can achieve integration of 2D semiconductors grown on different substrates on any substrate and preserve the intrinsic properties of the material [144], even further facilitating the construction of multicomponent heterostructures. Through combination of the exfoliation, transfer, and stacking processes, a flexible process flow is created such that formation of vdW junctions among arbitrary TMDs, control of the interlayer twist angle (as shown in figure 4(g)) [145], and creation of artificial asymmetric structures (e.g. artificial 3R bilayer [10] as shown in figure 1(d)), can all be achieved.
However, such methods are complex, inefficient, and poorly compatible with traditional semiconductor manufacturing processes. Hence, adopting either a two-step growth method or an epitaxial growth method to form heterostructures between layered materials allows heterostructure formation without compromising compatibility with traditional semiconductor processes. WSe 2 -MoS 2 and MoSe 2 -WSe 2 heterostructures formed by subsequent thermal CVD or MOCVD on epitaxial graphene have been reported [146]. It is worthy to note that the first layer growth of MoS 2 is converted to MoSe 2 when WSe 2 reacts in the atmosphere and forms WO 3 and vapor phase Se, resulting in S to Se substitution in MoS 2 , as shown in figure 4(h). Compared to the two-step CVD, Li et al demonstrated a unique way to form vertical heterostructures in a selected position by creating defects on the bottom layer using a laser [22]. As a result, the second layer of TMDs favors nucleation and growth on the defect sites.
The step-growth method is more compatible with the traditional semiconductor manufacturing processes, but interlayer contamination is inevitable between growing steps. Some onepot heterostructure synthesis methods have been developed to combat the formation of interface defects, the resulting strain in the stacking process, and the effect of contaminants when exposed to air during two-step growth. It is important to note that, one-step heterostructure formation can be done by modulating the reactivity difference between different TMDs [147,148] or intentionally controlled by tuning the reaction conditions, such as the composition of carrier gases [121,149]. Fu et al realized MoS 2 /NbS 2 vertical heterostructures using a one-pot growth method shown in figure 4(i) [148]. Nucleation of NbS 2 is favored at the corners of MoS 2 layers since the higher concentration of defects there assists the nucleation process. This method is based on thermal CVD and the different growing temperatures of MoS 2 and NbS 2 . Coverage of the second-layer NbS 2 depends on the elapsed growth time and hence may be incomplete when the time of growth is not sufficiently high. Plasma-enhanced CVD (PECVD) with H 2 S plasma sulfurization done by Seok et al has shown promise in fixing this drawback. W and Mo metals are deposited on the wafer sequentially, and H 2 S plasma is used to sulfurize the predeposits to form WS 2 and MoS 2 simultaneously, as shown in figure 4(j) [150]. This method is very efficient, compatible with traditional semiconductor manufacturing processes, and avoids interlayer contamination, however, plasma brings an increased chance of introducing defects and resulting in poor crystallinity.
To further enhance TMDs' performance and expand their applications, TMDs have been integrated with other layered materials beyond TMDs, such as TMD/perovskite heterostructures, TMD/MXene heterostructures, TMD/h-BN heterostructures and so on. TMD/perovskite heterostructures have been explored for use in photovoltaic and light-emitting devices. Yang et al have shown that the enhancement of emission from 2D perovskite/WS 2 few-layer heterostructures can be up to 150-fold compared to the bare WS 2 . By using a solvent-free process, researchers successfully achieved the fabrication of TMD-on-2D organic and inorganic hybrid lead halide perovskites heterostructures [151].
TMD/MXene heterostructures have been investigated for their potential in energy storage applications. Etching methods are simple and convenient for producing MXene sheets, but the top-down synthesis strategy results in sheets with abundant defects and functional groups on the surface. These surface features can facilitate the growth of TMDs. Intercalated/delaminated MXenes have larger interlayer spacing and more sites for hybridization with TMDs, allowing for greater storage of metal ions and transportation of small molecules in hierarchical MXene/TMD heterostructures [152]. Additionally, TMD/h-BN heterostructures have been studied for their enhanced electrical and mechanical properties. Mechanical exfoliation and transfer are commonly used methods. Park et al transferred a MoS 2 flake onto an h-BN flake with a polydimethylsiloxane (PDMS)/polypropylene carbonate (PPC) stamp to fabricate a vertical heterostructure. Temperature-dependent interlayer coupling of the MoS 2 /h-BN heterostructure under non-resonant and resonant conditions was well studied, indicating enhanced electron-phonon coupling and vdW interactions in the MoS 2 /h-BN heterostructure [153].
Compared with pure TMDs synthesis, heterostructure synthesis faces more challenges including interface control, materials scale, repeatability, uniformity of structures and properties, etc. The direct integration of layered semiconductor with targeted substrate is more desirable for semiconductor industry. Thus, to some extent, the hetero-integration of traditional materials as layered semiconductor growth substrate with layered semiconductor is more promising compared with growth and/or transfer methods.

TMDs-based electronics and optoelectronics
Layered semiconductor, represented by atomically thin TMDs with clean vdW interfaces, exhibit excellent controllability and heterogeneous integration potential with other layered materials. Therefore, TMDs based devices was treated as promising candidates for a wide variety of device applications. This section discusses the structure, performance, and challenges of TMD based homo/heterostructures devices.

TMD-based transistors.
Field effect transistors (FETs) are the most basic components of today's industrialized integrated circuits. Therefore, a promising first step has been the successful fabrication of an n-type MoS 2 transistor with a 6.5 Å thick monolayer channel [154]. The MoS 2 transistor, fabricated using a 30 nm HfO 2 film as a high-κ top-gate dielectric and a mobility booster, exhibiting a mobility of over 200 cm 2 ·V −1 ·s −1 and a current on/off ratio of 10 8 at room temperature, as shown in figure 5(a) [155]. Unlike bulk materials, layered semiconductors are easily depleted and suffer less from SCEs, allowing for an even shorter gate length. Recently, a MoS 2 -based FET with a sub-1 nm physical gate length was fabricated, as shown in figure 5(b) [7]. Fabrication and modulation of vertical monolayer MoS 2 channels were achieved with a 0.34 nm graphene edge gate and a HfO 2 dielectric. The resulting FET device exhibited an on/off ratio up to 1.02 × 10 5  [156]. Copyright (2021) American Chemical Society. (d) Van der Waals Schottky junction compared to common metal/TMD Schottky junction. Less damage is done to the structure of semiconducting TMD in the formation of vdW Schottky junction compared with Schottky junction formed between TMDs and conventional metals, resulting in weakened Fermi-level pinning and more ideal Schottky interface. Reproduced from [158], with permission from Springer Nature. (e) Characteristic curve of BP/MoS 2 diode with inset of rectification ratio. Reprinted with permission from [159]. Copyright (2014) American Chemical Society. (f) All-2D n-MoS 2 /p + -WSe 2 TFET showing sub-60 mV·dec −1 SS. Reprinted with permission from [15]. Copyright (2020) American Chemical Society. (g) BP/ReS 2 Esaki diode with negative differential resistance (NDR). and a subthreshold swing (SS) value as low as 117 mV·dec −1 . This side-wall structure utilizes the natural thickness direction of atomic layers to scale down the gate length below 1 nm, breaking through the limitation of lateral, local, top gated 2D transistor structures. Due to their high modularity, layered semiconductor can be adapted into various novel transistor structures, for example, to be integrated with an ionic gate medium to construct a synaptic transistor. MoS 2 -based mobile ion-gated synaptic transistors on a SiO 2 layer diffused with Na + have been demonstrated, as shown in figure 5(c) [156].
The conductance of the MoS 2 channel can be effectively modulated at high temperatures, resulting in a large on/off ratio of 10 6 at 350 • C and the realization of long-term and short-term synaptic functions at 150 • C and 350 • C, respectively. Such synaptic devices with high working temperatures are suitable for various neuromorphic applications.

TMD-based Schottky devices.
TMDs with atomically clean, dangling bond-free surfaces are suitable for vdW integration in the fabrication of functional devices, such as diodes, Schottky junctions, and TFETs [157]. A near-ideal rectifier based on an all-2D Schottky junction was demonstrated by integrating metallic 1T ′ -MoTe 2 and semiconducting monolayer MoS 2 , as shown in figure 5(d) [158], where the vdW interface efficiently addresses the severe Fermi-level pinning effect which causes an increased Schottky barrier height in conventional metal Schottky junctions. The rectifier exhibits a near-unity ideality factor of ∼1.6, a rectifying ratio of more than 5 × 10 5 , and the external quantum efficiency (EQE) of over 20%, which is attributed to the enlarged Schottky barrier width, leading to the feasibility of building high-performance layered-material-based Schottky diodes.

TMD-based p-n junction devices.
VdW p-n junctions, consisting of p-type BP and n-type monolayer MoS 2, are reported to show a photodetection responsivity up to 418 mA·W −1 and an EQE of 0.3%, as shown in figure 5(e) [159]. The small band gap and high mobility of few-layer BP are adequately utilized in this gate-tunable p-n diode structure. The dangling-bond-free vdW interface in a vdWH is absent of interface defect states which may cause considerable leak current. However, the vdW gap can also act as a natural tunnel barrier. Therefore, TMD-vdWHs become ideal candidates for interface-quality-sensitive tunneling devices such as TFETs, tunnel diodes and resonant tunneling diodes (RTDs), among which TFETs are capable for achieving a lower SS than the Boltzmann limit of conventional FETs (60 mV·dec −1 ) [15]. Heterointerfaces qualities, such as band alignment and the ability to form heterointerfaces, have proven to be critical factors in producing n-MoS 2 channel heterostructure TFETs. Nb-doped p + -MoS 2 crystals with a sufficiently high doping level (instead of p + -WSe 2 ) can form a more stable type-III band alignment as an alternative source, making it possible for extremely low SS, as shown in figure 5(f). Furthermore, it was found that all-2D heterostructure TFETs with an h-BN top-gate insulator have a defect-free, clean interface compared to TFETs with deposited Al 2 O 3 top-gate insulators, making band-to-band tunneling (BTBT) dominant currents feasible at room temperature. Tunnel diodes [160,161] and RTDs [146], which can show a negative differential resistance (NDR) behavior, have also been demonstrated in TMD-vdWHs. An NDR device based on a BP/ReS 2 heterojunction with a type-III broken-gap band alignment has been reported for realizing multi-valued logic applications, as shown in figures 5(g) and (h) [161]. Compared with type-II heterojunctions, highly doped type-III heterojunctions are easier to be implemented and verified in a ternary inverter.

TMD-based optoelectronic devices.
Photodiodes based on TMD heterostructures are another research focus. Diodes with atomically-thin geometry and atomically-sharp interfaces are constructed by stacking p-type WSe 2 and n-type few-layer MoS 2 , as shown in figures 5(i) and (j) [162]. Without the lateral confinement in the planar structures, the entire WSe 2 /MoS 2 overlapping area forms the p-n junction, which shows excellent current rectification behavior, rapid photoresponse, and a peak EQE of up to 12%. Furthermore, the photoelectric and electroluminescence performances exhibit dependence on the thickness of semiconductors, revealing the critical role of the direct band gap in monolayer TMDs. For vdW photoelectric devices, the speed of photoinduced charge transfer has a decisive effect on the photoelectric conversion efficiency. An et al have demonstrated through calculations and experiments that strong band hybridization in WS 2 /W x Mo 1−x S 2 heterostructures can lead to extremely fast charge transfer rates [163].
Furthermore, p-n-junction-based photovoltaic devices constructed using a vdW homojunction exhibit a higher opencircuit voltage (V OC ). This difference is attributed to the more favorable band alignment compared with that in a heterostructure [164]. For example, a p-MoS 2 :Nb/n-MoS 2 :Fe vdW homojunction is fabricated by vertically stacking substitutionally doped MoS 2 , as shown in figures 5(k) and (l). A V OC of 1.02 V is measured under broadband illumination with 4 W·cm −2 when the photoactive Schottky diodes at the TMD-metal contacts are sheltered, indicating the importance of favorable band alignment and Ohmic metal-semiconductor contacts. Furthermore, p-n homojunctions can be formed using laser-induced p-doping in 2H-MoTe 2 [53]. In addition, surface recombination issues resulting in low V OC and limited power conversion efficiency (PCE) in TMD photovoltaics were addressed. MoO 3 deposited on the surface of layered TMD semiconductors was reported as an effective passivation layer, leading to multilayer WS 2 Schottky-junction solar cells with a V OC of 681 mV under AM 1.5G illumination, and PCE of over 20% [104]. Moreover, flexible WSe 2 solar cells with a record PCE of 5.1% and a specific power of 4.4 W·g −1 were demonstrated by combining MoO x capping and graphene contacts to mitigate Fermi-level pinning and improved the method to transfer to PI substrates [165].
Recently, a spontaneous-polarization-induced photovoltaic effect was reported in ferroelectric 3R stacked MoS 2 bilayer [34] with the same structure as shown in figure 1(d). In contrast to photovoltaic mechanisms based on shift current and injection current, bilayer 3R-MoS 2 with spontaneous polarization will generate a depolarization field at the surface, which drives the photocarriers to form photo-currents. Assembled with graphene electrodes, the MoS 2 enables a large depolarization field, leading to an EQE up to 16% at room temperature, and thus provides a promising candidate for energy-efficient photodetection applications.  [166]. The superconductivity of 2D materials, such as the much-publicized magic-angle graphene [167], has aroused great interest in the field of physics. Shen et al demonstrated in their research on 4Hb-TaS 2 that the quasi 2D superconductivity in the 1H layer coexists with the Kondo resonance in the 1T layer, and the intensity of the Kondo resonance peak can be modulated by adjusting its relative position to the Fermi level [168].
In addition to optical, electrical, and magnetic functional devices, using the atomic thickness of 2D materials to achieve atomic scale micro mechanical structures and nano electromechanical systems has become an important interest of researchers [169]. Among these devices, nano resonators have received the most research. Zhu et al demonstrated a nano resonator based on WSe 2 and achieved a wide frequency tuning range of up to 230% and a high tuning efficiency of 23% V −1 . Further, by studying devices with different thicknesses and diameters, researchers have revealed the frequency scaling law in WSe 2 . This provides guidance for the subsequent development of WSe 2 resonators and high performance micro mechanical devices [170].

Fabrication methods and device applications of elemental layered materials and their heterostructures
The concept of elemental layered material refers to layered materials composed of single elements, in which atoms are connected by strong covalent bonds. At present, studies have shown that B, C, Si, P, Ge, As, Sn, Sb and Bi can form elemental layered materials [171]. Considering the strong chemical inertness and environmental stability of graphene are significantly different from other elemental layered materials, this chapter mainly introduces other elemental layered materials represented by phosphorene, i.e. monolayer BP.

Fabrication methods of elemental layered materials and
their heterostructures. Similar to TMDs, elemental layered materials are synthesized primarily through mechanical exfoliation and physical or chemical synthesis. The chemical inertness of bulk BP has enabled successful exfoliation and application of phosphorene [172]. Similar to graphene, phosphorene was first obtained from BP using the scotch tape exfoliation method [172]. Subsequently, liquid exfoliation method were employed to layer BP and prepare phosphorene. Through ultrasonic processing in amide solvent like N-cyclohexyl-2pyrrolidone, researchers successfully obtained phosphorene [173]. However, the mechanical exfoliation methods have faced challenges in achieving large-scale production of singlelayer phosphorene suitable for industrial applications.
With the increase of researchers' interest in phosphorene, breakthroughs have been made for its synthesis. Researchers have successfully synthesized few-layers BP via CVD method on silicon substrates [174]. A similar CVD process has been demonstrated to synthesize BP film with thickness of about 40 nm on flexible substrates [175]. By controlling the oxygenfree synthesis environment, the wet-chemical synthesis of phosphorene has shown potential for mass production. For example, Zhao et al synthesized bilayer phosphorene crystals by hydrothermal method, which adopted red phosphorus as precursor and adding ammonium fluoride to reduce activation energy [176]. Other synthesis methods such as MBE [177] and PLD [178] have also been employed to grow phosphorene crystals.
As for heterostructure fabrication, the transfer-and-stack method is a commonly used approach for to preparing vertical heterostructures. Since phosphorene is prone to oxidation and degradation in ambient air [179], other layered materials are often employed as passivation layers to encapsulate phosphorene. Graphene [180] and h-BN [181] are typical components of such encapsulating heterostructures. Vertical heterostructures offer opportunities to enhance the photoelectric properties of phosphorene. The calculation results demonstrate that the 2D crosslinked h-BN/graphene/BP heterostructure exhibits enhanced charge redistribution at the BP interface, forming distinct electron-hole puddles and improved photovoltaic performance [182]. Vertical heterostructures can also be fabricated by electrochemical intercalation. Wang et al report an electrochemical molecular intercalation approach to intercalate organic ions into BP for synthesizing monolayer phosphorene molecular superlattice [73]. The molecular layers effectively isolates the phosphorene monolayers, resulting in superior environmental stability and excellent mobility.

Elemental layered material electronics and optoelec-
tronics. Based on layer-number modulation, BP can achieve a large adjustable bandgap range from 0.3 eV (bulk) to 2 eV (monolayer) [183], maintaining its direct bandgap nature and high room temperature carrier mobility (∼1000 cm 2 ·V −1 ·s −1 ) [184], which creates a huge potential for optoelectronic applications. By preparing the Bi 2 O 2 Se/BP heterojunction, a photodetector with broadband detectivity for wavelength of 700-1550 nm and fast response speed (∼9 ms) was demonstrated [185]. In terms of photovoltaic devices, by constructing graphene-BP heterostructure, in which graphene acts as a packaging layer as well as a highly efficient charge transport layer, Liu et al achieved the photoresponsivity up to 3.3 × 10 3 A W −1 [180].
In addition to optoelectronic devices, BP also has broad application prospects in electronic devices and flexible devices. In an early research, p-type phosphorene and n-type MoS 2 were used to fabricate an inverter and achieved a maximum gain of 1.4 [172]. By encapsulating BP on PI substrate, Zhou et al realized the preparation of flexible BP FET and showed a maximum carrier mobility of 310 cm 2 ·V −1 ·s −1 . The researchers further prepared a variety of flexible devices for basic digital and analog circuit applications, including an AM demodulator which can provide the possibility for the realization of flexible radio receiver [186].
Overall, layered-semiconductor-based devices show excellent electronic and optoelectronic characteristics by fine tuning the materials properties and device structure. However, most devices studies are limited to academic research labs instead of industrial research center. Compared with traditional semiconductor-based devices, overall device performance optimization still needs massive research endeavors. An alternating strategy by partial replacement of traditional semiconductor with layered semiconductor or heterogeneous integration of traditional semiconductor with layered semiconductor may be more feasible to show the unique advantage of layered semiconductor materials system.

Heterogeneous integration of layered semiconductors and traditional semiconductors
Layered semiconductors represented by TMDs show great potential in future electronic and optoelectronic devices. However, despite their extraordinary properties and novel applications, their adoption has been hindered due to the challenges faced in layered semiconductors' fine synthesis and devices engineering. For example, degenerate doping in layered semiconductors is still challenging, and it is also hard to form complex 3D structures with layered materials. As a result, the utilization of devices comprised entirely of layered semiconductors is largely impeded. In contrast, several generations of traditional semiconductors have developed to maturity. The heterogeneous integration between layered and traditional semiconductors, combing the technical and economic advantage of both materials system provides a practical middle route for the first stage of post Mooreera. Table 1 presents the basic properties of traditional semiconductors along with some well-studied layered semiconductors. Based on the comparison between traditional and layered semiconductors, it is clear that layered semiconductor did show some basic specifications advantage, especially the relative high mobility at sub-1 nm dimension. However, the partial materials properties advantage did not guarantee the success of layered semiconductor in industrial application as tons of challenges of layered semiconductor, such as full device performance supremacy in certain application, industrial synthesis and process, high computing to energy ratio. However, current intensive study proposes that heterogeneous integration of layered semiconductor with traditional semiconductor may show some unique irreplaceable advantages.

Mature development of traditional semiconductors.
First-generation semiconductors, dominated by Si and Ge, were the first to be made into transistors in 1940s, replacing the bulky vacuum tube. The switch to solid-state electronics promoted the development of the modern integrated circuit [258]. In the 1970s, second-generation semiconductors became popular due to the demand for materials with higher frequency and speed. III-V compound semiconductors such as GaAs and InP became staples in microwave devices, communication devices, and navigation systems, contributing to the rapid growth of modern mobile communication, satellite communication, and optical communication fields [259,260]. Thirdgeneration semiconductors, represented by SiC and GaN, exhibit wide band gap, high critical breakdown field strength, and high saturated electron drift velocity, endowing them with unique advantages, such as high-voltage resistance, radiation resistance, and high thermal stability. The properties of thirdgeneration semiconductor materials have been successfully exploited in fields such as smart grid, railway transportation, and electric vehicles [261,262].
Compared to layered semiconductors, the development of traditional semiconductors allowed for mature materials synthesis and control, devices design and manufacturing process integration technology. Firstly, it is easier to control the doping process for traditional semiconductors, carrying out doping with a relatively high concentration or with a concentration gradient. For example, solar cells based on the GaAs created with heavy doping exhibit high-quality tunnel junctions, which play a vital role in the efficiency of the solar cell [263]. Secondly, epitaxy technology for bulk semiconductors makes it possible to prepare extremely pure and defect-less epitaxy layer. For example, with the introduction of the lateral epitaxy technique, the dislocation density of GaN falls to 10 6 levels [264]. In addition, ascribed to the mature processing technology, complicated structures can be fabricated on traditional semiconductors, including complex micro-electro-mechanical system (MEMS) structures which have been prepared at the micro and sub-micro scales. In terms of the integrated circuit, advanced nanostructures have drawn significant interest. For example, InGaAs-GAA MOSFETs remain unaffected by the SCEs [265]. A GaN-based SOI FinFET enhances electrical performance and is prepared to improve CMOS circuit performance [266]. At this time, the development of GAA devices has achieved an advanced stage and are commercially available.

Limitations of tradition semiconductors.
With the size shrinking to nanometer-scale, the properties of traditional semiconductors undergo dramatic degradation, even suffering from structure instability. As structure sizes decrease to the nanometer scale, the energy levels of an electron near the Fermi level switch from a continuous energy level to discrete levels. This switch results in a difference in the physical and chemical properties between the nanometer-scale and bulk material. As a result, resonance and optical gap widening can be observed in the Si particles. This gap widening is ascribed to the 3D quantum confinement effects on the photogenerated carriers [267]. Moreover, it is worth mentioning that the conduction band minimum depends on the crystal size of Ge nanocrystals [268]. The quantum confinement effect gives unique properties to nanomaterials. However, nano-electronic and nano-photoelectronic devices based on traditional semiconductors face two key challenges: (a) the degradation of properties of traditional semiconductors, particularly mobilities, and (b) a no longer negligible surface and interface effect originating from the 3D nature of traditional semiconductors. In contrast, layered semiconductors maintain their semiconducting properties even if thinned to atomic thickness due to the absence of dangling bonds on their surface.

Advantage of layered-tradition semiconductor heterogeneous integration.
By integrating layered semiconductors with traditional semiconductors, the novel properties of layered semiconductors and the well-developed engineering of traditional semiconductors can be jointly exploited.
High-quality vdWHs can be formed not only among layered semiconductors but also between layered and traditional semiconductors. This quality is due to the absence of dangling bonds in layered semiconductors. For example, scanning tunneling spectroscopy research of graphene/SiC interface demonstrates the lack of Fermi-level pinning, indicating the formation of a high-quality Schottky vdW interface [269]. This kind of vdW interface allows for the fabrication of devices sensitive to interface properties, for example, tunneling devices [270,271].
Layered-traditional semiconductor vdWHs can be formed using the transfer methods discussed in section 2.2. In addition, direct synthesis methods using traditional semiconductors as substrates provide more flexibility. In contrast, the growth of layered materials onto layered materials continues to face significant challenges. Interestingly, epitaxial growth can be realized between lattice-matched layered semiconductors and traditional semiconductors, such as MoS 2 on GaN [272,273]. The main benefit of direct synthesis is that contamination and interface defects generated during transfer are avoided. Direct growth of layered semiconductors on traditional semiconductors also simplifies the process flow and has the added benefit of being compatible with traditional semiconductor manufacturing and device fabrication technologies.
The mature development of traditional semiconductors allows for flexibility in designing the electronic structures of devices and enables the fabrication of complicated integrated circuits. For example, recent research has exposed opportunities in optoelectronics where layered semiconductors with traditional semiconductors take advantage of the microstructures formed to improve light absorption [274,275]. Furthermore, reports on the direct growth of MoS 2 grown on micrometerscale Si waveguides [276], nanometer-scale FinFETs, and gate all around field effect transistors (GAAFETs) channels [277] make for exciting opportunities.

Physical method fabrication of layered semiconductors on traditional semiconductors.
Transfer and stacking is one of the most common physical methods used to fabricate layered-traditional heterostructures [278]. However, such method suffers from many drawbacks such as low-throughput, contamination during transfer, and poor compatibility with conventional semiconductor manufacturing technology. Meanwhile, more efficient heterojunction fabrication methods, such as solution-based methods, are growing in popularity. For example, two-layer and few-layer WS 2 from bulk WS 2 was synthesized by using a solution-based method to fabricate p-WS 2 /n-Si heterojunctions using a dip-coating technique. These heterojunctions exhibited excellent rectification behavior of up to 1 MHz with relatively low values of ideality factor [279]. Drop casting can also be used to fabricate more complex heterostructures when combined with other methods. For example, reduced graphene oxide (r-GO) nanosheets were drop-casted onto the MOCVD-grown GaN wafers for rGO/GaN devices [280]. The Ag nanoparticles were spread onto the liquid-phase exfoliated WS 2 nanosheets using microwave-assisted solvothermal synthesis. The resulting Ag-WS 2 nanocomposite was then drop-cast onto a Si-substrate to fabricate an Ag-WS 2 /Si heterojunction-based photodiode [281]. Sputtering is another common method used to synthesize heterostructures. Wang et al deposited vertically standing MoS 2 film onto p-Si-substrate with a predefined SiO 2 window via magnetron sputtering. A 50 nm Ag electrode was used as the top contact on MoS 2, and a 50 nm Au electrode served as the back contact to p-Si, as shown in figure 6(a). A cross-sectional transmission electron microscopy (TEM) investigation shows the MoS 2 film deposited by sputtering has a uniform thickness of approximately 150 nm [282].

Physical-chemical growth of layered semiconductors
on traditional semiconductors. Modified from purely physical method, physical-chemical methods, such as postchalcogenation, are also widely used to synthesize heterostructures. Due to its ability to create high-quality products and ease of implementation in large-scale production environments, post-chalcogenation has been used with Si to grow hybrid heterostructures. Using thermally assisted conversion of in situ pre-deposited PtSe 2 layers on Si substrates, the in situ construction of large-scale homogeneous multilayered PtSe 2 /Si vertical hybrid heterojunctions was realized as shown in figure 6(b) [283]. Additionally, post-chalcogenation methods are often used after sputtering to prepare high order heterostructures. For example, researchers successfully deposited a large area of SnS 2 thin film via deposition of Sn on p-Si using DC magnetron sputtering followed by sulfurization. The result was the fabrication of an SnS 2 /p-Si device with excellent photoelectric performance [284]. Similarly, layered-traditional heterostructure-based devices like PtSe 2 /SiO 2 /Si devices [285], PdSe 2 /GaN Schottky junction devices [286], and PtSe 2 /Si Schottky devices [287] have been successfully fabricated. Liang et al reported another method controlled by preparing pyramidal Si using alkaline etching of an n-type lightly doped Si wafer to fabricate multilayer PdSe 2 /pyramid Si device as shown in figure 6(c) [274], demonstrating the possibility of fabricating layeredsemiconductor-including heterostructures with complicated structure. Besides, physical-chemical growth methods based on non-metal predepositions have also been developed. For example, a MoS 2 /Ge heterostructure based on the sulfurization of MoO 3 predeposition has been fabricated [288]. Figure 6(d) shows the process of synthesizing MoS 2 on p-Si via a (NH 4 ) 2 MoS 4 thermolysis method. Compared with the cases using SiO 2 /Si as the substrate, the hydrophobic nature of the non-oxide wafer surface makes it impossible to form an (NH 4 ) 2 MoS 4 coating directly. Thus, an evaporated MoO 3 layer is adopted as a hydrophilic layer [289]. A similar method has also been adopted to fabricate WS 2 /p-Si heterostructures [290].

CVD growth of layered semiconductors on traditional semiconductors.
Direct CVD growth of TMDs on pristine Si wafers is another technical route. For example, PTAS promoter-assisted CVD MoS 2 growth on a degenerately doped Si wafer was reported [291]. PECVD with low-temperature, high-throughput, and large-area synthesis capability, is beneficial for synthesizing competitive 2D-TMD/3D-traditional-semiconductor heterojunction devices. For example, Kim et al developed an atmosphericpressure PECVD technique to grow MoS 2 and WS 2 multilayers directly onto 4 inch Si substrates at temperatures of <200 • C, as shown in figure 6(e) [292]. Another approach is MOCVD, which is widely studied in the fabrication of layered-traditional heterostructure. For example, Zhang et al demonstrated the scalable synthesis of MoS 2 and WSe 2 via MOCVD on GaN substrate. They elucidated the structure of the layered-traditional heterostructure, as shown in figure 6(f). The AFM images show a controlled layer number of MoS 2 or WSe 2 grown on p-GaN. The number of layers ranges from a monolayer to five layers [293]. MOCVD can also achieve large-area growth of p-type V-WSe 2 , n-type MoS 2 [294], and sequential growth of wafer scale vertical SnS 2 /ReS 2 /MoS 2 vdWHs on rollable Al foils [295].

Epitaxy growth of layered semiconductors on traditional semiconductors.
Same as silicon based semiconductor, the epitaxial approach is essential when preparing high-quality lattice-match layered-traditional heterostructures. For example, Ruzmetov et al investigated MoS 2 /GaN hybrid structures on sapphire (c-plane) substrates and demonstrated vertical electrical conduction across the interface, as shown in figure 6(g) [272]. In their subsequent research, they used pre-epitaxial MoS 2 on GaN to ensure that the postdeposited Au layer was epitaxial to substrate GaN. In other words, all-epitaxial, vertical Au/1L-MoS 2 /p-GaN heterojunctions were successfully synthesized [296]. MBE is one of the most effective and widely used epitaxial methods. Lee et al reported on the synthesis and properties of wafer-scale n-SnSe 2 on n-GaN (0001) by MBE. Current-voltage measurements of SnSe 2 /GaN diodes exhibited nine orders of magnitude rectification, a significant breakthrough at that time [297]. Seredyński et al achieved MBE growth of a NiTe 2 on a nearly complete lattice-matched GaAs (111) substrate, as shown in figure 6(h) [298].

Integration of traditional semiconductors on layered semiconductors.
Layered materials which exhibit hexagonal in-plane lattice arrangements and weakly bonded layers, can easily be transferred onto flexible substrates. Hence, flexible III A -nitride devices can be implemented using 2D release layers [299]. For example, the usage of highgrowth-temperature AlN on h-BN leads to Al diffusion into h-BN, and the researchers can enhance the surface and interface dangling bonds and anchors on the layered h-BN. This process successfully controls the mechanical adhesion of h-BN layers, which benefits the large-scale fabrication of III-V devices grown on h-BN [300].
Another driving force in epitaxy development is improving atomic precision. Improved atomic precision enables the production and hetero-integration of flexible, transferrable, and stackable freestanding single-crystalline membranes. Moreover, remote epitaxy has drawn increased attention as it allows for an epitaxial approach to the fabrication of functional materials. This has the added benefit of making it possible to release grown materials from their substrates with atomic precision. Kim et al have thoroughly studied the factors that affect epitaxial quality. They revealed the respective roles and impacts of the substrate material, graphene materials, substrate-graphene interface, and epitaxial material in the electrostatic coupling of these materials, which governs cohesive ordering and can lead to single-crystal epitaxy in the overlying film, as shown in figure 6(i) [301].
Single-crystal InAs stripes are mechanically peeled and then dry transferred on top of monolayer graphene to form traditional-on-layered vdW integration. This technique for transferring traditional materials to graphene is important in enabling inorganic III-V/graphene interfaces, which are not possible using conventional growth approaches [302]. Furthermore, traditional-layered-traditional heteroepitaxy has been demonstrated with oxide remote epitaxial growth through MoS 2, realizing precisely controllable traditional-layeredtraditional heteroepitaxy for the design and development of next-generation devices [303].
As the high investment nature of current advanced chip industry, silicon-based semiconductor mostly will dominate the semiconductor industry for next one or two decade and leave rare opportunities to pure novel-semiconductor-based devices. However, novel semiconductors, especially layered semiconductors attract more and more investment from semiconductor industry as a part of progressive strategy for post Moore era. Based on past few years' research on layeredtraditional semiconductor heterostructure, it is clear that basic element to construct layered-traditional semiconductor heterostructure is mostly ready. The next focus of whole community is the net advantage of layered-traditional semiconductor heterostructure based devices compared with current most advanced silicon-based devices.

Electronic devices based on layered-traditional heterostructures
To demonstrate the devices performance of layered-traditional heterostructure, the dangling-bond-free surface of an atomically-thin layered semiconductor is used to form vdWHs devices with traditional semiconductors. These layeredtraditional heterostructures devices take advantage of the properties of both kinds of materials and could be compatible with proven fab processing techniques.

Integration of layered materials in traditional CMOS devices.
TMDs with atomically smooth surfaces and relatively high mobilities at atomic thickness are excellent channel material replacements for extreme transistor scaling and IC development. FinFET and GAAFET with MoS 2 layers for V th matching have been demonstrated by integrating the lowtemperature CVD into CMOS technology [277]. Such layeredtraditional heterostructures combining the superior electrostatic controllability of TMDs and the mature complementary doping process of traditional semiconductors are inferred as suitable for high-performance multifunctional heterostructure devices and vertical integration on conventional semiconductor architectures. More recently, an integrated process flow of transistors with monolayer WS 2 channels was demonstrated on 300 mm wafers [304]. The processing uniformity was optimized to achieve a single-device yield of more than 90%, shedding light on alternative routes to the future scaling of nodes in integrated circuits.
The layered-traditional heterostructure is applicable in fabricating Schottky devices with optimized performance. Layered Dirac semimetal graphene is reported as an efficient carrier collector in graphene/Si photodetectors [305]. The device based on Graphene/Si shows outstanding Schottky diode characteristics with a barrier height of 0.76 eV, as shown in figure 7(a). Beyond graphene, type-II layered WSMs with a unique nonlinear optical structure and topological nontrivial electronic structures, such as 1T ′ -WTe 2 , are also used for layered-traditional Schottky heterostructure construction. In a fabricated 52 nm 1T ′ -WTe 2 /GaAs vdW vertical Schottky diode, the gapless linear dispersion and the enhanced nonlinear optical effect of WSM WTe 2 improve the rectification behavior and the photovoltaic performance [306].
A barristor is a transistor-like Schottky device with a variable barrier suitable for device applications such as inverters. Barristors were first reported by Yang et al in 2012 as having an atomically sharp interface between graphene and hydrogenated silicon, as shown in figure 7(b) [307]. The Fermi-level pinning causing high device resistance in silicon electronics is overcome as the benefits from the negligible interactions between chemically inert graphene and a completely saturated semiconductor surface. Moreover, graphene's electrostatically tunable Fermi energy makes a well-controlled Schottky barrier realizable. Such devices achieved logic function with an on/off ratio of ∼10 5 , indicating an alternative route for IC scaling. Similarly, vertical thin film transistors (VTFTs) with amorphous indium gallium zinc oxide (α-IGZO) as the channel and graphene as a work function tunable contact are demonstrated [308]. This type of VTFT satisfies the requirements of high current density, high on/off current ratio, exceptional flexibility, and wafer-scale processability, which could be applied in high-performance wearable device applications.

Layered-traditional-heterostructure-based hot electron
transistor (HET). The performance of a HET with a metallic base is limited by carrier scattering and self-bias crowding. In thinner metal-base devices, the former is reduced, but the latter is exacerbated along with increased resistance. Therefore, atomically thin graphene, with its high conductivity, becomes an ideal material for HET bases. On the other hand, vertical HETs with graphene base exhibiting an on/off current ratio of over 10 4 have been realized, in which the Fermi energy of the graphene base is modulated to control the device states, as shown in figure 7(c) [309]. Follow-up studies show that applying bilayer insulator tunnel barriers can increase injected tunneling current density by promoting Fowler-Nordheim tunneling and step tunneling while suppressing defect-mediated carrier transport [310]. More recently, HETs with MoS 2 and HfO 2 as the filter barrier interface and a noncrystalline semiconductor such as ITO as the collector exhibited an unprecedented increase in the common-base current gain of ∼0.95 at room temperature, as shown in figures 7(d) and (e) [311]. HETs with graphene bases with a high joint base current gain and an intrinsic current gain cutoff frequency of around 65 GHz are also demonstrated [312], revealing a possible combination of layered-traditional heterostructures for hot-carrier complementary transistors. Furthermore, the dualmode operation of layered-material base HETs has been realized by varying the polarity of V CB , in which the alternative hot-electron mode or a reverse-current dominating mode enables multifunctional device applications [313].

Layered-traditional-heterostructure-based p-n junction
devices. p-n junction devices based on layered-traditional heterostructures have been already widely reported, including p-n junction diodes and transistors, tunnel devices, and JFETs. Compared with the classical p-n structure, semiconductorinsulator-semiconductor (SIS) diodes with the tunneling transport mechanism are able to achieve higher current and threshold voltages. An SIS heterojunction diode, consisting of monolayer MoS 2 , h-BN, and epitaxial p-GaN, can be created using a transfer strategy. The higher current and threshold voltage compared to conventional p-n junction indicates the dominance of tunneling transport, as shown in figures 7(f) and (g) [314]. With a top gate control, vertical FETs (VFETs) based on the p-n junction formed between monolayer to fewlayer n-MoS 2 and degenerately doped p ++ -Si and p ++ -GaN can be constructed. Such devices exhibit tunable Fermi level high tolerance to the interface quality with high rectification ratio and on/off ratio, as shown in figures 7(h) and (i) [315].
Similar with TMD-vdWH based devices, with the atomically sharp vdW interface between layered and traditional semiconductors, tunnel devices based on layered-traditional heterostructures have been well developed. Tunnel diodes based on n-MoS 2 /SiO 2 /p-Si heterostructure are reported to show multiple NDR peaks corresponding to the conductionband alignments of the different layer numbers of MoS 2 [316]. A tunnel diode without a separating insulation layer formed by transferring multilayer Nb-doped p + MoS 2 to heavily doped n + GaN shows a peak current of 446 A·cm −2 , a peak-to-valley ratio of 1.2, and minimal hysteresis, as shown in figures 7(j) and (k) [317]. MoS 2 /p-Si heterojunctions fabricated by in-situ CVD synthesis have also provided a fab processing method capable of constructing layered-traditional tunnel diodes [291]. A high current density of 1 µA·µm −2 in tunnel diodes is achieved by introducing n + -SnS 2 layered semiconductors integrated with p + -Si [318]. Recently, the tunnel diode behavior in highly uniform MoS 2 /SiC heterojunctions was reported [319]. The MoS 2 layer was p + -doped by the MoO 3 product formed in a predeposition-sulfurization process, realizing interband tunnel transport and NDR performance in the heterojunction, showing great potential for lowpower tunneling devices.
TFETs based on layered-traditional heterostructures with abrupt switching behavior also show great potential for further scaling without a power penalty. For example, a TFET using highly doped Ge as the source and atomically thin MoS 2 as the channel was demonstrated, as shown in figures 7(l) and (m). Benefiting from the excellent electrostatics and the low tunnel barrier at the strain-free clean interface, the TFET exhibited a sub-thermionic SS over four orders of magnitudes of drain current variation at a low power-supply voltage of 0.1 V [270]. Besides TMDs and elemental semiconductors, BP and oxide semiconductors such as IGZO have also proven to be excellent components for layered-traditional heterojunction devices. Utilizing the thickness-dependent p-doping characteristic of BP, thick and thin BP are used in stacked BP/IGZO vdWHs to construct a TFET with a minimum subthermionic SS value of 11 mV·dec −1 and a JFET with large on/off current ratio exceeding 10 5 , a high field-effect mobility of 23.5 cm 2 ·V·s −1 , and improved SS value of 83 mV·dec −1 [320]. Recently, a TFET based on the n-InSe/p ++ -Si vdWH was demonstrated [271]. The atomically thin nature of InSe coupled with the fixed doping profile in bulk silicon enabled the strong modulation of the band alignment by a capacitively coupled gate, finally leading to a BTBT behavior. These triodes have a current on/off ratio of approximately 10 6 and an on-state current density of 0.3 µA·µm −1 at a drain bias of −1 V, suggesting applications in ultralow-power and highly scaled logic switches.
Interestingly, p-TMD/n-Ga 2 O 3 layered-traditional heterostructures with an ultrathin TMO layer instead of a vdW interface separating the two different semiconductors exhibit unique functions similar to an ambipolar channel junction FET (JFET), as shown in figures 7(n) and (o) [321]. Despite the ultrathin oxide layer, the separated directional in-plane current passed through an n-type β-Ga 2 O 3 and a p-type TMD can be controlled by the heterojunction p-n diode, which shows a high on/off current ratio of ∼10 8 and an ideality factor of 2.4. Furthermore, the JFET could be developed into a photosensor, inspiring devices with hybrid architecture and functional applications.

Layered-traditional-heterostructure-based photodetect-
ors. Based on traditional semiconductors or TMD vdWHs optoelectronics, optoelectronics can be realized with p-n junctions formed between layered and traditional semiconductors. Figure 8(a) shows a photodetector based on a transferred n-MoS 2 /p-Si heterostructure [278]. With the approximate bandgap and different doping types of n-MoS 2 and p-Si, a type-II band alignment is achieved. When illuminated under reverse bias, photo-generated electrons and holes flow to the n-region and p-region, respectively, resulting in prominent photo-conductive behavior. Figure 8(b) shows a recently reported p-WSe 2 /n-Ge photodetector with ultrafast photoresponse, exhibiting fast rising and falling of approximately 3 µs under 638 nm illumination and 30 µs rising and 5 µs falling under 1550 nm infrared illumination [322]. Similar photodetectors based on type-II junctions between layered semiconductors and Si or Ge have been reported with various material combinations, including n-MoS 2 /p-Si [292,323], n-WS 2 /p-Si [292,324], p-WS 2 /n-Si [279], n-MoTe 2 /n-Si [325], n-SnSe 2 /p-Si [326], n-MoS 2 /p-Ge [327], n-WS 2 /n-Ge [328], and p-MoTe 2 /i-Ge [329].
Photodetectors based on layered semiconductors and III-V semiconductors are also demonstrated, such as WS 2 /GaAs photodetectors [330]. GaN is a third-generation traditional semiconductor with a direct wide bandgap of 3.4 eV falling in the ultraviolet (UV) spectrum region. A MoS 2 /GaNbased photodetector has been demonstrated to show broadband detection in the UV to near-infrared (NIR) spectrum region [331]. Recently, a p-GaSe/n-Ga 2 O 3 UV photodetector, where Ga 2 O 3 is a wide bandgap semiconductor, has also been demonstrated [332].
In some cases, an insulating layer is introduced into the layered-traditional semiconductor junction to form an SIS structure for improved performance. In a p-MoTe 2 /i-Ge photodetector, a GeO 2 layer was formed by Ge oxidation as a blocking layer to reduce hot carriers transporting and thus suppress the leakage current [329]. An AlO x passivation layer grown on Ge in an n-WS 2 /n-Ge photodetector was introduced to reduce the carrier traps on the interface and thus reduce the interface recombination [328].
The p-n junction between layered and traditional semiconductors can also be exploited as JFETs. As previously mentioned in section 3.3, p-MoTe 2 /n-Ga 2 O 3 JFETs (with the schematic diagram shown in figure 7(j)) also exhibit fast photoresponse under 16 kHz (visible red) to 29 kHz (NIR) illuminations [321]. A p-WSe 2 /n-ZnO JFET with photoresponse was also reported [333].
The Schottky photodiode is another typical type of reported layered-traditional-heterostructure-based photodetector. VdW Schottky interfaces can be formed between traditional semiconductors and metal or semimetal layered materials, including graphene [305,334] and metallic TMDs. Figures 8(c) and (d) shows a Schottky photodiode formed between metallic 1T-PtSe 2 and n-Si [335], where the figure 8(d) shows the mechanism of photocurrent generation under reverse bias. Similarly, Schottky photodiodes based on PtTe 2 /Si [285] and WSM 1T ′ -WTe 2 /GaAs [306] heterostructures are also reported. PdSe 2 is an atypical metallic TMD with a unique low-symmetry crystal structure, as shown in figure 8(e). This unique crystal structure makes it suitable for high-sensitivity polarization detection, which was realized in a PdSe 2 /GaN Schottky photodiode exhibiting a dichroic ratio of 4.5 [286]. The figure 8(f) shows the normalized photocurrent of the PdSe 2 /GaN Schottky photodiode as a function of the polarization of incident light.
Light absorbance is essential for the performance of photodetectors. The heterogeneous integration of layered and traditional semiconductors brings flexibility to the design of the microstructure of devices for absorbance improvement. Firstly, the 3D nature of traditional semiconductors allows the design of microstructures. A popularly adopted method is creating pyramid-like morphology on Si with wet etch, as shown in figure 6(c) [274,275,336]. Secondly, the robustness and solidity of traditional semiconductors allow more flexible formation methods of layered materials on it and, thus, more variable morphology while maintaining the electric properties of the devices. For example, as shown in figure 6(a), high absorbance can be achieved with the vertically standing MoS 2 on Si, resulting in ultrafast and high-contrast photodetection [282]. Similarly, in a p-SnS/n-Si heterostructure formed with PLD, the coexistence of laterally and vertically aligned layered SnS (figure 8(g)) results in enhanced light scattering and absorption [337]. The morphology of drop-cast Ag-WS 2 nanocomposites on Si also shows enhanced absorption and photodetection [281].

Layered-traditional-heterostructure-based light emitting diodes (LEDs).
Due to quantum mechanical confinement, the band gap in monolayer TMDs is direct, leading to a strong interaction with light that can be exploited for building layered-traditional-heterostructure-based LEDs. The light-emitting diodes based on vertical heterojunctions composed of n-type monolayer MoS 2 and p-type Si are shown in figures 8(i) and (j). The device also operates as a solar cell, with typical EQE 4% [338]. Concurrently, a higher energy electroluminescent exciton peak of 2.255 eV in monolayer MoS 2 on a heavily p-type doped Si substrate was discovered using a high electron-hole pair injection rate [339]. LEDs can also be realized by changing the substrate of the TMD material. For example, using p-NiO as the substrate, a monolayer MoSe 2 /NiO vdWH was constructed as an LED. The electroluminescence peaks of n-MoSe 2 /p-NiO LED locate at 812 nm, 848 nm, and 918 nm, all of which are in the infrared light range [340]. Large-area monolayer MoS 2 single-crystal nanosheets with a side length of more than 100 µm on GaN substrates were also synthesized for LED [341].
Notably, an indirect bandgap multilayer can also be used in fabricating LEDs. Li et al reported electric-field-induced strong electroluminescence in multilayer MoS 2 ; they showed that GaN-Al 2 O 3 -MoS 2 vertical heterojunctions could be created with rectification behavior, as shown in figure 8(k). The insulating Al 2 O 3 layer can partly block the electrons to inject from n-MoS 2 to p-GaN while allowing holes to be effectively injected from p-GaN to n-MoS 2 due to the unique band alignment (see band diagram in figure 8(l)), where the desired EL occurs. Their studies reported the broad-area EL emission of the entire junction area of the MoS 2 vertically stacked heterostructures and demonstrated unusually strong EL emission in the indirect bandgap multilayer MoS 2 [342].

Layered-traditional-heterostructure-based solar cells.
Many photodevices based on either p-n junctions [328,330] or Schottky junctions [305,335] have been demonstrated with photovoltaic effects. At the same time, most of these junctions' efficiency is not sufficiently high for the utility of energy conversion. A photovoltaic effect with an EQE of 4.4% and a broad spectral response was demonstrated in the device shown in figures 8(i) and (j), which is aforementioned as an LED [338]. A similar MoS 2 /p-Si heterostructure-based solar cell was presented with a PCE of 5.23% [343]. Schottky-diodebased solar cells are also reported, for example, a graphene/InP solar cell with a PCE of 5.6% [344].
Several strategies can be adopted to improve the efficiency of solar cells. By introducing an SIS structure and using a thin layer of oxide grown on Si, the built-in voltage of MoS 2 /Si heterostructure can be improved, consequently improving the V OC and PCE [345]. A similar strategy can also be adopted in a Schottky solar cell to form an MIS structure, for example, in a graphene/Si structure with an h-BN insulating layer [346]. When an insulating layer is introduced, the interface quality and the thickness of the insulating layer are crucial for the device's performance [347]. Lin et al demonstrated a MoS 2 /GaAs solar cell optimized with a combination of several strategies, including introducing an h-BN insulating layer, chemical doping of the MoS 2 layer, and electrical gating, with the device structure shown in figure 8(m), reporting a PCE of 9.03% [348]. A graphene/GaAs Schottky solar cell with combined surface-charge-transfer doping, antireflection-layer, and gating show an even higher PCE of 18.5% [349].

Layered-traditional-heterostructure based electro-optic
modulator. Electro-optic modulation has been reported with graphene/Si heterostructures. For example, Liu et al experimentally demonstrated a graphene/Si-based optical modulator with broadband modulating behavior, as shown in figures 8(n) and (o) [350]. Later research reported a graphene/Si-based modulator with a large modulation depth of 35 dB and a high modulation efficiency of 0.28 V·cm comparable with the state-of-art Si-based modulator [351]. Semiconducting layered materials and traditional semiconductors based modulator are feasible in principle [352].

Layered-traditional-heterostructure-based photocata-
lysts. In addition to their applications in electronics, layeredtraditional-heterostructure possess interesting catalytic properties for energy and chemical reaction. Photocatalysis for hydrogen production is a promising route to address current energy demands. For example, ZnIn 2 S 4 nanosheets were self-assembled on few-layer MoS 2 nanosheets to fabricate ultrathin and close-contact 2D heterostructure-based photocatalysts. The dramatically enhanced photocatalytic performance was ascribed to the better charge separation and the accelerated surface reaction as a result of the increased active sites provided by the MoS 2 heterostructure [353]. The nitrided 2D/3D heterostructure with an effective interface treatment exhibits a clean band gap and substantially improved capability of optical absorption and could be potentially used as a practical photocatalyst for hydrogen generation by water splitting using solar energy [354]. The principle of photocatalysis is further studied. Using first-principles calculations, Wang et al designed a MoS 2 -based heterostructure by stacking MoS 2 on ZnO, as shown in figure 8(p). The typical type-II heterostructure combined with large built-in electric fields and superb optical absorption make the MoS 2 /ZnO vdWH a great potential candidate for application in photovoltaic and photocatalytic devices [355].

Conclusions
In this review, the comparative coherence between layered and traditional semiconductors is carefully examined, highlighting the significance of layered-traditional heterostructurebased strategies in developing novel electronic and optoelectronic devices in the post Moore era. Over the course of more than a decade of research, various engineering techniques have been developed to modulate the properties TMDs, including phase engineering, defect engineering, layer number engineering, strain engineering, doping, and alloying. Moreover, in the 2020s, the fabrication processes for wafer-scale TMDbased devices have reached a mature stage, primarily attributed to the industrial compatibility of the CVD-based synthesis process. The fabrication of vdWHs among TMDs can be accomplished through transfer methods or sequential growth methods such as two-step growth or one-pot growth techniques. These exceptional materials properties and devices characteristics endow TMDs with unique and exciting opportunities to integrate with conventional semiconductor process technologies.
As for the TMDs-based electronic devices and optoelectronic devices, it is no doubt to extend Moore law to the sub-1-nm scale. Additionally, the vdW interfaces formed between arbitrary TMDs provide atomically sharp interfaces with a naturally tunable vdW gap, allowing for the creation of highquality tunnel interfaces preferred in the design of quantumtunnel-based devices, such as Schottky diodes, tunnel diodes, and TFETs with abrupt switching behavior. Furthermore, the direct-bandgap nature of monolayer TMDs facilitates the exploration and development of high-performance TMDbased optoelectronics, including photodetectors and solar cells.
Beyond pure TMD-based devices, various functional devices with superior performance have been demonstrated based on layered-traditional heterogeneous integration. VFETs and diodes have been presented. The direct synthesis of layered semiconductors on patterned microstructures based on traditional semiconductor offers a feasible approach of the integration of layered semiconductors into conventional CMOS process, enabling the fabrication of transistors with channels covered or replaced by layered semiconductors. The high-quality vdW interface between layered and traditional semiconductors further facilitates the fabrication of high-performance Schottky devices, such as barristors and tunnel devices, including TFETs with SS far lower than 60 mV·dec −1 . Optoelectronics based on layered-traditional heterogeneous integration has also garnered significant witnessed substantial advances in recent years.
Despite the tremendous opportunities brought by layered semiconductors and their heterojunctions, the precise control over physical dimensions, chemical composition, relative orientations, interface properties and the device performance remains a challenge that requires further investigation. In the case of layered-traditional heterogeneous integration, critical issues revolve around the stability and reliability of hetero interfaces, as well as the fabrication compatibility with CMOS technology. To develop high-performance layered-traditional heterogeneous integrated devices, concerted efforts are needed at both the material level and integration level, particularly in interface engineering. This involves reducing the contact resistance with metals, integrating high-k dielectrics, developing doping strategies and exploring strain engineering techniques. Another significant challenge lies in the fabrication compatibility of layered semiconductor devices with existing current CMOS process. Automatic wafer-scale transfer techniques of layered semiconductors with intact properties and clean interface, or alternately, low-temperature and highquality patterned growth methods of layered semiconductors on arbitrary substrates, are strongly demanded for large-scale device fabrication and integration.
Although commercialization of layered-traditional heterogeneous integrated devices is yet to be realized, substantial progress has been made in intrinsic physics, material properties, device structures, and integration strategies indicating promising prospects for the future. With the heterogeneous integration between novel layered semiconductors and well-developed traditional semiconductors, layered-semiconductor-based functional devices possess enhanced flexibility in material selection and structural design with higher comprehensive device performance, eliminated process and equipment development requirements, improved comprehensive device performance, greater acceptance by industrial chip makers, thereby paving the way for a technically and economically viable path in the post Mooreera.