An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories

In this work we experimentally demonstrate a Si 3 N 4 photonic integrated circuit which offers row decoding and RAM addressing functionalities. The passive integrated structure comprises a MRR-based wavelength filtering bank scheme in a 2 × 4 configuration, which reveals a suppression ratio in the range of 12–25 dB. The performance of the optical circuit has been evaluated in a system-level testbed, where successful addressing in one RAM row has been achieved. Error-free operation has been accomplished for all cases under study, with the whole row decoder system’s performance to offer a total power penalty of 2.5 dB.


Introduction
Fetching data from the memory in current computing architectures is still carried out at a lower speed compared to the processing speed offered by the CPUs, a problem that has been already identified a few decades ago and is typically referred to as the "Memory Wall [1].The efforts to overcome the speed limitations of electronic random-access memories (RAM) led to the introduction of a plethora of optical memory and optical RAM technologies during the last two decades [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20], with the main target being the transfer of the high-speed capabilities of photonic technologies into the memory segment.This aims at creating a seamless interface between the optical memory and the optical bus waveguide, enabling a transition into a data fetching and storing paradigm that can be performed exclusively in the optical domain.This visionary target has led to a remarkable progress in the scientific field of optical memory technologies: following the introduction of the first optical RAM cell back in 2009 [2], optical RAMs have witnessed important advances along all relevant key performance metrics, including speed, capacity and functionality.
The fastest experimentally demonstrated optical RAM cell has been shown to offer random access read and write operation at 10 Gb s −1 [3] with its respective theoretically predicted limits going to speed values up to 40 Gb s −1 [4].More recently, the deployment of complete optical RAM rows comprising four optical RAM cells per row allowed for an aggregate read/write throughput of 20 Gb s −1 per row [5].In terms of memory capacity and integration density, the adoption of photonic crystal-based technology platforms allowed to reach ultra-small footprint values [6,7] and multi-bit capacity developments, allowing for an impressive 512-bit on-chip optical memory technology through the use of InP photonic crystal modules [8,9].Finally, the migration towards highly functional optical memory blocks that can demarcate from simple multi-bit memory setups into addressable optical RAM banks and complete optical cache memories was initially proposed back in 2013 [10], but was only recently realized experimentally [11,12], designating an important milestone on the way to practical high-speed optical memory solutions that can support the whole chain of processes required within processor-memory transactions.
Taking, however, the next logical step towards fully integrated on-chip addressable optical RAM banks and optical cache memories requires not only the integration of RAM cells, but also the on-chip transfer of optical RAM peripheral circuitry, including column/row decoders (RDs) [13,14] and tag comparators [12].RDs, for example, have been already reported via different technology and operational concepts, relying either on injection locking mechanisms [15] or on single-mode Fabry-Perot Laser diodes [16] and semiconductor optical amplifier (SOA)-based configurations [14,17].All these deployments employ active optical structures for guiding the incoming optical signal to the selected output row, requiring electrical power supply for their successful operation.All-passive RD circuit architectures were initially proposed several years ago adopting Wavelength Division Multiplexed (WDM)-encoded optical information schemes together with wavelength-selective filtering bank setups for lowering the energy consumption overhead [13], with the same layout being also recently utilized in the experimental demonstration of the first 4 × 4 optical Cache memory.However, this all-passive RD circuitry has been so far realized only through discrete and fiber-pigtailed bulky optical filtering elements.A respective silicon-based integrated RD layout was initially proposed in [13] but has never been fabricated and demonstrated as a photonic integrated circuit (PIC).
In this work, we present for the first time, to the best of our knowledge, an integrated Si 3 N 4 all-passive 2 × 4 optical RD circuit and demonstrate experimentally its credentials to support successful Row Decoding in addressable optical RAM architectures that utilize WDM-encoded optical address fields.The integrated 2 × 4 RD chip comprises a 1 × 4 MMI splitter and an eight-element all-pass micro-ring resonator (MRR) filtering bank, with every one of the four MMI splitter outputs leading to a pair of cascaded MRRs.The experimental characterization of the 2 × 4 Si 3 N 4 RD PIC reveals a successful dual-resonant spectral response at every output waveguide, with a spectral rejection ratio that ranges between 12-25 dB.This multi-resonant filtering performance has been evaluated with respect to its optical RAM row addressing capabilities by utilizing a 2-bit WDM-encoded optical address at 5 Gb s −1 line-rate and driving a SOA-based optical RAM cell, presenting error-free random access read operation for all possible address combinations with a power penalty of 2.5 dB.

Principle-of-operation
Electronic decoder circuits are widely employed as address selection modules, being typically utilized in electronic RAM configurations for its row address selection and column address selection circuit stages.Figure 1(a) illustrates the layout of an elementary 2 × 4 electronic decoder circuit that utilizes two address bits A and B as its input signals and activates only one of the four possible Worldline (WL) outputs O 1 -O 4 for every different address bit combination, as shown in more detail in its respective logical truth table.
The proposed 2 × 4 all-passive optical RD circuit layout is presented in figure 1(b).It follows the design that has been initially proposed in [13] and includes a 1 × 4 power-splitter that connects to four different branches, with every branch hosting two cascaded MRRs of different radii and forwarding the propagating signal to a RAM row access gate (AG) unit.Its principle of operation relies on the adoption of a WDM-encoded address field, where two address bits (λ A and λ B ) and their complementary values (λ Ā and λ B) are encoded in the wavelength domain and enter the RD circuit as a WDM address stream.This stream is then broadcasted through the 1 × 4 splitter to the four RD waveguides, with every RD waveguide performing a two-channel wavelength-selective filtering operation by correlating the MRR resonances with two out of the four different wavelengths incorporated in the address field.In this way, two of the address wavelengths get filtered out and only the remaining two wavelengths are allowed to propagate through the MRR chain.Following this principle, a zero optical power will be obtained at the RD waveguide output only when the incoming address field content corresponds to the two wavelengths that match the MRR resonances.A non-zero optical power will exit the RD waveguide in all other address bit combinations, as can be more clearly seen in the truth table shown also in figure 1(b).As such, a logical '0' value will be provided only at the WL that gets activated, while all other three RD rows will transmit a logical '1' value that corresponds to a non-activated RAM row.

PIC design and characterization
A microscope image of the PIC 2 × 4 RD structure is depicted in figure 2(a).In figure 2(b) the mask layout of the proposed integrated unit is illustrated, indicating the test structures (yellow highlighted area), as well as the integrated RD scheme (green highlighted area).The proposed PIC has been designed on a low-loss Si 3 N 4 waveguide platform, having been fabricated by Ligentec.The structure consists of a strip waveguide of 800 × 800 nm, with propagation losses of 0.4 dB cm −1 .The cascaded rings of the structure indicate different radii values of R 1,1 = 54 µm, R 1,2 = 50 µm, R 2,1 = 62 µm and R 2,2 = 46 µm.In table 1 reveals the characteristics of radius, free spectral range (FSR) and Q factor of each ring structure.Additionally, an indicative spectrum response of the MRR, with 50 µm radius (MRR 1,2 ) is illustrated in figure 2(c), for a span of 20 nm (1540-1560 nm).The spectral response of the cascaded MRRs obtained across all four RD outputs were acquired through a wavelength sweep process, recording the RD waveguide output signal within a spectral span of 20 nm (1540-1560 nm).The wavelength characterization has been conducted with the use of a C-band tunable laser source (TLS) using in addition polarization controllers and a polarization maintaining fiber array unit (PM FAU) for polarization control purposes.The response of every one of the four possible WLs is presented in figure 3. The highlighted areas depict the four wavelength values that have been selected within the range 1552-1555 nm for the WDM address encoding, showing extinction ratio (ER) values that range between 12-25 dB.The total losses experienced by a single RD waveguide output were measured to be ∼22.2dB, which can be broken down into 0.2 dB for Si 3 N 4 waveguide propagation losses, 6 dB stemming from the 1:4 signal splitting, ∼1 dB per MRR structure and 14 dB for fiber in/out coupling losses.Based on the experimental measurements that have been performed for the specific Si 3 N 4 die, the discrete building blocks of the test structures have demonstrated the following insertion loss values: Spot size converters depicted losses of <3.5 dB, MMIs revealed an IL <0.25 and the MRRs have a loss of <1.2 dB.Given that the experimental measurements of the RD PIC show a deviation in terms of IL, compared to the expected values that have been acquired through various simulations, the main estimation is that the integrated circuit has experienced fabrication failures, which in turn lead to the higher ILs.In case that the fabrication errors could be avoided in the next fabrication run, the total losses of the RD circuit should be expected to be not higher than 15.9 dB [21].

PIC experimental validation
The validation of the PIC structure as RD circuit relies on the use of an experimental testbed that generates and transmits a WDM address signals through the PIC.The experimental setup is illustrated in figure 4(a)

Optical RAM row decoding
Having successfully verified the wavelength-filtering capabilities of the integrated RD the next step will be to utilize the structure in a complete RAM row addressing experimental implementation.Given, however, the unexpectedly high losses of the RD PIC, the optical power levels obtained at the PIC outputs were rather low and not enough for driving a subsequent optical RAM configuration.As such, its optical RAM row decoding credentials were verified by replacing the RD PIC with a corresponding fiber-based setup that was configured to offer identical wavelength filtering characteristics.The experimental setup utilized is shown in figure 4(c).It comprises again an ASGU similar to the one shown in figure 4(a), which feeds then a wavelength filtering bank stage (WFBS) that effectively implements the functionality of the RD PIC circuit.The WFBS comprises an AWG demultiplexer that separates the four incoming wavelengths into respective discrete output branches and employs a VOA and an EDFA at every branch in order to control the power level of every signal.ODLs are also utilized at certain stages for ensuring bit-level synchronization of the four signals prior their recombination at the WFBS output.In this way, the WFBS can be configured to provide an output spectrum that will be identical to the spectral response provided by a certain RD PIC output waveguide, ensuring the same SRs values and resembling in this way the wavelength filtering properties of the RD PIC.The WFBS output enters then the optical RAM row subsystem that stores one bit of optical information and comprises a SOA-MZI AG and a SOA-based FF.The WFBS output signal enters the SOA-MZI AG as a control signal, controlling in this way the access to/from the memory row.The memory row employs a single integrated InP SOA-based flip-flop (FF) cell, for every possible WL wavelength combination.Additionally, two CW signals (λ 5 = 1546.2nm and λ 6 = 1548.6nm) are being produced and launched into the optical integrated InP FF memory element, via port A and port C respectively.The bistable memory structure is based on cross-gain modulation phenomena, following a 'master-slave' configuration.Specifically, the memory device relies on a cross coupled arrangement, that includes two SOA components.The two SOAs are getting powered by the two CW signals (λ 5 and λ 6 ), allowing the SOAs to interchange between the 'master' and 'slave' states of the memory cell.In this specific approach the memory unit has been configured to operate at one of the two possible memory states (logical '1' memory state), with a detailed description of its operation presented also in [18].Consequently, the respective FF output signal is collected at port D and is also being amplified in order to enter into the SOA-MZI AG, through port F. At the output of the SOA-MZI AG the information of the wavelength conversion operation will be imprinted onto the λ 5 or λ 6 signal, with the output content being collected at port C of the AG.This operation allows for a complete RAM row 'Read' functionality, since the FF memory has a constant value of logical '1' , for every one of the four possible RAM rows of the specific implementation.The logical output signal of every RAM row operation is filtered and then amplified before being received by an oscilloscope and a bit error tester, for further quality evaluation of the received signals.The specific fiber-based implementation is embedded into a complete RAM Row unit, being presented in figure 4(c).
Figure 5(a) illustrates the spectrum obtained at the output of the WFBS (dashed lines) for every possible WL combination (WL '00'-WL '11'), with the solid lines showing the corresponding spectral response of the PIC RD for the same WL.In all four cases, the spectra of both the RD PIC and the fiber-based WFBS outputs reveal a perfect match, confirming that the fiber-based approach can successfully emulate the performance of the PIC RD circuit within a complete 2 × 4 RAM access experimental configuration.Figures 5(b) and (c) show the synchronized Address bit signal traces (Address bit 1 and Address bit 2 ), with every column including the address waveform of the two unsuppressed wavelengths, indicated at the top right corner of each time  trace.The combination of the specific address signals for every different WL case at WFBS output results to a multi-wavelength and multi-level signal that exhibits three different power levels, as shown in figure 5(d) for every possible WL.The memory content that emerges at the output of SOA-MZI AG for every respective WL is depicted in figure 5(e).The specific time traces indicate that the content of the FF memory can emerge at the output of the RAM AG only when both unsuppressed address wavelengths in this specific WL carry a logical '0' value, so that also the combined multi-level signal has a logical '0' value.In all other cases, the combined multi-level signal will have a non-zero power level that enters the SOA-MZI AG and blocks the memory content.
Finally, the performance of the proposed RAM row addressing architecture has also been evaluated through acquired eye diagrams and bit error rate (BER) measurements.Figure 6 illustrates the BER curves of the final RAM row output signal for all possible WL combinations, as well as for the Back-to-Back (BtB) modulated signals.The measurements reveal successful error-free operations, at 10 −9 , for all the memory addresses ('00' , '01' , '10' and '11') with power penalties that range between 1-2.5 dB compared to the BtB signals.Moreover, clearly open eye diagrams have been captured in all the WL cases revealing ERs of 3 dB for the cases of WL '00' and WL '11' , 2.7 dB for the case of WL '01' and 3.5 dB for the case of WL '10' .The operational conditions for all the above measurements were: an average power level of 2 dBm for every of the four data channels at the WFBS input, an average power of 5 dBm for the λ 5 and λ 6 signals at the FF output after the EDFA and an average power of −8dBm for the multi-level control signal when entering the SOA-MZI AG.The SOAs of the FF memory cell were driven at 180 mA, while the SOAs of the SOA-MZI RAM AG at 260 mA.

RD scale-up analysis and discussion
The specific proposed work features a 2 × 4 Si 3 N 4 integrated passive RD circuit, showcasing the prospect towards high-bandwidth memory applications and at the same time lower consumption approaches.Even though the current approach is limited to a 2 × 4 configuration, the RD architecture could also be implemented on a larger scale, in order to facilitate high-capacity RAM memory schemes.In this regard, an analysis of a scaled-up RD system, with the capabilities of serving 2 N addressing rows is being presented.A schematic layout of a N × 2 N RD is depicted in figure 7.In order to support the N address Bits, the architecture will require: 2 × N wavelengths for the addressing signals, N × splitting stages for the support of 2 N addressing lines and N × MRRs at every one of the 2 N supported rows.Based on previous experimental measurements for the individual structures on this same Si 3 N 4 platform, an approach for a feasible passive RD scheme would be to set an estimated upper limit of 5-bit addressing, with 32 addressing rows.For this certain layout the total losses can be broken down to: insertion losses of the spot size converters used for I/Os being 7 dB, losses of ring resonators to be measured <1.2 dB and the insertion losses of the MMIs to be 0.25 dB.In this approach, in case of injecting an input signal with a power of 20 dBm to the passive circuit, the proposed architecture would be capable of scaling up to a 5 × 32 RD, rendering the system sufficient enough for a RAM addressing operation.Thus, the total losses for a single row at the 5 × 32 RD configuration can be broken down into: 7 dB for I/Os, 6 dB for all the respective ring resonators and 16.25 dB for the total MMIs.Of course, the presented analysis on this completely passive RD configuration can be further extended in an even higher scaled-up approach, in case additional SOA circuits get implemented in such an arrangement.More specifically, in case the previous architecture is adapted and an input signal of 10 dBm power gets injected in the 1:32 configuration, the output power of every address row, prior to the MRRs of each line would approximately be around −10 dBm.Placing an additional 20 dB gain SOA component, at every output row, will lead to an estimated output power of 10 dBm, for every implemented line.Such an approach would be able to support 16 additional lines, for every one of the 32 rows, leading to 512 addressing rows in total, while providing an output power >−10 dBm in order to drive the AG unit.This hybrid architecture can support a 9-bit addressing scheme, serving as a 9 × 512 RD system.It needs to be mentioned that these scale-up solutions may impose various limitations due to the extra loss parameters of the additional splitting stages or due to the additional noise level and the wavelength dependence of the SOA gain, that will degrade the overall performance of the system.
The analysis towards a scaled-up architecture can be further exploited in case a complete RAM memory layout is also implemented.Based on the feasible approach of the 5-bit addressing ×32 rows RD addressing unit, a RAM bank layout, comprised by 4-bit memory lines can be incorporated in the current study, since the specific scaling has already been demonstrated experimentally [12].This proposed approach would require: 32 × SOA-MZI AG units, for facilitating every RAM addressing line and 128x FF memory elements, in order to address the 1:32 RD circuit.The considered RD passive unit is estimated to occupy an area of approximately 14 mm 2 , contributing only to the footprint requirements of the proposed architecture.On the other hand, the AG and memory units will also affect the energy requirements of such a scheme.Specifically, the total energy for all the necessary SOA-MZI AGs is estimated to be around 6656 pJ/bit, since every AG requires 208 pJ/bit and the aggregated energy consumption for all the memory cells would amount to 18 432 pJ/bit, if we consider that a single FF requires 144 pJ/bit.In terms of area dissipation, the memory elements for this complete RAM bank implementation will require an area of 896 mm 2 [18], while the area estimation for the gating elements cannot fully be addressed because of their bulky-based nature.Such proposed approaches require considerable footprint and energy requirements, but on the other hand can really facilitate in the realization of larger-capacity optical RAM layouts, escalating their overall capacity and data-rate capabilities.
Even though our work utilizes non power efficient and bulky SOA-based components, due to the fact that the target is to emphasize on the addressing capabilities of a completely passive RD element, the optical memory technologies have demonstrated significant advantages, regarding their power efficiency and their footprint capabilities.Towards this regard, the progress of the optical memory implementations has already been identified [6], when comparing them with their electronic counterparts.It is true that the state-of-the-art electronic memories [22][23][24][25] have revealed breakthrough technologies, based on new material designs, in order to further improve the impeded electronic memory systems.Such approaches are the various 2D materials, like the proposed 10 T SRAM cell [26], revealing capabilities of energy reduction up to 66% compared to conventional electronic cells.Additionally, the magnetoelectric RAMs have shown to be able to achieve switching times of less than 1 ns, and at the same time operate in the energy regime of fJ and even ZJ [27,28].However, the optical memory layouts have revealed that, during the past years, their power requirements have drastically reduced by five orders of magnitude [29], reaching down to the 1 fJ/bit, in specific cases.Their energy efficiency improvement is also accompanied by the reduction in the memory access time, reaching the 50 ps [30], since they can take advantage of their bit-rate transparent power consumption in order to offer high bit-rate capabilities.On the other hand, the electronics are required to balance between the trade-off of the access time and the energy efficiency.As reported, some electronic technologies have revealed energy approaches in the fJ regime for access times of around 160 ps, while in the case that the power requirement is reduced to the aJ scale, the access time increases to 300 ps [31], revealing their loss in access time improvement in case that the target is a lower-energy approach.It becomes clear that the Optical memories have the potential to scale down even more their power consumption and footprint, which will also lead to enhanced capacity and bit-rate capabilities.Additional different approaches, such as the phase change materials [6,9,19] or the photonic crystal technology [6,7], can offer footprint capabilities of around 1 µm 2 and additionally operate with energy requirements of less than 1 fJ, for the second case.These numerous approaches can significantly facilitate in paving the road towards the realization of fast, with small footprint and low power consumption optical memory systems, rendering them as a challenging candidate against their electronic counterparts.Detailed analysis and comparison of the emerging optical memory technologies can be found in previous presented works [6,32].

Summary
This work presents an experimental demonstration of an integrated Si 3 N 4 PIC that can perform as a 2 × 4 RD structure.The specific chip utilizes MRR-based filtering elements, in a wavelength-filtering bank configuration, addressing one out of four RAM rows, within an optical RAM bank architecture.The PIC wavelength characterization indicates promising wavelength-filtering capabilities, for a successful row decoding operation, at 5 Gb s −1 .On top of that, a fiber-based row decoding approach has been experimentally implemented, for the evaluation of a complete optical RAM row access functionality, at 5 Gb s −1 .Different cases under study indicate error-free operation, with a total power penalty of 2.5 dB, in the worst case, paving the way towards effectively integrated memory implementations.

Figure 1 .
Figure 1.(a) Implementation of an electronic decoder unit and its respective truth table and (b) Layout of an optical decoder unit with its respective truth table.

Figure 2 .
Figure 2. (a) Microscope image of the PIC RD, (b) mask layout of the integrated structure and (c) R1,2 test structure's spectral response.

Figure 4 (
b) illustrates the output spectra obtained at all RD WL outputs ('00'-'11').The dashed lines of every graph correspond to the input spectrum injected into the PIC RD of the four signals, while the solid lines represent the output spectrum at every WL output.As can be noticed, two out of the four incoming wavelengths in every WL exit the RD PIC with a significantly lower power level, since they match the MRR resonances employed in this specific WL.More specifically, the suppression ratios (SRs) of the two suppressed wavelengths are 14.5 and 21.5 dB at the WL '00' output, 21 and 25 dB at the WL '01' output, 12 dB and 15 dB at the '01' WL output and, finally, 15 dB and 20 dB at the '11' WL output.This indicates that the PIC circuit can successfully perform as a RD circuit when two out of the four wavelength signals are utilized in order to carry out a 2-bit addressing implementation.

Figure 4 .
Figure 4. (a) Experimental setup for the validation of the integrated row decoder, (b) spectral response at every RD WL output and (c) experimental setup for optical RAM row decoding.

Figure 6 .
Figure 6.BER curves for BtB and RAM access cases, along with the respective eye diagrams, at 5 G s −1 .

Figure 7 .
Figure 7.A schematic of a N × 2 N row decoder architecture.

Table 1 .
Measured test structures characteristics.