Contact engineering for organic CMOS circuits

Organic field-effect transistors (OFETs) have been widely studied, but there are still challenges to achieving large-scale integration in organic complementary metal–oxide–semiconductor (CMOS) circuits. In this article, we discuss the issues on organic CMOS circuits from a device perspective. Our discussion begins with a systematic analysis of the principal parameters of the building block, a CMOS inverter, including gain, noise margin, and power dissipation, as well as the relevant challenges and the potential solutions. We then review state-of-the-art organic CMOS inverters and their fabrications. Finally, we focus on the approaches to optimize organic CMOS circuits from a specific point of view of the contact engineering, particularly for N-type OFETs.


Introduction
Organic electronics attracted great attention for unique features of large area, flexibility, and low cost [1][2][3][4], and has been used in various fields like flexible display [5], biological sensor [6], internet of things, solar cell [7], and integrated circuit (IC) [8].As a fundamental building block, organic field-effect transistor (OFET) played the most important role therein.The mainstream IC technology so far has been relied on silicon, from the bulk metal-oxide semiconductor FETs (MOSFET) to silicon-on-insulator and FinFET and to the latest gate-all-around devices [9], the demand for new applications, in particular organic electronics, is constantly growing.Despite that, organic devices still face serious challenges, e.g.poor charge transport and charge injection.The performance gap between organic and silicon-based devices is huge [10].Regarding the charge transport, the highest electron mobility reported in N-type organic semiconductors (OSCs) is about 6 cm 2 V s −1 [11], which is two orders of magnitude less than that in silicon (∼1000 cm 2 V −1 •s) and also less than that in III-V semiconductors like InGaAs (∼4000 cm 2 V −1 •s) [12].In terms of operating stability, the molecules of OSC are linked by van der Waals force, which makes organic devices susceptible to the external influences, e.g.water and oxygen [13].As devices' channels continue to shrink, contact engineering becomes a critical issue.In this respect, the injection mechanism of OFETs differing from the P-N junction contact injection of the silicon-based is mainly dominated by the Schottky barrier at the contact interface between the source/drain (S/D) electrode and the OSC [14].Therefore, researches have been devoted to contact engineering.Many methods have been proposed to reduce the Schottky barrier and interface effect to enhance the efficiency of charge injection, such as doping [15][16][17], interlayers [18][19][20], chemical modification [4,21].For organic CMOS circuits, though P-type OFET has made progress in performance improvement, N-type OFETs still face serious challenges, mainly due to the poor charge injection at contacts [22].
In this article, we discuss the organic CMOS circuits and the relevant impact of contact engineering.Our discuss starts with the principle parameters, namely, gain, noise margin (NM), and power dissipation that determine the performance of CMOS circuits.Next, we revisit the recent progresses of CMOS inverters incorporating novel materials and structures.After that, our attention is turned to the recent advance of organic CMOS circuits and the fabrication processes.We also analyse the challenges faced by the present organic CMOS technology from a perspective of device design.Finally, we focus on the impact of contact engineering on the device, mainly for N-type OFET, and discuss the potential solutions.

Basics of CMOS circuitry
ICs have developed for decades, starting from the invention of transistor to small-scale integration, medium-scale integration, large-scale integration (LSI), and very LSI [23,24], where CMOS architecture played a vital role.
CMOS circuit is based on complementary and symmetrical pair of P-type and N-type MOSFETs.Taking inverter as example, a CMOS inverter consists of a NMOS and a PMOS, as shown in figure 1.When the input voltage (V in ) is low, the PMOS is activated and the NMOS is deactivated, leading to a high output voltage (V out ) ('1').Conversely, when V in is '1' , the V out is '0' .This CMOS design offers low power consumption, higher switching speed, and great robustness to noise compared to unipolar inverter.Of course, the principle of complementary symmetry can be extended to more complex logic gates, such as NAND, NOR, or XOR.Up to now, CMOS circuits have been mainly referred to silicon-based ICs.In fact, the concept of CMOS can be also adapted to OFETs-based circuits.

Principal parameters
As a fundamental building block, CMOS inverter is often utilized as a testing vehicle to verify the circuit function and to evaluate the circuit performance.Therefore, we discuss the principal parameters of CMOS inverter, viz., gain, NM, and power consumption.

Gain
The gain of a CMOS inverter is defined as the differential of V out in the CMOS voltage transfer characteristics (VTCs) with respect to V in , which is calculated by dV out /dV in .In the CMOS VTC curve, the point V in = V out is defined as the switching threshold (V M ) and the maximum gain typically occurs near the switching threshold V M .In principle, it is desirable to have a gain as high as possible since higher gain delivers higher performance [25].From a device point of view, high gain can be obtained by increasing the mobility, e.g. using semiconductors with high carrier mobility [26].For a fixed technology, however, the semiconductor cannot be changed freely.One can thus find different ways to improve device performance.In this regard, contact engineering is crucial, especially for devices that use novel semiconductors.Because conventional doping techniques (e.g.ion implantation) cannot be applied directly.

Noise margin (NM)
NM is defined as the maximum noisy signal that a circuit can tolerate.As long as the noise remains within the tolerance defined by the NM, the device will operate correctly to provide the expected output.
In the literature, there are many definitions for NM [27,28].The first detailed description of NM and their relationship to the transport characteristics of logic gates was published by Hill CF in 1967 and1968 [29, 30].Later, Lohstroh gave a summary [28].At present, the '−1' slope criterion is widely accepted for most of digital circuits.As shown in figure 2, the abscissas represent the minimum input voltage (V IL ) and the maximum input voltage (V IH ), and the ordinates represent the minimum output voltage (V OL ) and the maximum output voltage (V OH ).The corresponding high-level noise margin (NM H ) and low-level noise margin (NM L ) are defined as: The NM of an inverter can be improved by designing its VTC curve to be as symmetrical and steep as possible.This can be achieved through a variety of methods, such as adjusting the device characteristics of the NMOS and PMOS to be well matched so that the switching occurs at the half of the supply voltage and the NM for both of high and low-levels can be maximized.The VTC curve will shift left or right if parameters do not line up, preventing VM from being equal to 1/2 V dd and leading to an imbalance between high and low-level NMs.This issue can be avoided through contact engineering techniques like doping and other approaches or by modifying the gate dielectric interface to adjust the performance of N-type and P-type devices, respectively.

Power dissipation
Power dissipation has always been a major hindrance to the technology evolvement.As the integration scale increases, power dissipation becomes a serious concern.For a CMOS IC, the total power dissipation includes P total = P dynamic + P static . ( With regard to the dynamic power dissipation, it arises typically from two sources.The first is the power consumed during the CMOS switching.When the parasitic capacitor (C L ) is charged through the PMOS transistor, its voltage rises from 0 to V dd , at which the devices absorb energy from the power supply.Some of this energy is consumed by the PMOS transistor, and the rest is stored in the parasitic capacitor C L .When the parasitic capacitor C L is discharged through the NMOS transistor, the high voltage is switched to a low voltage.At this time, some energy will be consumed by the NMOS transistor as well, in addition to the energy released by the capacitor discharge.The dynamic power dissipation can be expressed as where k is the active factor denoting the activity degree of all gates in IC, V dd is the supply voltage, and f is the operating frequency.The second source is on-power dissipation, which occurs when the input waveform is not zero under ideal conditions.When the output signal transitions from a high to a low level, both the PMOS and NMOS transistors are on at the same time, and the on-resistance of the transistors generates additional power dissipation.A number of approaches have been proposed to reduce the dynamic power [36][37][38], e.g.decreasing V dd .Furthermore, the gain and noise tolerance all rely on the supply voltage.So, finding the balance between circuit performance and power dissipation is challenging.If it is not feasible to lessen the supply voltage without sacrificing performance, reducing the parasitic capacitance and the operating frequency become alternative solutions.However, for most devices, the operating frequency (f ) is fixed, so the only option is to reduce C L of the CMOS circuit.This can be achieved by using devices with smaller area and lower-κ dielectric [39][40][41][42][43][44].
The static power dissipation of a CMOS inverter is not zero due to the existence of off current (I off ).The resultant static power dissipation is It is obvious that reducing I off is essential, and in fact, is challenging.Proper IC design can alleviate this issue [45,46], yet from a device point of view, I off originates mainly from leakage current in the subthreshold regime and gate leakage [46].It is usually optimized by utilizing high-κ dielectrics and by optimizing deposition methods to obtain gate dielectrics with lower defect states [47][48][49][50].For organic inverter, on the other hand, high I off may stem from a different origin, ambipolar conduction.This is because one of the paired PMOS and NMOS is not fully turned off in the nominal off state, but rather enters ambipolar conduction state.For the conventional Si MOSFETs, they are unipolar devices so the channel can be well switched off in the off state.A so-called subthreshold regime separates the off-and on-states.In OFETs with ambipolar conduction channel, there is no subthreshold regime at all.The observed subthreshold slope is often very high and the minimal drain current (or I off ) is orders of magnitude higher than that in unipolar transistors.To weaken ambipolarity, contact engineering has been proved to be effective, such as introducing interface dipole [51][52][53] and doping [52,54].Note that, the supply voltage is also responsible for static power consumption, which can be reduced by gate engineering [55].Some researchers have also proposed new device structures to reduce static power consumption, such as a biristor threshold switch and so on [56].In a word, the precedent discussions indicates that the performance of a CMOS inverter can be optimized by contact engineering.

CMOS circuitry using novel semiconductor devices
Before moving on to the OFET-based CMOS circuits, we briefly revisit the recent development of CMOS circuits using novel semiconductors and novel device structures.
Novel semiconductors are important to the next-generation ICs.Among them, two-dimensional (2D) semiconductors demonstrated the most promising potential owing to their unique 2D microstructure and great electronic properties [57][58][59].At the beginning of 2D research, it was challenging to achieve CMOS inverters using a single 2D semiconductor.Two different semiconductors were commonly utilized, cf table 1. Transition metal chalcogenides are a series of 2D semiconductors with variable energy-band structures, among which MoS 2 is the most widely reported one [60].MoS 2 FETs essentially exhibit N-type characteristics for sulphur vacancy defects [61].In order to build CMOS circuits, efforts have been made by using heterogeneous combinations of different P-type semiconductors, e.g.carbon nanotubes, BiSr 2 Co 2 O 8 , black phosphorus (BP), WSe 2 , and MoTe 2 , etc [32][33][34]62], as depicted in figure 3(a).
Note that, fabrication of CMOS circuits using a single semiconductor is the best way, since the manufacturing processes and thus the cost can be reduced.A two-dimensional semiconductor material with strong ambipolarity is required.In this regard, WSe 2 shows its superiority over MoS 2 [67].CMOS inverters can be achieved through channel doping or contact engineering, as illustrated in figure 3(b).For channel doping, different dopants were used to make ambipolar semiconductors and in turn to achieve unipolar conduction (N or P-type).For instance, Yu et al examined the doped WSe 2 to realize P and N-type transistors separately [64].Through this doping, WSe 2 CMOS inverters exhibited good characteristics over a wide voltage range, with full logic swing, abrupt change, symmetrical sharpness, and high NMs.As for the contact engineering, numerous techniques like doping, self-assembled monolayers (SAMs), and interlayer were employed to adjust the contact physics so as to realize unipolar devices and high-performance CMOS circuits.Tosun et al fabricated CMOS inverter by using work-function matched metals and doping techniques [63].So, contact engineering allows for convenient control of the performance of CMOS inverters and provides ideas for improving organic CMOS inverters.
Besides 2D semiconductors, oxide semiconductors also demonstrated the possibility of realizing high-performance CMOS circuits owing to their electrical properties and high environmental stability, e.g.IGZO (indium gallium zinc oxide) [68].Unfortunately, high-performance P-type oxide semiconductors are still lagging [69], so the oxide-based circuits are not CMOS-like in early research.In 2021, Hsu and colleagues used IGZO and SnO to fabricate N-and P-type transistors on the same substrate by patterning techniques [25].
In addition to the conventional CMOS inverter structure mentioned above, three-dimensional (3D) inverter structure was also devised to improve space utilization, as shown in figure 3(c).The 3D inverters were attained by stacking multiple layers [65,66].Yet, this structure contains numerous heterojunctions, which could generate a large number of defects and interface effects.While there are some limitations in preparing this innovative structure, it presents a new avenue for exploring CMOS circuit.
Through the investigation above, it can be seen that the operational principle of these novel semiconductor devices is similar to that of OFETs and thus their development is a good reference for the research of organic CMOS circuits.

Organic CMOS circuitry
Organic CMOS circuits have seen significant advancements in performance.In terms of gain, Guo et al developed an organic complementary inverter by connecting an N-type organic permeable dual-base transistor and a P-type organic permeable base transistor, reaching a high gain of 28 [70].To attain even higher gains, Lee et al demonstrated an ultra-high gain of 81.1 by using a double-gate structure [71].
In modern CMOS inverters, NM is a critical parameter for enhancing anti-interference capability.Realising a higher level of NM need to ensure that the N-type and P-type devices have similar electrical characteristics.For instance, in 2021, by varying the molecular ratio of dielectric, Park et al realized balanced electrical characteristics between a pentacene-based P-type and a N,N ′ -dioctyl-3,4,9,10perylenedicarboximide (PTCDI-C 8 )-based N-type OFETs, achieving the high NM (up to 12.78 V at V dd of 40 V) [75].
Power consumption is a critical consideration for practical application.In a unipolar inverter, power is constantly dissipated through the load resistance, while a CMOS circuit reduces power consumption because only one transistor is turned on during operation.Yet, organic CMOS inverter may not be able to turn off completely due to the ambipolar conduction.Contact engineering, e.g.doping or adjusting the energy band matching of contact interface, has been attempted to avoid ambipolar charge injection [15,52,76].Also, organic transistors usually operate at high voltages, which is not desirable to reduce power consumption.So, negative capacitance transistors incorporating ferroelectric hafnium oxide can operate at low voltage with a mobility as high as 10.4 cm 2 V −1 s −1 .The composed inverter exhibited a peak power of about 50 nW [77].In 2020, an ultra-low power consumption (1 nW) was reported by Sawada et al, who adopted a highly heat-resistant poly (adamantyl methacrylate) as the interlayer between the OSC and the dielectric layer, which provided large single-crystal domains and lowers the dielectric/OSC interface state [78].
According to the recent advancements in organic CMOS circuits, their manufacturing can be mainly classified into three methods: spin-coating, inkjet printing and blade coating.Inkjet printing has been a popular technique to fabricate OFETs because of its ability to form high-resolution patterns without the need of masks, as well as the efficient material utilization and the absence of physical contact [72].However, this method often produces non-uniform film for the low viscosity of semiconducting ink and the uneven drying speeds of droplets on non-absorbent substrates, resulting in coffee ring effect.To address this issue, it is common to use a blend of high-boiling and low-boiling solvents with different surface tension energies, which reduces the evaporation rate at the edge of the liquid deposit [79].Alternatively, increasing the substrate temperature also can lessen the effect [80].Spin coating is another widely used method to deposit film and to make organic CMOS circuit.Spin coating can achieved great electrical characteristic at low cost [81,82].In this process, the quality of the film is directly influenced by the speed during spin coating, and the annealing after spin coating.
Besides the above two conventional methods, blade coating has become one of the most popular and important methods to prepare high-quality semiconductor films.This technique can modify the arrangement of organic molecules and the film roughness, yielding high-performance organic semiconductor film for OFET application [83][84][85].
Many other techniques have been explored too, including self-assembled monolayers (SAMs) and reverse offset printing (ROP).SAMs were employed to adjust the work function (WF) of metal electrodes.Now, with the optimization of the process, it can be adapted to form semiconductor films, as shown in figure 4(b) [73,86].This approach has gained attention in making organic devices owing to the surging demand for miniaturization.As for the ROP, it is a method to fabricate single-micrometre features that can form patterns with good edge definition, regardless of the size of the printed features [87].In 2021, Yu et al reported high-resolution organic CMOS inverter using a patterned pentacene ink layer made by ROP [88].Additionally, ROP can be applied to prepare electrodes for stacked devices, resulting in a flat electrode surface suitable for devices with a stacked structure [74].

Contact engineering for organic CMOS circuits
Despite the progresses made over the past years [1,10,89,90], numerous challenges remain unsolved.Contact engineering is one of the challenges to realize high-performance organic CMOS circuits, since it directly affects the parameters of CMOS inverter.In the next section, we focus on the contact engineering for organic CMOS circuits, in particular for N-type OFETs.In Si MOSFETs, Ohmic contacts are made by heavily doping the Si at contacts so that charge carriers can be easily injected from the metal contact into Si via tunnelling.The effective Schottky barrier is negligible.In OFETs, however, the well-established doping technique (e.g.ion implantation) is not feasible for the fragile OSCs.So, the contact between source/drain electrode and OSC is primarily Schottky contact with a sizable energetic barrier.As a consequence, the contact resistance (R c ) of OFETs is often of 100 Ω•cm and even more, which is much higher than the R c in Si MOSFETs (0.01 Ω cm) [91].Such high contact resistance seriously degrades the device characteristics and in turn the performance of CMOS inverter.Note that, the contact engineering of organic devices not only impacts the contact resistance but also the off-state current, which influences the power consumption [92,93].
The charge injection from metal into semiconductor can be through thermionic emission and filed emission (tunnelling), as shown in figure 5.The current density (J) can be expressed as: where J 0 is the reverse-saturation current density, q is the elementary charge, V a is the applied voltage at the contact, k is the Boltzmann constant, T is the absolute temperature.Without considering the image force and interface dipole, according to the thermionic emission model known as the Richardson-Schottky Model, J 0 is: where A * is the Richardson constant, φ b is the Schottky barrier.If the semiconductor is heavily doped, the depletion width is greatly reduced.The charge injection will change from thermionic emission to tunnelling, and its current density can be rewritten as: where h is the modified Planck's constant, ε is the relative dielectric constant to vacuum, ε 0 is the vacuum's permittivity, m * is the effective mass, and N D is the doping concentration.If gap states distribute at the metal-semiconductor interface, charge injection may also appear as a charge transition from the metal level through the gap states into the semiconductor, as shown in figure 5 (right panel).The contact resistance R c is defined as: So, the R c corresponding to the above thermionic emission model and tunnelling model can be obtained: From both models, one can see that R c is exponentially related to φ b , and thus the height of the Schottky barrier plays a vital role.For an ideal condition assuming that the vacuum level aligns, the WF of the metal is φ m , the electron affinity is χ, and the ionization energy is I, then the height of the Schottky barrier (φ b ) can be expressed as: where φ bn and φ bp are the Schottky barrier to electron and hole injection, respectively.In OFETs, the height of Schottky barrier varies with interfacial dipole, gap states and extrinsic factors such as image-force effect, and may deviate sizably from the above theoretic prediction.Kelvin probe force microscopy can detect the potential difference between the tip and the metal sample to measure the metal's WF [20,94].The height of Schottky barrier can be directly measured by photoelectron spectroscopy [95], or by I-V characterizations at different temperatures.For more details, readers can refer the previous review by Xu et al [14].

Contact issue for N-type OFETs
As a basic component of organic CMOS inverters, high-performance N-type OFETs are important.Up to now, the highest electron mobility of N-type OFETs has exceeded 10 cm 2 V −1 s −1 [13,90].However, due to the energy level position of the lowest unoccupied molecular orbital (LUMO) of N-type organic semiconductors (3.0-4.0 eV below the vacuum level) and their high susceptibility to water and oxygen in air [96], high-density of charge traps are often generated, affecting both of charge injection and stability.Therefore, N-type OFETs develop slower than the P-type rivals [1,20,97].As mentioned previously, charge injection is impacted by a number of factors.Among them, the LUMO level and the interface morphology are critical.Next, we discuss in more detail.

Energy levels
In N-type OFETs, electrons need to overcome the Schottky barrier (φ bn ) to be injected from the Fermi level of the source electrode into the LUMO level of the OSC.Often, gold (Au) is the most commonly choice of source/drain electrode [20,99,100].Its WF is quite high, ∼5.1 eV, which is much higher than the LUMO of most N-type OSCs (3.0-4.0 eV).Hence, Au-contacted N-type OFETs have high contact resistance.Although low WF metals (e.g.Ca, Mg) can deliver lower Schottky barrier [22], their active properties easily cause chemical reaction, e.g. with water and oxygen in air, making device very unstable.Inserting interlayer to reduce the WF of source/drain electrodes is thus effective [101,102].

Morphology
Morphology plays an important role in charge injection [1,103].Rough interface introduces high-density gap states, providing energetic ladders to charge carriers at contacts.The morphology of the contact interface can be altered by the fabrication method of the contact electrodes and OSC, and the annealing (temperature, duration).These process steps have a direct impact on interface states.If not optimized, these may introduce abundant traps and thus generate a large number of gap states at the interface, which could lead to undesirable consequences like Fermi-level pinning.For instance, spin coating, a straightforward and inexpensive technique, is frequently used to deposit polymer semiconductors, where the coating parameters, the annealing, and the solution are essential [81,104,105].However, the produced film has poor consistency.Small-molecule OSCs can be formed through thermal evaporation in a vacuum and a solution process [106][107][108].This process can produce high-quality film but is often difficult to control.As for the fabrication of contact electrodes involves thermal evaporation in a vacuum, i.e. physical vapour deposition.
And similarly, the evaporating rate can influence the electrode morphology [109,110], which is the most common way to prepare electrodes, but the formed electrodes are less dense.Of course, metal electrodes can be produced by other methods like ROP and sputtering, which may deliver higher-quality electrodes with reduced interface effect [74,111,112].Among these, sputter is now widely used in commercial silicon-based chips, while ROP is not yet mature.
In addition to the fabrication of electrodes and OSC, device structures call for attention too.OFETs can be classified as top-contact and bottom-contact, according to the positions of the contact electrodes and OSC.For top-contact OFETs, the OSC film is first formed on the substrate and then the source/drain electrodes are deposited on top of the OSC film.In this case, good contact not only requires smooth OSC film but also precise control of the deposition rate for source/drain electrodes.If the rate is too fast, the high temperature may damage the OSC film, while if the rate is too slow, the metal may diffuse into the OSC film and form metal clusters [110].For bottom-contact OFETs, good contact interface necessitates additional attention for the surface treatments of the source/drain electrodes, e.g. by SAM [113,114].

Solution to contact limitation for N-type OFETs
In the next section, we will examine methods to improve the charge injection by using alternative contact electrodes, inserting interlayer, and doping.

Conductive polymer electrode
The straightforward way to improve electron injection is by energy-level alignment.Low-work-function metals are thus selected to match the OSC's LUMO, yet limited by their high chemical activity.To address this issue, Lyu et al applied a conductive polymer (PEDOT:PSS) as the contact electrodes by means of electro fluid dynamics inkjet printing [98].PEDOT:PSS can vary the WF by adjusting the ratio in addition to having high conductivity and good film-forming qualities [115][116][117].Two kinds of PEDOT:PSS solutions were mixed at different volume ratios to adjust from the highest WF (HWF, about 5.28 eV) to the lowest 4.53 eV, as seen in figure 6(a).When the ratio of PEDOT:PSS is 0:1, the WF is the lowest (LWF, about 4.53 eV) closing to the OSC's LUMO.When the ratio of PEDOT:PSS is 1:0, the WF reaches the highest (HWF, about 5.28 eV) closing to the OSC's HOMO (highest occupied molecular orbital).The output and transfer curves shown in figure 6(b) indicate that the contact is Ohmic and the device characteristics are good.Note that, polymer electrodes are easy to prepare without concern of oxidation.So, conducting polymer is an appealing alternative of metal for contact engineering.

Interlayer
Though energy-level alignment is effective, it is sometimes hard to find the suitable materials.Modulating WF by inserting an interlayer becomes interesting, which can be divided into two types.
For the first kind, the electrode's WF and thus the Schottky barrier are directly modulated by several chemical materials, such as NaBH 4 , PEO z and so on.For example, Kim et al recently fabricated staggered OFETs with contact between the top and bottom of the gate by using a solution-based processing; see figure 7(a).They inserted a NaBH 4 interlayer to modulate the WF of gold (Au) electrodes from 4.7 eV to 3.7 eV [118].The NaBH 4 interlayer, which is equal to N-type doping of the interface, improved electron transport while suppressing ambipolar property of the devices, reducing the off-state current.Nam et al also improved the charge injection by using non-conjugated neutral dipole polymer (PEO z ) to form nano-point structure [4].Through a solution-based treatment, PEO z was proven to be an effective interlayer to induce dipole.The effective WF of Al/Au electrodes was reduced, enhancing N-type FET performance.Note that, most of the treatments discussed so far are for bottom-contact devices.For the OFET with top contacts, Sarkar et al reported P(NDI2OD-T2) thin film on Si/SiO 2 surface, mixing hexa(ethyleneglycol)-dithiol (HEG-DT) with P(NDI2OD-T2) solution through a self-generated interlayer method and eventually form the interlayer between OSC and electrode automatically [119].The WF of silver is reduced by the polarized O-C bond of HEG-DT itself [22,120].
For the second type, an intermediate energy states are generated, allowing charge carriers to hop through these gap states without need to overcome the Schottky barrier [19,121].Those interlayers can improve the contact morphology between metal and OSC, alleviating issue on low crystallinity of OSC caused by uneven morphology.In this regard, metal oxides are commonly used [122,123].For instance, CuO offers an energy state close to the HOMO, which improves the performance of P-type OFETs [124].For N-type OFETs, there are very few reports on this topic.Roh and co-workers found that ZnO is an effective interlayer to improve the performance of N-type OFETs [125].

Doping
Doping is the well-known approach to make Ohmic contacts.Different types of dopants are applied to N-type and P-type OFETs separately so that high-performance organic CMOS inverters can be obtained.Chen et al achieved unipolar P-and N-type OFETs by using P-type (TrTPFB) and N-type (N-DMBI) dopants, respectively, on a single ambipolar OSC [126].Although the performance of individual devices has been greatly improved, this method cannot be applied to the designated regions like local doping.In order to realize organic CMOS circuits by modulating contacts, local doping is required.Xu et al realized selective doping of contacts for OFETs [15,16].On the other hand, doping incurs some negative effects.Dopants may diffuse into OSC, altering the threshold voltage and the off-state current [16,127].This issue gets more pronounced as the device scales down, eventually making device fail to turn off.In order to alleviate this problem, Kim et al proposed a scheme to hinder the doping diffusion by dopant-blockade molecules [17].Some other works also showed that diffusion can be solved by a polyelectrolyte layer at the interface to attain local doping.In this process, ion exchange between the dopant and polyelectrolyte molecular layer results in a polarization layer for doping; see figures 8(a) and (b) [128,129].Finally, it should be mentioned that the number of dopants available for organic semiconductors is still limited and a well-established doping technique suited for OSC and OFET is highly desired.

Self-assembled monolayer (SAM)
SAMs have commonly been employed for interface treatment [132], to reduce the roughness of metal electrode [133,134] and to regulate the WF [135,136] by inducing interface dipole [137,138].Thus, one can manipulate charge injection in N-type and P-type OFETs by using different SAMs.Through precise control  [131].In order to localize the SAM on the contact interface, patterning is required.This was demonstrated by Lamping and colleagues by using microcontact chemistry [139].

Summary
In summary, this article provides an overview of organic CMOS circuits.Taking CMOS inverter as an example, we first revisit the performance parameters and then explain the operating principle, where possible strategies to improve the circuit performance is discussed.Next, we examine the CMOS circuits using two-dimensional semiconductors as well as new structures.Next, a review of the latest developments of organic CMOS circuits is provided.Finally, we focus on the challenges of organic devices in terms of contact engineering, and explore the ways to improve contact performance so as to enhance the performance of organic CMOS circuits.

Figure 5 .
Figure 5. Charge injected from metal into semiconductor by thermionic emission mechanism (left) or tunnelling (right).

Figure 6 .
Figure 6.(a) Five different PEDOT:PSS work functions and the band diagram of PTCDI-C8 with Al, LWF and HWF.(b) Output and transfer curves of OFET prepared by N-type PTCDI-C8 and low work function PEDOT:PSS electrode.(c) Channel-width normalized total resistance prepared by PTCDI-C8 versus the channel length (at Vg = 40 V).Reprinted with permission from [98].Copyright (2020) American Chemical Society.

Table 1 .
CMOS inverters fabricated with different semiconductors and their electrical parameters.