Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors

We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ~100 MHz in transmon frequency. In TSV-integrated substrates, Dolan junctions suffer most in both yield and disorder, making Manhattan junctions preferable. Manhattan junctions show pronounced conductance decrease from wafer centre to edge, which we qualitatively capture using a geometric model of spatially-dependent resist shadowing during junction electrode evaporation. Analysis of actual junction overlap areas using scanning electron micrographs supports the model, and further points to a remnant spatial dependence possibly due to contact resistance.


Introduction
Monolithic superconducting quantum processors (SQPs) have scaled to enable key demonstrations of quantum-computational advantage [1] and milestone demonstrations of quantum error correction [2,3,4] on the road to fault-tolerant quantum computing.Sustaining this scaling requires a multi-faceted fabrication approach simultaneously meeting yield, frequency, coherence, and coupling requirements of circuit elements, as well as the routing of control lines needed for gate and measurement operations.The latter motivates the active development of 3D integration strategies such as flipchip [5,6,7] to avoid overcrowding of circuit elements and vertical routing [8,9,10] of input and output lines to circumvent the scaling limitations associated with lateral wirebonding.Through-silicon visas (TSVs) are needed in some vertical routing approaches [11,12,13,14], and especially for suppression of resonance modes arising from the increased size of SQPs and their packaging.
TSVs further aggravate the targeting of superconducting qubit frequencies, which already bottlenecks the yield of operable devices even on planar substrates [15].Poor qubit frequency targeting is a primary cause of crosstalk induced by microwave drives [2] and can limit gate speeds.It also increases residual  coupling in processors with always-on qubit-qubit coupling [16,2,3], making gate fidelity and leakage dependent on the state of spectator qubits [17].Laser annealing of qubit Josephson junctions (JJs) [18,15,19,20,21] is an established method for selective qubit frequency trimming without intrinsic effect on qubit coherence.Currently, laser annealing allows a monotonic decrease with ∼ 300 MHz range and ∼ 15 MHz precision.To safely rely on laser annealing for post-fabrication trimming, fabrication itself must target qubit frequencies with a precision of ∼ 50 MHz.
The main limit to qubit frequency targeting is variability in the fabrication of Al-AlO x -Al JJs, which most commonly relies on double-angle shadow evaporation with intermediate in-situ oxidation.Two main variables affecting the Josephson coupling energy are the overlap area between the two Al electrodes and the tunnel barrier thickness.The two most popular JJ fabrication variants differ only in the shadowing mechanism: Dolan [22] JJs use a suspended resist bridge whereas Manhattan [23] junctions do not.Since Dolan JJs are more sensitive to resist-height variation by design, Manhattan junctions may be preferable particularly on substrates with TSVs that compromise the uniformity of spin-coated resist.On the other hand, recent reports by colleagues and us [24,25,26] indicate that geometric effects cause pronounced centreto-edge variation in Manhattan JJs, affecting their uniformity at wafer scale.
In this work, we present an experimental investigation comparing the uniformity of Dolan versus Manhattan JJs at both die-and wafer-scale on planar substrates with and without TSVs.We benchmark uniformity using room-temperature (RT) conductance () measurements, extracting the conductance coefficient of variation (CV) and residual standard deviation (RSD) of predicted transmon frequency.A wafer-centre-to-edge variation is again observed particularly in Manhattan junctions, which we attribute to a geometric shadowing effect during electrode evaporation.Scanning electron microscopy (SEM) of many junctions supports the model, and further points to remnant spatial dependence possibly due to contact resistance.Our findings indicate that for our current fabrication processes, Dolan JJs perform best for planar substrates, while the opposite holds for TSV-integrated substrates.We identify several paths for further required improvement.

Design of experiments
We investigate uniformity of Dolan and Manhattan JJs using six 100-mm diameter Si wafers.(Sections S1 and S2 of the Supplementary Information provide detailed descriptions of the fabrication processes used.)Three of these wafers, labelled Planar 17Q (quantity one) and TSV 17Q (quantity two), are used to obtain and compare metrics for both junction variants in fully planar substrates and TSV-integrated ones.Each wafer contains thousands of test structures, each consisting of two nominally identical JJs connecting in parallel to pre-fabricated NbTiN probing pads (200 nm thick, defined by sputtering and etching).These test structures mimic the two-junction transmon with NbTiN capacitor plates used in our standard SQPs (figure 1(a)).
In the Planar 17Q wafer, a 13 × 13 mm die-level layout mimicking our planar 17qubit SQP (Surface-17 [11,27,21]) is copy-pasted into two 2×4 arrays, the top (bottom) array with Dolan (Manhattan) test structures.At the location of each transmon of the SQP, we place a sub-array of 4 × 4 test structures.Within each sub-array (figure 1  the designed single-junction overlap area ( overlap ) is finely stepped within one of three ranges, labelled low (l), mid (m) and high (h), mimicking the choice of three qubitfrequency groups in our SQPs [11,16,27,21].For Dolan structures, we change  overlap by varying the width  t of the top electrode and keeping the width of the bottom electrode  b = 3 t .For Manhattan structures, we instead vary  b and fix  t = 160 nm.In total, the wafer contains 2176 test structures of each JJ variant.
Each TSV 17Q wafer contains test structures of only one JJ variant.In each wafer, the die-level layout (copy-pasted into one 2 × 4 array) has TSVs placed at the same locations as a variant of Surface-17 with TSVs (figure 1(b)).The density (∼ 1.7% area coverage) and position of TSVs is chosen to push the lowest-frequency spurious modes of the SQP in its sample holder to ≳ 15 GHz (as per finite-element simulation).At the location of each transmon in the SQP, we place a 5 × 5 sub-array of test structures.In this case, all sub-arrays are identical.Importantly, test structures overlapping with TSVs, although fabricated, are ignored and not included in conductance measurements.This yields at most 378 viable test structures per die and thus 3024 per wafer.
Three additional wafers, labelled Planar 35 × 35, are used to test the geometric resist-shadowing model and to investigate further sources of spatial non-uniformity in Manhattan JJs.Each wafer (figure 5) has a 35 × 35 array of nominally identical test structures ( b =  t = 200 nm).In the first wafer, like in the 17Q wafers, the test structures have symmetric JJ pairs with NbTiN probing pads.In the second, they have symmetric JJ pairs with TiN probing pads (160 nm thick, pre-defined by atomic layer deposition (ALD) and etching).In the third, they have single JJs with Al probing pads evaporated simultaneously with the JJ electrodes.

Measurements and analysis
All  measurements are acquired by the 2-point method using a home-built transimpedance amplifier.A low input voltage (10 mV) is applied across the junctions to minimize the possibility of causing failure to open or short circuit.Measurements on all planar wafers are performed using a manual probe station, with one exception noted below.During manual measurements, the intensity from a light-emitting diode source is set to the lowest possible visibility (< 500 lx) to minimize the parallel conductance contribution from the Si substrate to ∼ 5 μS.Measurements on the TSV 17Q wafers as well as on the Planar 35 × 35 TiN wafer are performed using a home-built automated probe station.The measured series resistance contribution from external cabling is < 10 Ω.The series resistance of NbTiN probing pads was found to vary from 200 Ω at wafer centre to 330 Ω at wafer edge by fabricating test structures with bays shortcircuited directly in the base layer.This variation is attributed to the radial dependence of the thickness of the sputtered NbTiN films (resistivity  = 100 μΩ-cm).
The range of  is 40−350 μS.Values < 20 μS and > 500 μS are filtered out as they mostly correspond to open and shorted junctions, respectively.To systematically detect and filter out data containing an open junction in a pair, a two-part linear regression analysis of conductance versus  overlap is implemented within each die in the Planar and TSV 17Q wafers.Values below 70% of the initial best fit are filtered out (figure S2  and S3).For the Planar 35 × 35 wafers containing nominally identical test structures throughout, conductance values below 70% of the mean are filtered out.
To quantify non-uniformity at both die and wafer scale, we use the conductance CV as a function of  overlap and the RSD of predicted qubit frequency.Die-(wafer-) level conductance CV is calculated using all the test structures with identical  overlap across the die (wafer) when calculating the mean   and standard deviation   .The spatial variation of junction conductance is visualized using heatmaps of conductance normalized by   of all test structures with identical  overlap .The predicted transmon qubit transition frequency ( 01 ) is calculated from  using where  C =  C /ℎ = 270 MHz is the designed transmon charging energy and  = 134 GHz/mS is an experimentally determined constant [28,29,30].Die-level frequency RSD is calculated from the residuals of the second fit.Wafer-level RSD is calculated similarly, but the residuals are obtained by performing a single fit on the combined filtered  data from all dies.
To test the geometric resist-shadowing model, SEM images of JJs from different coordinates on all Planar 35 × 35 wafers are acquired at 10 5 × magnification.SEM imaging is only performed after conductance measurements are completed.The actual deposited junction widths ( ′ b ,  ′ t ) and overlap area ( ′ overlap ) are extracted using home-made image analysis software (based on the OpenCV package) with the work flow presented in figure S7.The presence of other sources of spatial non-uniformity is evidenced from the spatial dependence of effective JJ conductivity calculated as /Σ ′ overlap .

Results
A total of 2176 (3024) test structures are fabricated per JJ variant for the Planar and TSV 17Q datasets.A zoomed-out view (figure 2) of the planar dataset shows that the spatial variation of normalized conductance for Dolan JJs is significantly lower than for Manhattan JJs.For the latter, there is a clear systematic decrease from centre to edge, making it unsurprising that the wafer-scale conductance CV is higher for Manhattan over all  overlap .The general decrease observed in the conductance CV with increasing  overlap is in line with previous works [31,32].At the die level, the spread of Dolan JJs is also lowest, with ∼ 100 MHz frequency RSD uniform across the wafer.For Manhattan JJs, the frequency RSD increases away from wafer centre, indicating that the spatial variation is relevant even at die level.Turning over to the TSV dataset (figure 3), we can again discern an underlying centre-to-edge dependence for Manhattan JJs.However, this trend is masked by a significant increase in disorder.The disorder is much stronger for Dolan JJs, evident both at wafer scale and die level.Interestingly, the CV for Dolan does not display any clear dependence on  overlap , suggesting that resist-height variations dominate the spread.Note that the CV and RSD for Dolan are calculated both with and without applying regression filters.This is necessary because the high disorder makes the regression filter unable to reject only defective junctions.Even with the artificial improvement of Dolan CV and RSD that may arise from removing nondefective junctions, a strong conclusion holds: with TSVs, Manhattan JJs systematically outperform Dolan JJs.Nonetheless, with > 300 MHz RSD at die level, even Manhattan JJs fall very short of frequency targeting objectives in the presence of TSVs.However, there is room for optimism as this investigation is best interpreted as a worst-case scenario for actual TSV-integrated SQPs.In our test, we place many junction pairs per transmon location of Surface-17.Therefore, in a real Surface-17, transmon JJ pairs would on average be farther away from TSVs.Furthermore, the footprint of TSVs could be further optimized following [12].

Summary of results
Conductance

Geometric resist-shadowing model
The essence of the geometric model is a spatial dependence of junction electrode widths arising from oblique incidence of the Al flux during evaporation.Specifically, the width of vertical electrodes (both electrodes for Dolan JJs, bottom electrode for Manhattan JJs) depends on the  coordinate, while that of horizontal electrodes (top electrode for Manhattan) depends on the  coordinate.Key parameters of the model are the thickness of the top resist  = 600 nm (which acts as the shadow mask), the wafer tilt  = 35 ∘ during Al evaporations, and the physical configuration of the electron-beam  (e-beam) evaporator (Plassys MEB550S).These last parameters include the distance  ′ = 650 mm between the crucible at ⃗  and the pivot point ⃗  ′ of the sample holder, and the distance  = 62.5 mm between ⃗  ′ and centre ⃗  of the exposed wafer surface (see schematic in figure 4(a)).This results in a distance  =  ′ cos () −  between ⃗  and the plane defined by this surface [33].In a cartesian coordinate system with origin at ⃗  and ⃗  = (, , 0) lying on this plane, ⃗  = (0,  ′ sin(), ).Evaporation under these conditions deposits electrodes extending along the  axis.An electrode of this orientation with  coordinate has actual width where  offset is a constant widening from over-exposure and development of the e-beam resist.Including these modifications to the width of both electrodes, the actual overlap area becomes We can further expand the model by approximating the contribution of sidewalls to  ′ overlap .The spatially-dependent actual bottom electrode thickness is where  b = 35 nm is the calibrated thickness at ⃗  under normal incidence ( = 0).Approximating the sidewalls as vertical, The modified spatial dependence is shown in figure 4(c).Note that we do not model the effect of shadowing by the bottom electrode during evaporation of the top electrode, which most likely reduces the overlap at the eastern sidewall (evident in figure S8).
Finally, we can model some predictable effects of the first evaporation (for the bottom electrode) on the top electrode.The first evaporation deposits an Al layer above the top resist, effectively increasing its height by ( ⃗ ) (also given by the righthand side of equation 3).More importantly, it also deposits a lip on the southern resist edge for the top electrode (see figure S1), with width  lip and height  lip : The shadowing effect of these features makes where  ′ ( ⃗ ) =  + ( ⃗ ) and  ′ lip ( ⃗ ) =  lip ( ⃗ ) + ( ⃗ ).Including all modelled effects leads to  ′ overlap ( ⃗ ) as shown in figure 4(d).
The geometric model predicts that junction conductivity erroneously computed as /Σ overlap will show a centre-to-edge decrease.Experimental results for the three Planar 35 × 35 wafers clearly show this trend (figures 5(g-i)).In turn, the model predicts that conductivity computed as /Σ ′ overlap will be flat.Due to the inaccuracy of approximating  ′ overlap using top-view SEM images, a slight centre-to-edge increase could even be observed.Conductivity computed as /Σ ′ overlap is very uniform for the all-Al wafer but not for the wafers with NbTiN and TiN probing pads, in which a strong centre-to-edge decrease persists.This suggests the possibility of a non-negligible series resistance from the small contact region (nominally 32.4 × 10 −2 μm 2 ) between each Al electrode and the NbTiN or TiN bays.These contact regions are also susceptible to spatial variation from the shadowing effect.It remains interesting for future work to increase the area of the contact region and to also add a bandaging layer post junction deposition [34,31] to test if conductivity computed as /Σ ′ overlap can flatten further.

Conclusions
Table 1 summarizes the findings of our investigation of Dolan and Manhattan JJs on planar and TSV-integrated substrates, spanning yield, conductance CV and frequency RSD at wafer level, as well as average die-level RSD.For planar substrates, Dolan JJs perform best in all categories.In TSV-integrated substrates, Dolan JJs show a marked increase in disorder and decrease in yield, most likely due to their higher susceptibility to resist-height variation.Manhattan JJs are thus the preferred choice for TSV-integrated substrates, but their uniformity must be further improved.First, we must pre-compensate the spatial variation of junction overlap area that arises from the shadowing effect captured by the geometric model.Next, the contribution of contact resistance between the Al electrodes and the NbTiN bays must be quantified and possibly diminished using bandaging layers.These improvements will allow to quantify the intrinsic disorder of Manhattan JJs and approach the ∼ 50 MHz target that will secure SQP yield by post-fabrication trimming using laser annealing.The average pixel value of the image is first calculated, then multiplied by a set range of thresholds between 1.0 and 2.0 to detect the edge.The top electrode is filled first to reduce pixel noise before detecting the edges of the bottom electrode.By summing the pixels row (column) wise above the threshold, the centre row (column) corresponding to the edge is obtained.The actual width  ′ t ( ′ b ) is calculated from the mean of the non-zero distance between the edges for each threshold.The defined range of thresholds is used to filter the image and obtain the best edge.The overlap area  ′ overlap is obtained by summing the pixels between the outer row edges of  ′ t over the inner column edges of  ′ b . (b)),

Figure 1 :
Figure 1: (a) Schematic and SEM images at two length scales of the test structures used to investigate uniformity of Dolan versus Manhattan JJ pairs on planar and TSVintegrated wafers.Two junctions in each structure complete a loop with a pre-fabricated NbTiN base.Probing pads in the base allow measuring the parallel conductance of the junction pair.(b) Die-level planar layout with 17, 4 × 4 sub-arrays of junction test structures.Each array is centred at the location of one transmon in our planar Surface-17 SQP.Each array has a sweep of junction overlap area  overlap in one of three ranges (labelled l, m and h).(c) Die-level TSV layout arranged as 17, 5 × 5 sub-arrays of junction test structures.Each array is centred at the location of one transmon in our TSV-integrated Surface-17.One such array is highlighted by the white dotted line.Each array has an identical sweep of  overlap .Test structures that overlap with vias (black circles) are ignored and not included in measurements, yielding at most 378 test structures per die.Heatmaps in (b) and (c) indicate the chosen  overlap for each test structure.

Figure 2 :
Figure 2: (a) Wafer-scale mean-normalized conductance heatmap of Dolan (top) and Manhattan (bottom) JJ test structures on the Planar 17Q wafer.The origin (0, 0) indicates wafer centre.Blank cells correspond to test structures identified as defective by the filtering.For this dataset, both JJ types are fabricated on a single wafer.(b) Wafer-scale conductance CV for both junction types as a function of  overlap .(c)Dielevel RSD of predicted qubit frequency as a function of distance () between die and wafer centres.

Figure 3 :
Figure 3: (a) Wafer-scale mean-normalized conductance heatmap of Dolan (top) and Manhattan (bottom) JJ test structures on TSV-integrated 17Q wafers.For this dataset, two separate wafers are fabricated, one for each JJ type.The origin (0, 0) indicates wafer centre.Blank cells correspond to defective junctions removed by filtering outliers at die level.Cells marked with black circles indicate TSV locations.(b) Wafer-scale conductance CV for unfiltered (nf) and regression-filtered (f) Dolan JJ pairs and for filtered Manhattan JJ pairs as a function of  overlap .(c) Die-level RSD of predicted qubit frequency as a function of distance () between die and wafer centres.

Figure 4 :
Figure 4: (a) Schematic of e-beam Al evaporation setup (not drawn to scale).Please see text for further details and parameter values.The illustration shows the decrease in junction electrode width from centre to edge of wafer arising from the spatiallydependent shadowing effect.(b) Wafer-scale mean-normalized conductance computed from actual junction overlap area  ′ overlap as per equation 2, for Manhattan JJs with  t =  b = 200 nm and  offset = 25 nm.(c) Same as (b) but adding the overlap contribution from sidewalls as per equation 4. (d) Same as (c) but adding effects of the first evaporation (of the bottom electrode) on the second evaporation (of the top electrode) (equations 5 to 7).

Figure 5 :
Figure 5: Wafer-scale mean-normalized conductance heatmap of 35 × 35 array of Manhattan JJ test structures fabricated on three planar wafers with the variants indicated by the top schematics.(a,b) Symmetric junction pairs with (a) NbTiN probing pads deposited by sputtering and (b) TiN probing pads deposited by ALD.The black dotted line indicates the diagonal along which the JJ pairs are imaged for figure S8.(c) Single junctions with simultaneously fabricated Al probing pads.The hatched rows indicate accidentally omitted junctions during data acquisition.(d-f) Distribution of actual junction overlap area  ′ overlap as a function of junction radial position ().The black curves are the best fits of the simplest geometric model (equation 2 with single free parameter  offset ).(g-i) Effective junction conductivity (computed from designed and actual overlap areas) as a function of .The dashed (solid) curves are quadratic fits of  overlap ( ′ overlap ).

Figure 4 (
Figure 4(b) shows the spatial dependence of  ′ overlap for Manhattan JJs with  b =  t = 200 nm and  offset = 25 nm on a 100-mm diameter wafer.

Figure S1 :Figure S2 :Figure S3 :
Figure S1: Cross-sectional SEM image of the resist stack of Manhattan JJs, with added false colour to highlight different materials.The cut shown corresponds to the horizontal electrode of a Manhattan JJ near wafer centre.The wafer is cleaved after deposition and lift-off of 20 nm of Al for both bottom and top electrodes at  = 35 ∘ .The Al thickness is intentionally reduced to minimize buckling of the resist stack.This image is taken at 76 ∘ tilt, using low beam current (10 μA) and accelerating voltage (5 kV) to minimize distortion of the resist stack.The large undercut for the PMGI layer is created by the higher dissolution rate of PMGI during development using MF-321, which is based on tetramethyl ammonium hydroxide.

Figure S8 :
Figure S8: Compilation of a subset of SEM micrographs used to extract actual electrode widths and junction overlap areas for several of the Manhattan-junction pairs fabricated on the planar TiN wafer.The images are acquired from test pads positioned diagonally across the wafer shown by the black dotted line in figure 5(b).Images of junctions for a JJ pair are placed side by side.Each image is labelled with the coordinates of the JJ pair relative to wafer centre.

Table 1 :
Summary of metrics obtained for Dolan and Manhattan JJ test structures on all wafers used throughout this study.The die-level frequency RSD is the average across the eight dies in the 17Q wafers.
a Without regression filtering.b With regression filtering.c Two rows were accidentally omitted during data acquisition.