Fully solution-processed carbon nanotubes thin film transistors and PMOS inverters on glass substrate

We report fully solution-processed thin film transistors and PMOS inverters fabricated on glass substrates using single-walled carbon nanotubes (SWCNTs) as active semiconducting material. All the electrodes (gate, source, and drain) were inkjet-printed using silver (Ag) as conductive ink. Spin coated poly-4-vinylphenol dielectric was optimized in terms of thickness and heating conditions for solution-processed SWCNTs thin film transistors to achieve a mobility equal to 0.81 cm2 V−1s−1. We will show that, hole traps at the dielectric-semiconductor interface are responsible for the hysteresis in the transfer curve, and controlled by the different sweep rate of the gate field. Drain-current transients under different bias conditions were studied and the increase in current occurs due to slow polarizations of residual dipolar groups in the dielectric. The adopted technology has been exploited to fabricate a PMOS inverter and studied for high gain and noise margin values at the supply voltage, V DD = −40 V.


Introduction
Semiconducting single-wall carbon nanotubes (SWCNTs) have attracted great interest in the fabrication of low-cost thin-film transistors (TFTs) using fully solution-processed techniques because of their excellent electrical properties [1][2][3][4][5]. In spite of the excellent device performance, the hysteresis in these CNT based TFT devices create large instability in threshold voltage (V Th ) which disturbed the switching characteristics and prevent their large scale industrial commercialization [6][7][8][9]. Traps presented at the dielectric-semiconductor interface or in the bulk of the dielectric were mainly claimed for the hysteresis and responsible for the bias-stress effect as well as shift in V Th [10][11][12][13]. In addition to charge carrier trapping, the immaturely cured or ambient air annealed PVP dielectric has large number of residual OH dipolar groups in the bulk and causes the slow polarization effect which in turn the reason for increase in drain-current and hysteresis in the transfer characteristics [14][15][16][17]. Although the hysteresis was widely studied but the control mechanisms are not yet well understood in fully solution-processed TFT devices with polymer dielectric.
Among the various solution-processed techniques inkjet printing is the most promising technology because of its digital layout for the required pattern printing. Inkjet printing technique further reduces the fabrication cost due to mask less technology, non-contact, less material wastage over the entire substrate, and compatibility with glass or flexible substrates [18][19][20][21][22][23]. A combination of spin coating, drop cast and inkjet printing techniques can increase the throughput of the TFT device fabrication for circuit applications. Integration of these TFT devices for circuits such as PMOS (P-channel metal-oxide-semiconductor) inverters also have been gaining attention because of the ease of fabrication and their applications as a basic unit for the fabrication of logic gates, ring oscillators etc [24][25][26][27][28][29]. PMOS inverters suffer with the low voltage gain and shift in trip point due to traps in the TFT devices and lack of symmetry controlled by noise margin values.
In this paper, we studied the dielectricsemiconductor interface in fully solution-processed SWCNT based TFT devices and PMOS circuits using polymer dielectric. Inkjet-printed Ag electrodes were used for all the electrodes, and the spin coated PVP dielectric was optimized in terms of thickness, S Singh capacitance and leakage current-density. TFTs were characterized to achieve high mobility devices in which the anti-clock wise hysteresis was observed due to hole traps and controlled by the different gate voltage sweep rate. Steady-state and dynamic bias-stress effects were used to study the dielectricsemiconductor interface and slow polarization phenomena using drain-current transients. Positive V Th shift, and increases in drain-current with time occurs due to slow polarization in the PVP dielectric and control the interface hole trap kinetics. A depleted load PMOS inverter was fabricated and characterized for high gain value and symmetric noise margin. The PMOS trip point was controlled by the V Th of the TFTs which in turn responsible for the presence of hole traps.

Device fabrication
We have fabricated thin film transistors (TFTs) on 0.7 mm thick fused silica glass substrates using inkjetprinted Ag electrodes. In the first step, the glass substrates were cleaned with DI water, isopropyl alcohol, and acetone by keeping them inside an ultrasonic cleaner for 10 min each. The substrates were cleaned with nitrogen gun and dried on top of the hot plate at 140 • C for 10 min. Then a solution of 6 wt% poly-4-vinylphenol (PVP) and 3 wt% poly melamine-coformaldehyde as a cross-linking agent (CLA) in propylene glycol methyl ether acetate (PGMEA) as a solvent was magnetic stirrer for 6 h at room temperature and then filtered with 0.2 µm PTFE syringe filters. This filtered PVP solution was spin coated at 1000 rpm as a basement layer, and the film was annealed directly on top of the hot plate at 160 • C for 40 min. This step was important to achieve good pattern of printed Ag electrode on PVP surface. We used Ag-nanoparticle ink, containing 30-35 wt% Ag nanoparticles in triethylene glycol monomethyl ether solvent (Sigma Aldrich, CAS No. 736465-25 G) as a conductive ink. This Ag nanoparticle ink was inkjetprinted as gate electrodes. An inkjet printer (Dimatix DMP-2850, Fujifilm) was used with a drop spacing of 60 µm and a 10 pL cartridge. The substrate temperature was kept fix at 50 • C during the printing process and a single nozzle was used. After printing, the glass substrates were annealed at 120 • C for 30 min on the hot plate to obtain the sintered and conductive Ag electrodes. Next, a dielectric layer was deposited over these printed Ag electrodes. For this purpose, we used 10 wt% PVP and 5 wt% CLA in PGMEA as a solvent and spin coated at 1000 rpm. The film was annealed at 200 • C for 1 h directly on the hot plate in air to achieve the final dielectric thickness of 620 nm. After this step, source and drain Ag electrodes were inkjet-printed over PVP dielectric similar to the bottom gate electrodes. Finally, the commercially available semiconducting SWCNTs ink in toluene (IsoSol-S100, from NanoIntegris) with a concentration of 0.05 mg ml −1 was used as an active channel material and drop cast over the region between source and drain. The average diameter and length of the CNTs used are 1.4 nm and 1 µm, respectively. The drop cast process was done by using a micro pipette with drop volume 0.02 µl at 45 • C on top of the hot plate. After 5 min heating at 45 • C, all the substrates were annealed directly on the top of the hot plate in air at 200 • C for 30 min to remove the toluene solvent.

Device characterization
All the current-voltage (I-V) measurements for TFT and PMOS inverter were carried out using a semiconductor parameter analyzer (Keithley, 4200 A-SCS). Capacitance was measured at different frequencies using KEYSIGHT E4980A LCR Meter (20 Hz-2 MHz). All the layer thickness and roughness were measured using the Stylus profiler (Bruker, Dektak XT). Optical microscope images were captured using Leica Microsystems (LEICA DVM6).

Resistivity measurement for printed Ag electrodes
Silver (Ag) electrodes were inkjet-printed on glass substrates and characterized using I-V measurements and optical microscope images. The inset of figure 1(a) shows the optical microscope image of a single inkjet-printed Ag electrode with 4.5 mm length and 100 µm in width, connected with 1 mm × 1 mm pads. The thickness of the printed Ag electrode is 310 nm. We printed Ag line electrodes on different glass substrates and annealed at 100, 150, 200, and 250 • C for 2 h each. The I-V characteristics for all the samples in linear scale were plotted in figure 1(a) in the voltage range from −1 to 1 V. Resistance value was calculated from the slope of the I-V curve. The calculated resistivity vs temperature curve is shown in figure 1(b). Resistivity decreases linearly with temperature because the Ag nanoparticles get sintered at higher temperature and become more conductive.
The resistivity values changes from 19.1 to 5.5 µΩ cm when temperature increases from 100 to 250 • C, respectively.

PVP dielectric: device structure and optimizations
After the bottom electrode resistivity measurements, we characterized the polymer dielectric thin film in terms of thickness and leakage current-density. Figure 2(a) shows the schematic diagram for the metal-insulator-metal (MIM, Ag-PVP-Ag) sandwich structure used in this study. For thickness variation, we spin coated the dielectric solution (10 wt% PVP and 5 wt% CLA) at four different rpm i.e. 1000,  2000, 3000, and 4000 rpm respectively, and the corresponding thickness curve in log-log scale is shown in figure 2(b). The leakage current-density for the PVP dielectric (620 nm thick) was measured in the voltage range from −15 to 15 V and illustrated in figure 2(c). We achieved the leakage current-density ∼2 × 10 −7 A mm −2 at 10 V. This leakage current can be further reduced by the thickness control, and proper heating conditions (such as heating inside high vacuum chamber) of the spin coated PVP layer [30,31]. For 620 nm thick PVP dielectric the capacitance vs frequency curve (C-f characteristics) at 1 V dc bias is depicted in figure 2(d). We used the capacitance value 60.56 nF cm −2 at 100 Hz frequency S Singh  for TFT device parameter calculations as discussed in next section. At higher frequency, capacitance decreases because of the leakage current. In our previous research work, we also conclude that it is the increase of concentration of the polymer which is responsible for lower free volume (reduced leakage current) and hence a higher dielectric constant [30]. This is also reported that the dielectric constant varies with frequency and the cross-linked polymer was less affected to change in frequency due to better immunity against moisture [32,33].

Thin film transistors: hysteresis and transient measurements
Next, we move for a complete thin film transistor (TFT) device fabrication using the semiconducting SWCNT as active channel material. Figure 3(a) shows the schematic for the TFT device structure. The obtained TFT device parameters for V DS = −5 V were listed in table 1. The mobility in linear region was calculated using the following relation: where, L and W are the channel length and width respectively, and C i is the geometric capacitance for the PVP dielectric. We obtained the sub-threshold swing, SS = 6.5 V/decade confirm the good dielectricsemiconductor interface formation. The SS value was calculated from the equation: Equation (2) was used to calculate the trap density in TFT devices. Trap kinetics control the hysteresis in transfer characteristics. Hysteresis gives two different V Th values which disturb the switching characteristics for TFT devices. We calculate the interfacial trap density (N it ) in our CNT based solution-processed TFT devices using the following relation [34]: where k B is the Boltzmann constant, T is temperature, and q is the electron charge. Due to large hysteresis in transfer curve the N it density is one order larger as compared to literature values [12,35]. The calculated value is, N it = 3.1 × 10 13 cm −2 V −1 , also reported in the table 1. Figure 4 shows the effect of V GS sweep rate on the hysteresis control on transfer characteristics. The largest hysteresis was obtained for slow sweep rate at V GS = 0.1 V interval measurements. When the V GS sweep rate increases from 0.1 V to 0.5 V, the hysteresis decreases very fast. At high sweep rate (i.e. 0.5 V intervals), less number of holes get trapped at the dielectric-semiconductor interface and hence hysteresis decreases. The change in V Th for different hysteresis loops gives the trap carrier density using the relation N Trap = C i |∆V Th | q . The trapped charged concentration of the order of 1.4 × 10 12 cm −2 was obtained in previous research work [13] by using the similar PVP dielectric. The sweep rate is important to optimize for such solution-processed TFT devices to achieve low hysteresis. Again, at very high sweep rate some data points can be missed out.
Further, the hole trap signature and their respond with gate field was investigated and shown in figure 5. In figure 5(a), steady-state transfer characteristics for these printed SWCNT based TFT devices were repeated more than 25 times at 1 min interval. V Th shifted in positive direction indicates that number of holes in the channel increases after each |I D |-V GS measurement. In case of polymer dielectrics such as PVP, parylene, etc it is widely reported that slow polarization due to residual dipolar groups i.e. OH group, is responsible for drain-current increase as well as positive V Th shift [36,37]. We annealed the PVP film in ambient air environment on the hot plate. In literature, it is reported that with proper heating conditions of the PVP dielectric such drain-current instabilities can be reduced [14,38,39]. With gate field the dipoles oriented slowly and add more number of hole carriers in the channel. Due to more number of holes in the semiconducting channel, I D

PMOS inverter
A depleted load PMOS inverter was fabricated by connecting two high mobility SWCNTs based TFT devices for which the schematic circuit diagram was shown in figure 6(a). An input voltage (V IN ) was applied to the gate electrode of the driver TFT. The drain terminal of the driver TFT was connected to the source of the load TFT, and this common terminal was used for the measurement of the output voltage (V OUT ). Figure 6 from V DD /2 (−20 V) due to equal channel width (1500 µm), same V Th for both the driver and load TFTs as well as defects present in the TFT devices. The symmetry of the VTC of the PMOS inverter was determined by the noise margin. The noise margin value for the PMOS was calculated from the largest side of the square formed between VTC and its reverse mirror image curve [40]. We obtained 10% noise margin for these printed SWCNT based PMOS inverters. In such PMOS structures, the symmetry was controlled by the positive and negative values of the threshold voltage for both the TFTs used.

Conclusions
Inkjet-printed Ag electrodes were electrically characterized for which the resistivity varies from 19.1 to 5.5 µΩ cm when temperature increases from 100 to 250 • C, respectively. Spin coated PVP dielectric with thickness of 620 nm was optimized for fully solutionprocessed SWCNTs based thin film transistors to achieve high mobility of 0.81 cm 2 V −1 s −1 . Anticlockwise hysteresis in the transfer curve confirms the hole trapping at the dielectric-semiconductor interface, and controlled by sweeping the gate voltage at different intervals. Drain-current increases with time due to slow dipole orientation (slow polarization) in the PVP dielectric with gate field. A depleted load PMOS inverter was fabricated with the complete voltage swing from 0 to −40 V, gain value of 2.5 with 10% noise margin for the supply voltage, V DD = −40 V. The shift in trip point was controlled by the V Th or traps presented in TFT devices.

Data availability statement
The data that support the findings of this study are available upon reasonable request from the authors.