Electronic properties of ZrO2 films fabricated via atomic layer deposition on 4H-SiC and Si substrates

Being an important semiconductor material for high power applications, silicon carbide (SiC) faces the problems while used as a gate oxygen layer in traditional Si MOS devices. In view of this, an innovative approach was adopted in the present work to replace the conventional SiO2 with a high-k material (ZrO2) as the gate oxygen layer to investigate its effect on the electrical characteristics of the devices. In particular ZrO2 films were deposited on Si and SiC substrates by atomic layer deposition (ALD), and Al was used as the electrode. The atomic force microscopy (AFM) microregion scan revealed a highly flat surface with Rq < 1 nm after the ALD growth of ZrO2 layer. The sample surface analysis via x-ray photoelectron spectroscopy (XPS) suggested the presence of a small amount of ZrOx components. According to the electron energy loss spectrum (EELS), the band gap width (Eg) of this ALD ZrO2 dielectric was 5.45 eV, which met the requirements for high-quality 4H-SiC-related MOS devices. The electrical properties of the samples were then studied, and the maximum breakdown voltage of the Al/ZrO2/SiC/Al MOS structure was obtained to be 23 V, i.e., nearly twice that of the Si substrate. As for the oxide layer, the interface defect density (Dit) near the conduction band of the Al/ZrO2/SiC/Al MOS structure was only 1012 eV−1 cm−2 orders of magnitude. The Neff value (the movable charge) of the structure was also controlled at 1012 cm−2. Therefore, the overall performance of the ZrO2/SiC structure in terms of electrical properties exceeded that of the ZrO2/Si structure and previously reported counterparts. In this respect, the ZrO2/SiC MOS capacitor structure has great research potential.


Introduction
As one of the typical third-generation wide-band semiconductor materials, SiC-based power appliances are bound to gradually replace Si-based devices that require high-power, high-temperature and radiation-resistance characteristics.This is due to the development of high-quality substrates and process technologies, as well as the inherent performance advantages of 4H-SiC materials (wide band gap, high thermal conductivity, etc) [1].Compared with other third-generation wide-band semiconductors, SiC has the advantage of growing conventional high-quality SiO 2 films directly on the epitaxial surface.This process is the key point for the preparation of MOS structured power devices.Therefore, 4H-SiC MOS structured power appliances are among the SiC core electronic systems.Gate oxide with superior performance is a key element of the MOS composition structure [2].Silicon dioxide (SiO 2 ), which is the main material for gate oxides in standard MOS devices, is easy to grow and exhibits the outstanding performance [3].However, the relative permittivity of SiC is 2.5 times that of SiO 2 .This means that, according to Gauss's theorem, the SiO 2 layer needs to withstand the electric field which is 2.5 times that of the SiC material, and the stronger electric field enhances the tunneling effect of electrons, leading to greater leakage currents and breakdown risks [4,5].Therefore, in order to fully exploit the potential of SiC as a material for high-power and high-voltage applications, a high-k dielectric layer could theoretically be used [6,7].
Among the common high-k gate dielectric films, zirconium dioxide (ZrO 2 ) has a relatively high k value (k = 20-25) and is thus an attractive candidate material [8][9][10].There have been numerous studies on ZrO 2 combined with Si substrates [10][11][12][13][14][15][16][17][18][19].However, relatively few studies have been conducted to describe the electrical properties of zirconium dioxide (ZrO 2 ) deposited as a gate oxygen layer on SiC substrates.In order to thoroughly investigate the electrical properties, ZrO 2 films were applied onto Si and SiC (0 0 0 1) substrates by atomic layer deposition (ALD).The deposition quality of the oxide film was then characterized via atomic force microscopy (AFM).The I-V and C-V curves of MOS samples were also acquired by means of a semiconductor parameter analyzer, and the probe bench tests were conducted as well.The material properties and electrical characteristics of ZrO 2 as a gate oxygen layer on the SiC substrate were carefully analyzed in comparison with those of the Si substrate.

Experimental section
In this study, Al/ZrO 2 /Si/Al and Al/ZrO 2 /SiC/Al MOS capacitor structures were prepared via atomic layer deposition (ALD) of ZrO 2 films.The ALD ZrO 2 growth process chose TDMAZr and water as zirconium and oxygen precursor respectively.Before ALD ZrO 2 layer growth, the surface was cleaned using 5% HF solution.The potential oxidation layer of SiC substrate surface should be removed and Si-OH surface structure remained, but carbon clusters near the surface are hard to be removed.ALD process undergone at 270 ℃, without plasma enhancement.In a single ALD cycle, the zirconium precursors react with −OH on SiC surface, combines with the surface and produce dimethylamine.After argon flow purge removing reactant, water vapor react with TDMAZr on the surface and form ZrO 2 layer.A new self-limiting reaction cycle starts after Ar purge again.The film thicknesses on the SiC and Si substrates were 44 nm and 40.5 nm, respectively.Prior to the deposition of the aluminum electrode, the sample is inevitably exposed to air for a short period of time, resulting in a certain amount of CO 2 and H 2 O that should be adsorbed on the surface of the sample's ZrO 2 surface and the surface of the SiC layer and remain at the electrode interface.Subsequently, aluminum electrodes with 200 nm thicknesses and 200 × 200 μm 2 surface areas were deposited onto the ZrO 2 films by magnetron sputtering through a shadow mask, and the back electrodes of the samples were formed by re-evaporation of aluminum on the backsides of the contact electrodes (see figure 1).
The surface morphology of the sample films was examined via atomic force microscopy (AFM) imaging within the micro-areas with three different sizes, namely 10 μm × 10 μm, 5 μm × 5 μm and 1 μm × 1 μm, and the corresponding AFM images are shown in figure 2. Spectroscopic ellipsometry (SE) was applied to obtain the thickness of ALD ZrO 2 films.SE experiments were conducted with a fixed incidence angle of 70°and within the wavelength range of 300-1000 nm.The Cauchy model was applied for processing raw SE data, and the Levenberg-Marquardt algorithm (LMA) was applied to determine the film thickness.
The XPS tests were carried out using an ESCALAB 250Xi spectrometer equipped with a monochromatic Al Kα x-ray source operating at the power of 15 W (the photon energy hν was 1486.6 eV).The surface XPS scans were acquired on a raw 4H-SiC wafer slice and an ALD ZrO 2 surface.All the surface scan profiles were later calibrated using a C 1s peak position of 284.8 eV for the reference and fitted for detailed surface chemical state analysis.
The electrical characteristics of MOS capacitors were determined by measuring the quasi-static capacitancevoltage (C-V) curves and current-voltage (I-V) curves using a PC-controlled Keysight B1500 semiconductor analyzer and a Lakeshore cryogenic probe stage, respectively, at the frequencies of 1 kHz, 10 kHz, 100 kHz, and 1MHz.Based on the I-V data, the leakage current densities and breakdown voltage of the samples were analyzed [20].The C-V data were collected at the frequencies mentioned before.The interface defect densities (D it ) and the movable charge densities (N eff ) of the oxide layers of the samples were then calculated and analyzed [21].

Results and discussion
According to the AFM images, the substrate had a good surface flatness and a uniform height distribution, which indicated its high surface quality.Using the 10 μm × 10 μm AFM images for average roughness calculations, it was found that the roughness of the SiC surface was R q was less than 0.2 nm, while that of the ALD-deposited ZrO 2 surface was below 1.5 nm.This result implied that after the ALD deposition of the 39-nm-thick ZrO 2 film onto the substrate, the heterostructure surface remained relatively flat.The undulation of the ZrO 2 surface was basically kept within 8 nm, and the material distribution within the scanned zones was also fairly uniform.This indicated that the surface morphology of the ZrO 2 sample after ALD deposition was sufficiently high.The SE analysis suggested that the film thicknesses (t ox ) of ZrO 2 /SiC samples were about nm, while those of ZrO 2 /Si specimens were nearby 40.5 nm.The refractive index (n) and extinction coefficient (k) were also measured through the SE experiments, as shown in figure 3(b).
The XPS tests were performed on the surfaces of both the raw SiC substrate and the ZrO 2 film.The survey XPS scan(a), O 1s spectra(cd), core level spectra(ef), and EELS(b) spectra of ALD ZrO 2 are shown in figure 4, respectively.In the O 1s spectrum of 4H-SiC, a small single peak can be observed at the binding energy of 531.98 eV.Additionally, in the Si 2p spectrum of SiC, tiny flat peaks of Si-O 2p 3/2 (100.94eV) and 2p 1/2 (101.56 eV) states can be distinguished by fitting, together with the main Si-C 2p peaks [22].This indicated that the surface of the SiC substrate was slightly oxidized, so that there was a low fraction of Si atoms bonding to exotic oxygen, forming a trace amount of the SiO x component.Surface oxygen presumably come from short time air exposure of sample before XPS experiments.The EELS spectrum of ZrO 2 film was generated based on the O 1s XPS signal.The interception of the linear fit plot and the baseline corresponded to the band gap of the ZrO 2 sample [23], which was found to be Eg(ZrO 2 ) = 5.45 eV.To produce a 4H-SiC-based MOS with ideal band offset width that ensures gate reliability, this as-deposited ALD ZrO 2 layer merely fulfilled the band gap width requirement for gate dielectric materials [24].
Related peak signals of Zr-O (530.01 eV, ZrO 2 component) and Zr-OH (531.94 eV) bonds are significant according to peak fitting analysis of the ZrO 2 O 1s spectra.The ALD procedure whereby the oxygen precursor H 2 O involving into the deposition reaction contributed to the existence of Zr-OH-related peaks.Since the removal of hydrogen at the reactive surface was incomplete, existence of oxhydryl remnants is predictable.The Zr 3d XPS scan revealed two pairs of zirconium components, including those related to 3d 5/2 and 3d 3/2 states of ZrO 2 and ZrO x (0 < x < 2) and suggesting the under-stoichiometric composition of the ZrO 2 film.This meant that during the ALD procedure, the ZrO 2 growth was under a relatively low O content condition [25].The lack of oxygen atoms in ZrO 2 led to the emergence of intrinsic oxygen vacancies.Since the reliability and trench mobility of MOS devices deeply rely on the quality of gate dielectric, the existence of intrinsic and interfacial defects of gate oxide, including oxygen vacancies, will have great negative effects on SiC MOS performance.As such, the ALD cycle should be conducted at a certain concentration of oxygen to make the ZrO 2 layer stoichiometric.
Figure 5 depicts the I-V experimental curves of the samples, where the electrode area is normalized with respect to the current.It is noteworthy that the breakdown voltage of various device configurations in the current-voltage curve analysis is one of the essential electrical parameters.Once the gate voltage increases, the measured voltage can be considered the breakdown voltage at which the current density rises sharply (by several orders of magnitude).This voltage corresponds to an electric field that causes a permanent breakdown of the oxide [25].In accordance with the experimental results in figure 5, the sample with a high-k insulating layer, i.e., the Al/ZrO 2 /Si/Al (SiC MOS) structure, had the larger breakdown voltage of 25.9V relative to that of the Al/ZrO 2 /SiC/Al (Si MOS) structure, with a leakage current of 1 × 10 −8 A/cm under a zero gate voltage.Although the ZrO 2 /SiC MOS structure achieves relatively high breakdown voltages (V B = 23V) [26][27][28], the application of ZrO 2 as a High-k material on its own as a gate oxygen layer is somewhat unsatisfactory when compared to the performance of conventional SiO 2 applications on Si as well as SiC substrates [29].This may be due to the low valence band offset of ZrO 2 (ΔE V = 0.52 eV) [8,30].
Figure 6 depicts the C-V data collected on the Al/ZrO 2 /SiC/Al sample at the frequencies of 1 kHz to 1 MHz.The frequency-dependent behavior of the Al/ZrO 2 /SiC/Al structure revealed the dynamic trapping and detrapping of active sites throughout the measurement.As shown in the figure, the C-V curve recorded at 1 kHz rapidly reached a lower capacitance with the increase in the positive bias.Conversely, the C-V plot at the high frequency (1 MHz) decreased slowly in the region of accumulation with a positive bias.Once the measurement frequency increased, the rising slope of the C-V curve decreased.A similar situation was also observed in the most composite substrate devices with elevated dielectric coefficients [31].Because of the high dielectric constant, the band gap of ZrO 2 is relatively narrow, leading to a marginal band offset between ZrO 2 and SiC.As a result, the interface trap can easily migrate with SiC, thus the accumulation region in the C-V curve is mainly determined by the interface trap.Some scholars affirm that oxygen vacancies are most probable to induce the energy gap, which will result in the emergence of interface defects as well as leakage currents in the gate structure.It has also been assumed that a part of oxygen vacancies generates interface traps [32].In this study, the direct growth of the ZrO 2 layer on the SiC substrate caused the scattering of the capacitance-voltage characteristic of the whole structure.
Figure 7 displays the forward and reverse C-V scans of the high-frequency voltage.Because the boundary trap is not able to respond to the change of AC small signal during the high frequency C-V test, it can be charged and discharged with the grid voltage DC scan.Therefore, when the grid voltage is scanned from inversion to accumulation and from accumulation to inversion respectively during the test process, hysteresis occurs between the two high-frequency C-V curves due to the presence of boundary trap charges.The hysteresis of the  Based on these data, it was proved that the samples with a ZrO 2 /SiC structure had the better interfacial quality.
In this work, the capacitance-voltage characteristics at high and low frequencies were acquired to determine the interface defect densities D it .The abundant interface traps can impair the effective modulation of the Fermi level and even cause the pinning phenomenon, which impedes the carrier transport in the channel and the fabrication of MOSFETs with desirable subthreshold slopes and drive currents [9].Interface defects introduce some defect-related energy levels within the semiconductor band gap that can trap carriers, and the external electric field can modulate the Fermi level E F up and down.As a result, there is a charge change at the position    where the defective energy level is occupied by carriers to cancel the external electric field felt by the normal energy level.However, the response to the change in the occupied state of the defective energy level is slow and cannot be maintained under the external electric field varying in the high-frequency range.According to this principle, the difference in the C-V curves due to the charge variation at high and low frequencies can reveal the corresponding interface trap density.The interfacial defect density of the MOS capacitor with a ZrO 2 /SiC structure was accordingly derived, as shown in figure 8. Near the conduction band, the interfacial defect density Dit was 9.5 × 10 12 eV −1 cm −2 , which exceeded the corresponding value for ZrO 2 applied onto the SiC substrate.The interfacial defect density at the mid-gap of the ZrO 2 /Si MOS capacitor structure was 2.7 × 10 13 eV −1 cm −2 , which was superior to that of the ZrO 2 /SiC MOS configuration.Therefore, the interface characteristics of ZrO 2 /SiC specimen were considerably improved according to the interfacial defect density (D it ) and the removable charge of the oxide layer (N eff ).

Conclusions
This study reported the electrical and structural properties of ZrO 2 layers produced via atomic layer deposition (ALD) on 4H-SiC and Si substrates as potential gate dielectrics for power MOSFET devices.The preliminary AFM and XPS data revealed the uniform deposition and high quality of ALD-produced ZrO 2 films on the 4H-SiC surfaces.Moreover, the difference between the band gap widths of ALD ZrO 2 and 4H-SiC was slightly larger than 2 eV.Meanwhile, though the ZrO 2 layer basically met the band gap width requirements for reliable gate heterojunctions, achieving a satisfactory band offset in the ZrO 2 /4H-SiC heterojunction is still an issue to be solved.Besides that, the ALD procedure needs a higher concentration of oxygen to obtain a stoichiometric ZrO 2 layer and reduce the potential intrinsic and interfacial oxygen vacancy concentrations.The interfacial quality of the Al/ZrO 2 /SiC/Al MOS structure was enhanced according to the lower interfacial defect density and fewer movable charges relative to the conventional structure.In addition, the breakdown voltage of the Al/ZrO 2 /SiC/Al samples was close to 25 V.Although the application of ZrO 2 as a separate oxide layer in MOS capacitor structures is still deficient in terms of breakdown voltage and leakage current, it is possible to use ZrO 2 as an oxide layer in MOS capacitor structures.These experimental results can still be used as a reference for the subsequent application of ZrO 2 as gate oxygen layer in MOS structures, and help to expand its application prospect in wide-band gap semiconductors.

Figure 3 .
Figure 3. SE results on ZrO 2 /4H-SiC samples: (a) phase difference Δ and amplitude Ψ of the measured complex reflectance; (b) refractive index and extinction coefficient.
high frequency C-V curve will bring a difference in the flat-band voltage, through which the boundary trap density can be obtained.According to the hysteresis flat-band voltage ( V FB ∆ ) obtained from the plots and the equation N the movable charge Neff of the insulating layer was further estimated.The calculated Neff values for ZrO 2 /Si and ZrO 2 /SiC were 2.63 × 10 13 cm −2 and 4.73 × 10 12 cm −2 , respectively.

Figure 5 .
Figure 5. I-V characteristics of ZrO 2 /Si and ZrO 2 /SiC MOS samples at room temperature.

Figure 7 .
Figure 7. Room-temperature C-V plots of the Al/ZrO 2 /SiC/Al and Al/ZrO 2 /Si/Al structures.The arrows indicate the voltage scanning direction.