Study of ultra-thin CdTe/CdS heterostructure solar cell purveying open-circuit voltage ∼1.2 V

Analysis of Microelectronic and Photonic Structures – One Dimensional (AMPS-1D) is a very general and versatile computer program to analyze device physics and device design. This simulation tool can be utilized to teach how material properties e.g., bandgap, doping, mobility, gap state defect distribution etc and device design together control device physics and thereby device response to light, voltage, and temperature. AMPS-1D numerically solves the three governing semiconductor device equations: Poisson equation, free electron continuity equation, and free hole continuity equation. It was originally created by Prof. Stephen J. Fonash and his team at the Centre for Nanotechnology Education and Utilization of the Pennsylvania State University, USA [10]. In this work Beta version 1.0 of AMPS-1D simulation package has been utilized to simulate the CdTe TFSC.

Table 1 provides the information for the p-type CdTe active absorber and n-type CdS window layers that were put in the Density of States (DOS) modelling approach of the simulator editor. Values for those parameters are collected from [1–3].

Table 1.  p-CdTe and n-CdS layer parameters for simulation.

AMPS symbol	Parameter	n-CdS	p-CdTe	Unit
EPS	Relative permittivity at cell temperature T, ε	9	9.4	—
MUN	Mobility of electron at T, μn	350	500	cm3/V-s
MUP	Mobility of hole at T, μp	65	60	cm2/V-s
NA	Acceptor impurities concentration, NA	0	1E10-3E16	cm−3
ND	Donor impurities concentration, ND	1E10-2E18	0	cm−3
EG	Mobility band gap at T, ${E}_{g}$	2.42	1.45	eV
NC	Effective DOS at conduction band edge ${E}_{C}$ at T, ${N}_{C}$	2.4E18	9.08E17	cm−3
NV	Effective DOS at valence band edge ${E}_{V}$ at T, ${N}_{V}$	1.79E19	6.3E18	cm−3
CHI	Electron affinity at T, χ	4.5	4.28	eV
—	Layer thickness, D	15–100	100–1800	nm

In AMPS-1D, two boundary conditions namely, PHIBO $({{\rm{\Phi }}}_{b0})$ and PHIBL $({{\rm{\Phi }}}_{bL})$ must be provided for performing the simulation task respectively for the Cathode (n-type TCO front contact) and Anode (metallic back contact). PHIBO/PHIBL in eV refers to the work function (WF), Φ_m of front/back metal contact layer minus electron affinity (χ) of semiconductor in contact. Choosing these two parameters eases in selecting the degree of ohmicity at any contact i.e., the quality of semiconductor contacts [10]. Ideal and non-ideal ohmic, or Schottky contact can be made in view of that. In this work, ATO was taken as n-type TCO front contact with assumed surface WF of 4.5 eV [14]. Since the CdS layer has an electron affinity of 4.5 eV [2], PHIBO becomes 0 eV for ATO which was kept constant during entire simulation. Varieties of metals were taken into consideration for simulation to act for the purpose of metallic back contact as shown in figure 2. Values for their corresponding work functions (Φ_m) were assigned from [21]. Thus we have a range of values for ${{\rm{\Phi }}}_{bL}$ as pictured in figure 2. For instance, Platinum with WF of 5.93 eV [21] at (111) plane has a barrier height ${{\rm{\Phi }}}_{bL}$ of 1.65 eV since the adjacent layer of CdTe material has the electron affinity of 4.28 eV [2].

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For entire simulation, the surface recombination speed at both contact layers for both electrons (SNO, SNL) and holes (SPO, SPL) was kept fixed at $1\times {10}^{7}{{\rm{cms}}}^{-1}$ corresponding approximately to the thermal velocity of the electrons, implying that the entire carrier will recombine if they can reach surface.

A surface through which light passes has to be treated so that it reflects minimally. TCO layer attached to the cell can act as the electrical contact to collect charges. The reflection coefficient of front (RF) TCO contact was set to 0.05 (5% reflection, 95% absorption) with a view to reflect the experimental spectral response data of the cell with ATO layer while the reflection coefficient of back (RB) metallic contact was set to 0.95 in order to get the energetic photons reflected back from the back surface. Magnesium Fluoride $\left({{\rm{MgF}}}_{2}\right)$ has higher potential for acting as the ARC layer coated on the glass substrate compared to other ARC coating materials. Textured TCO surface can increase the absorption probability of incident light.

When the modelled device is considered under illumination in AMPS-1D as in our case, a list of parameters is requisite for AM 1.5 illumination spectrum. CdTe having optical band gap energy of 1.45 eV is almost ideal for PV energy conversion and because of its high optical absorption coefficient (α) of ∼${10}^{5}\,{{\rm{cm}}}^{-1},$ all incident photons with energy (hυ) above CdTe optical band gap energy $({E}_{opt})$ are absorbed within its thin layer of 1-3 μm. Values for absorption coefficients for both p and n layers at a range of wavelengths of visible light at AM 1.5 have been assigned for simulation from [22].

Simulation process was started with 1 μm CdTe absorber, and 50 nm CdS window layers at cell operating temperature, T of $298^\circ \,{\rm{K}}\,.$ All other parameters were as mentioned in section 2. Figure 3 shows the thermodynamic energy band diagram (EBD) for CdTe/CdS cell in case of ${{\rm{\Phi }}}_{bL}$ of 0.72 eV and 1.65 eV for Iridium (Ir) – (210) plane with WF of 5 eV, and Platinum (Pt) – (111) plane with WF of 5.93 eV, respectively. Positions, x = 0, and x = L refers to the left- and right-hand side of the modelled device structure, respectively. Barrier height ${{\rm{\Phi }}}_{bL}$ can be rewritten mathematically in more general terms as follows [10],

$$\begin{eqnarray*}&&{{\rm{\Phi }}}_{bL}={E}_{C}-{E}_{F}\left[{\rm{at}}\,{\rm{position}}\,{\rm{x}}={\rm{Li}}.{\rm{e}}.,{\rm{CdTe}}/{\rm{Back}}\,{\rm{metal}}\,{\rm{interface}}\right]\end{eqnarray*}$$

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Effect of increasing ${{\rm{\Phi }}}_{bL}$ on band bending is illustrated in the band diagram for the conduction and valence band edge, E_C, E_V respectively. Schottky barrier is formed in the CdTe/metal interface at x = L position. With lower ${{\rm{\Phi }}}_{bL}$ (0.72 eV) separation between E_V and Fermi-level, E_F is much larger compared to that with higher ${{\rm{\Phi }}}_{bL}$ (1.65 eV). In other words, E_V goes away from E_F at x = L interface for lower ${{\rm{\Phi }}}_{bL}$ whereas, it gets closer to E_F at the same interface (figure 3). Increased ${{\rm{\Phi }}}_{bL}$ eases the majority carrier transport from the semiconducting CdTe material to the back metal. This eventually improves quantum efficiency (QE), and thus to increase power conversion efficiency. Lower ${{\rm{\Phi }}}_{bL}$ is responsible for lowering shunt resistance (R_sh) along with high reverse current, reducing the fill factor to a very low value. Thus all we need is to increase the ${{\rm{\Phi }}}_{bL}$ as possible as we can. The analogous effect of ${{\rm{\Phi }}}_{bL}$ on J-V characteristics, QE, and photovoltaic output parameters are demonstrated in figures 4, 5, and 6, respectively.

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In conventional CdTe solar cell, value for V_OC ranges typically from 800 mV to 850 mV [19]. Using nanocrystalline CdS window layer, V_OC of 1017 mV has been achieved [19]. When PHIBL = 0.72 eV for Ir (210-plane) metal, voltage goes to a maximum at open circuit voltage, V_OC of ∼660 mV. From PHIBL of 0.72 eV to 1.65 eV, short circuit current density, J_SC increases from 24.6 mA cm⁻² to a maximum of 28.6 mA cm⁻². However, voltage is dominated mainly by PHIBL. V_OC increases rapidly with increasing PHIBL as shown in figures 4 and 5. Although the J_SC is found same at 28.6 mA cm⁻² for Pt with either (110) or (111) plane, V_OC is different. Highest obtained V_OC was 1193 mV (∼1.2 V) for Pt back metal at (111) plane. This result shows the possibility of having voltages > 1V without any back surface field (BSF) layer if one incorporates Pt (111) as back metallic contact in CdTe solar cell. Metal Pt can be utilized industrially for higher performances in a large scale production since Pt has lower price compared to usually used Au back metal. This design will lead towards a simple CdTe solar cell structure with high voltages than previously obtained.

Approximately 90% QE can be achieved (figure 5) in most portions of the wavelength range for PHIBL > 1.42 eV i.e., metal WF > 5.7 eV. For 520 nm to 760 nm wavelength range, QE can be as high as 94.8% with Pt back metal at either (110), or (111) plane. Figure 6 reflects the photovoltaic performances with respect to varying PHIBL. It is evident from figure 6 that all output improves with increasing PHIBL i.e., back metals with higher surface work function (Φ_m). Cell efficiency increases almost linearly with increasing PHIBL. Highest fill factor (FF) and J_SC were attained for Platinum (Pt) metal at either (110) or (111) plane. Only Iridium (Ir) at (111) plane can compete the performances gained with Pt metal to some extent. To sum up, Platinum (Pt) at (111) plane has been opted to be used in back metal of our structure which is kept fixed for the subsequent simulation. This can be an optimistic solution for achieving V_OC beyond 1 V in single junction CdTe based solar cells.

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Under STC at cell operating temperature, T of $298^\circ \,{\rm{K}}\,\,$with 20 nm thick n-type CdS window layer and all other parameters being constant, figures 7 and 8 show the results obtained from AMPS-1D when the thickness of the p-type CdTe absorber layer was varied from 0.1 μm (100 nm) to 1.8 μm (1800 nm).

Each incremental thickness of CdTe absorber layer has a tendency of absorbing light. The thicker the absorber, the more prone light will be imbibed into the absorber, and more electron-hole pair to be generated. Figure 7 discloses that the short circuit current density $({J}_{sc})\,\,$increases sharply from 17.13 mA cm⁻² to 27.109 mA cm⁻² till 700 nm. Then it becomes almost stable in between 27.3 mA cm⁻² and 27.8 mA cm⁻² till 1800 nm. Open circuit voltage $({V}_{oc})\,\,$increases very slowly from 1.181 V to 1.193 V with increasing CdTe layer thickness till 600 nm. Beyond 1100 nm, it remains constant at 1.194 V.

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From figure 8, it is found that greater the thickness of the p-type CdTe layer, higher is the efficiency of the solar cell. Cell efficiency (η) increases rapidly from less than 18% to greater than 29% till 800 nm of the p-type CdTe layer. Then a slight negligible increment is noticed in the efficiency. If we go on increasing the thickness of the CdTe layer from 800 nm to 1800 nm, the efficiency will increase from 29.091% to 29.685%, implying an increase of only 0.594% efficiency by an addition of 1000 nm thick layer. But the cost will increase swiftly because of the two times thickness increment which is very insignificant compared to the level to which the efficiency is increased. Fill factor raises till 400 nm, then becomes constant at a percentage of 89.3. We determined the effect of CdTe thickness on cell performance, presenting that cell opto-electrical performance improves gradually from 0.8 μm to 1.8 μm of CdTe layer.

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Finally as a trade-off between cost and performance, 800 nm thick CdTe layer is approved for proposed cell structure which is over hundred times thinner than conventional bulk Silicon wafer based solar cell and two to three times thinner than conventional CdTe TFSC.

Under STC at $298^\circ \,{\rm{K}}$ with 800 nm thick p-type CdTe absorber layer and all other parameters being constant, figures 9 and 10 demonstrate the results obtained from AMPS-1D when the thickness of the n-type CdS window layer was varied from 15 nm to 100 nm. It is evident from figure 9 that ${J}_{sc}\,$and ${V}_{oc}$ decreases insignificantly from 27.53 mA cm⁻² to 27.518 mA cm⁻² and from 1.193 V to 1.192 V respectively with increasing CdS layer thickness from 15 nm to 100 nm. Thus we can surely state that CdS layer thickness has almost no effect on these two parameters or these optical outputs have a little sensitivity to degradation with increasing CdS layer thickness.

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In a superstrate CdTe/CdS solar cell, thicker CdS window film causes larger attenuation for photons that need to be absorbed by the active absorber layer. It was shown that negligible photo-generated current is contributed by the CdS layer. CdS thus constitutes a photocurrent loss for the wavelength (λ) ranging from 300–520 nm in spite of having a high optical absorption coefficient of over ${10}^{5}\,{{\rm{cm}}}^{-1}$over this range of λ [23]. The poor photo-response results in lowering hole lifetime and higher recombination rate. Thus, parasitic optical absorption in the CdS layer is the prime photocurrent loss, making it compulsory to lessen the CdS window layer thickness in the CdTe/CdS hetero-junction as far as possible. Figure 10 explicates that increasing the thickness of the CdS layer from 15 nm to 100 nm, η decreases from 29.385% to 28.791%. Increasing CdS thickness has also a negative impact on FF. It decreases from 89.4% to 87.7%. Hence we must chose CdS thickness as less as possible for the window layer.

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Bearing in mind the fabrication difficulties and short circuit effect, 50 nm thick CdS is chosen to act as the n-type heterogeneous partner for 800 nm thick p-type CdTe material.

Under STC with 800 nm thick CdTe and 50 nm thick CdS layers and all other parameters being constant, figures 11 and 12 illustrate the findings obtained from AMPS-1D simulation when the acceptor ion impurities concentration, ${N}_{A}$ in CdTe layer was varied from $1\times {10}^{10}\,{{\rm{cm}}}^{-3}$ to $3\times {10}^{16}\,{{\rm{cm}}}^{-3}.$ Figure 11 shows the effect of ${N}_{A}$ on the short circuit current density $\left({J}_{sc}\right)$ which increases with the increase of ${N}_{A}.$ The open circuit voltage $\left({V}_{oc}\right)$ was fixed at 1.193 V over the range simulated. Figure 12 shows that cell efficiency (η) increases beyond ${N}_{A}$ of $1\times {10}^{15}\,{{\rm{cm}}}^{-3}.$ Reverse saturation current decreases with increasing doping concentration leading to an increase in the cell conversion efficiency. Higher the doping concentration, more the growth time and deposition cost. Higher concentration of acceptor impurities in CdTe will reduce the density of minorities (electrons in this case). Thus it is sufficient to take $1\times {10}^{16}\,{{\rm{cm}}}^{-3}$ for ${N}_{A}$ to improve efficiency.

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Under STC with 800 nm thick CdTe and 50 nm thick CdS layers and all other parameters being constant, figures 13 and 14 illustrate the findings obtained from AMPS-1D simulation when the donor ion impurities Conc. (${N}_{D}$) was varied from $1\times {10}^{10}\,{{\rm{cm}}}^{-3}$ to $2\times {10}^{18}\,{{\rm{cm}}}^{-3}.$ Figure 13 shows the effect of ${N}_{D}$ on ${J}_{sc}$ which tends to go down with increasing ${N}_{D}.$ The open circuit voltage $\left({V}_{oc}\right)$ was fixed at 1.193 V over the range of ${N}_{D}$ simulated. Figure 14 exhibits that η decreases beyond ${N}_{D}$ of $1\times {10}^{17}\,{{\rm{cm}}}^{-3}.$ Higher the doping concentration, more the deposition time and production cost. We investigated from both figures that all the opto-electrical output parameters remain almost constant till ${N}_{D}$ of $1\times {10}^{17}\,{{\rm{cm}}}^{-3}.$ Hence $1\times {10}^{10}\,{{\rm{cm}}}^{-3}$ for ${N}_{D}$ can be opted for CdS layer in the solar cell.

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Solar cell performance degrades from the reference points at the non-optimal operating temperatures. These cells work greatest at certain optimum temperature. All the thin film solar cells lose some percentages of their conversion efficiency with increasing operating temperature. For instance, at normal terrestrial temperatures of $25\,^\circ {\rm{C}},$ silicon's efficiency compares satisfactorily with other materials; but at a high temperature of $200\,^\circ {\rm{C}},$ silicon's efficiency has dropped to 5% [24]. We determined the effect of cell operating temperature, T on cell performance, showing that cell opto-electrical performance (${V}_{oc},$ η, and FF) degrades gradually with increasing temperature, except for the short circuit current $\left({J}_{sc}\right)$ which was found to be almost constant. Heat is nothing but the trembling of atoms and molecules on atomic and molecular level. For any solar cell working at a higher temperature implies that the atoms are vibrating quicker, so it's harder for the electron to get out without bumping into these atoms.

When cell operating temperature increases, thermal energy increases accordingly. The lattice vibrations obstruct the route of the free passage of charge carriers, thus the junction begins to lose its power to keep the charges apart. As a result, cell efficiency goes down due to the collision with thermally excited atoms. With 800 nm thick CdTe and 50 nm thick CdS cell at STC, cell efficiency, η was found to be 29.33% with ${J}_{sc}$ of 27.53 mA cm⁻², ${V}_{oc}$ of 1.193 V, and FF of 89.3%. When the solar cell is heated, open circuit voltage decreases faster than the short circuit current increases, resulting reduction in overall efficiency. Decreasing cell efficiency with increasing temperature of figure 15 explores a negative temperature coefficient of $0.04824/^\circ {\rm{K}}$ which reveals the value of a highly stabilized solar cell.

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The current density versus circuit voltage (J-V) characteristic curves of the proposed CdTe solar cell is displayed in figure 16. Under STC, values for the key optoelectrical output parameters of the cell such as short circuit current density $\left({J}_{sc}\right),$ open circuit voltage $\left({V}_{oc}\right),$ fill factor (FF) and cell power conversion efficiency (η) have also been provided in figure 16. With only 800 nm thick CdTe active absorber layer, our proposed structure promises better quality device than the conventional ones.

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