Effect of physical parameters on the drain characteristics of Double gate MOSFET incorporating Quantum Mechanical Effects

Scaling of bulk MOSFETs in nanometre regime has several disadvantages. The electrical behaviour of the devices doesn’t show the anticipated characteristics if scaling is done beyond certain point. But in order to have smaller devices with higher density on chips, it is necessary to avoid short channel effects (SCE) which lead to unexpected electrical features. One of the methods to avoid SCE is to have multi-gate architecture of MOSFET. This paper investigates the behaviour of double-gate MOSFETs with respect to the variation of their physical dimensions. The analyses have been done taking into notice the quantum mechanical effects due to dimensions in nanometre scale. The results obtained highlight how subthreshold and above threshold regions are impacted due to the various physical quantities that have been varied.


Introduction
By reducing the dimensions of MOSFETs, more number of components can be incorporated on a VLSI [1, 2] chip to have diversified applications. Adjusting short-channel effects (SCE) is the major issue during scaling down of conventional MOSFETs. There are several ways through which SCE can be lessened while reducing the dimensions of a device. There are many prominent techniques to overcome these shortcomings. Use of strain as reported in [3][4][5] alleviates SCE and boosts electrical integrity. Similar advantages have been found through the use of junctionless transistors [6][7][8].Use of multiple gates has been reported in [9][10][11][12]. The core theme of all these methods is to enable gate electric field to be more dominant in the channel region. Proper lithographic techniques are used to enable these methods. In multi-gate MOSFETs, there is more than one gate and all gates are maintained at the same potential through the application of gate voltage. The role of gate is to govern the electrons in the channel. Due to multi-gate, the channel electrons are better controlled [13] and exhibit superior properties than single gate transistors. In this work the electrical behaviour of Double-Gate (DG) MOSFET as shown in figure 1 has been examined by varying the physical parameters of the device. The subthreshold characteristics denote the region of MOSFET operation when gate voltage is smaller than the required turn-on voltage. Subthreshold region determines the power consumption of the device when it is supposedly in off state. In the nanometre range, the energy levels redistribute and it impacts the threshold voltage of the given device. In our calculations we have taken into this consideration which is known as quantum mechanical effect (QM) [14].

Theoretical details
The potential in the channel and its charges are related through the Poisson expression written as d 2 /dx 2 = (q/ si )n i e (-V)q/kT where  is the potential in the channel, q is charge,  si is the silicon permittivity, n i is the doping concentration, V is the quasi-Fermi potential, and kT/q is the thermal potential. The solution of this equation can be found using boundary conditions [15]   The drain current expression is given as [16] 0 ( ) The current in the linear, saturation and subthreshold regions are given as [15] , 2 2 ds ds Lin ox g t ds where  is the mobility, C ox gate oxide capacitance, W is channel width, L is channel length, V g is applied gate voltage, V ds is drain to source applied voltage and threshold voltage V t is expressed as [15]  

Results and Discussion
The calculation results are presented in Fig. 2-7. The channel length used is 1m and oxide thickness as 1.5 nm for all calculations otherwise it has been stated.   2 shows the variations of current with respect to applied gate voltage for different gate oxide thickness. The oxide thickness has been varied from 1.5 nm to 4.5 nm. The effect of oxide thickness variation is negligible in subthreshold region while it considerably affects the above threshold region. In Fig. 3, silicon channel thickness has been changed to get the current variation. Here t si affects subthreshold characteristics more than above threshold and it is as per the observations in [15]. The channel thickness near 5 nm contributes more to the elevation in threshold voltage arising due to QM effect. The effect of change of channel width on the drain current is shown in Fig. 4. Current increases with width W. In this case, W has relatively more effect on above threshold area. Drain current can be increased by increasing W, but then it increases the size of the device.  By changing the metal work function, desired threshold voltage can be obtained and accordingly the drain current is also affected. It can be observed from figure 6 that metal work function affects both But one of the disadvantages is that smaller metal work function increases subthreshold current and hence the leakage current. Leakage current must be kept at minimum level. From this graph the optimum value of metal work function can be inferred. The effect of mobility on current can be visualized from Fig. 7. Mobility shows more impact in the above threshold area. Therefore techniques that increase mobility may be incorporated in DG MOSFETs to increase drain current.

Conclusion
In this work the sensitivity of drain current of DG MOSFET for device dimension changes have been explored. It may be concluded that constraints exist for the selection of proper parameter so as to get maximum current and minimum dimension. Subthreshold current determines the off-state of the device and therefore it should be as low as possible. In the on-state, i.e., when the gate voltage is greater than the threshold voltage, larger current is expected. Selection of metal gate work function also plays very important role in the optimum performance of the device. As a future work, the effect of variation of channel length would be explored.

References
[1] Thota M and Gunda M 2018 Design of low power and area efficient 64 bits Shift Register using pulsed latches Advances in Computational Sciences and Technology 11 pp 555-60