Design of Dual Priority Persistent CSMA Protocol Based on FPGA

In order to study the MAC layer protocol in the wireless sensor network under the actual channel condition, the field programmable gate array (FPGA) hardware circuit is used to provide a dual-priority implementation scheme for the persistence carrier sense multiple access (CSMA) protocol. According to the characteristics of each node in the network, analyzes the system throughput and energy consumption, and the FPGA is used to overcome the shortcomings of the existing implementation scheme and the article combines the actual application, changes the single channel mode, and realizes the dual channel data transmission. Finally, the simulation tests the correctness of the design.


Introduction
CSMA(Carrier Sense Multiple Access) is an important random multiple access protocol, which effectively enhances the efficiency of data transmission, and CSMA is widely used in wireless sensor networks and wireless networks. In the communication system accessed by the protocol, each information station adjusts its own information transmission rhythm according to the channel state that is heard, thereby improving node transmission efficiency and system performance.
For the research of CSMA protocol, Literature [1,2,3] drawing plot of the theoretical formula by using Matlab, we can verify the theoretical results by the research method only, and does not reflect the principle of protocol control and real-time data transmission in the experimental process. The development of embedded technology provides a good technical support for the implementation of MAC protocol. In the literature [4][5][6], an implementation scheme based on FPGA to implement CSMA protocol is proposed. Although it can show the information packet transmission process, it only relying on the circuit design, Poisson source is not generated, and the circuit structure is complex, the experimental parameters should not be changed, so the statistical value of the simulation result is quite different from the theoretical value. Based on this, the paper uses Matlab and Quartus software to successfully introduce Poisson data stream into the circuit. The hardware description language Verilog HDL and schematic diagram are combined to build a simple and clear circuit. Design a dual priority data transmission system. The simulation results verify the correctness of the circuit design from the aspects of throughput and node energy consumption, and provide useful reference for the theoretical research and implementation of communication protocol.

Model of Protocol
Persistence CSMA protocol principle: The network node needs to monitor the channel before transmitting the data, and monitors the channel to have data transmission and continuously monitors; otherwise, it detects that the channel has no data to send and immediately sends the data.   Figure 2 shows system model of the dual-priority persistence load balancing. There are two channels in the system and there are two priorities. Priority 1 to Priority 2 are priorities from low to high, among these priorities, each priority node can have multiple access users. The channels occupied by different priority nodes are different. If the priority of the node is 2, the node occupies channel 1 and channel 2. The priority is "y" node's arrival rate on channel "x": ( ) 2 ≤ y y λ , the channel utilization rate is , considering the load balancing of the system, the utilization of each channel The same is:

Analysis of system throughput
Before analyzing the random multiple access protocol dual priority persistence CSMA, make the following rules for the system: The mode of channel access is dual-priority stick-type CSMA, and the information packet arrival process on channel "x" satisfies the Poisson distribution ( ) 2 ≤ x with independent parameterλx. The protocol is analyzed by using the time slot method. The length corresponding to the idle state is "a", and the length corresponding to the data transmission is "1+a" (the value is an integer multiple of a). The information packet that is collided or abandoned will be retransmitted at a later time, and the retransmitted packet has no effect on the arrival process of the channel.
According to the law of Poisson distribution, the average length " ( ) 2 U E " of the successfully transmitted event " 2 U " in channel 2 is first solved: For channel 2 of the dual-priority stick-type CSMA control protocol, only the information packets of priority 2 are transmitted, and the successful packet transmission is divided into the following two cases: One information packet arrives in the last time slot of the idle period, and is sent immediately in the next time slot. The average number of time slots of the event is: In summary, the system total throughput expression of the dual-priority stick-type CSMA is:

Analysis of node power
Before analyzing the node power, first make the following assumptions about the power of the nodes in the wireless sensor network under different states: The power required by the node to transmit data is " s P "; the power required when the node is in the channel detection state is: " l P "; when the node receives data, the required consumption is" r P ". Specific analysis of dual-priority adherence CSMA: First, assume that the total number of nodes in the system is "M". Only one of the "M" nodes has only one packet arriving in the idle time slot and decides to transmit. The system power can be calculated as: Therefore, the power required for the channel to be in the transmit state during each averaging period is: When no node in the system decides to send a packet in the idle time slot a, when all nodes are in the channel detection state, the power of the system is: " l MP ", so the power required for the channel to be idle in each averaging period is: Combined with the previous analysis, the power of the system when the packet sent by the node collides in each averaging period is: Therefore, in each averaging period, the power of the overall system is:

Design of system modular
According to the design characteristics of FPGA top-down [7][8] , the implementation of dual-priority stick-type CSMA protocol requires modular design.  Figure 3. Circuit architecture diagram Figure 3 shows the system circuit architecture. According to the protocol principle, the circuit is composed of a data storage module, a source processing module, a selective reading module, a channel multiplexing control module, and a throughput detecting module.

Data storage module
According to the previous analysis of the dual-priority CSMA model, it is known that the information packet arrival on the channel satisfies the Poisson distribution with independent parameter λ. [9] , but it can not generate a Poisson distribution of data streams with IP core or module in the Quartus II. The pPoisson data stream is generated here using Matlab software.  Figure 4 is a circuit diagram of the data storage module. Firstly, the Poisson data with the arrival rate of λ, 5000 rows and 1 column is generated by the Poisson function poissrnd (λ, 5000, l) in Matlab software, and saved as a file(.mif) format. Then, the data stream under the file (.mif) is stored by the kernel ram module in Quartus, and the stored Poisson data stream is generated to generate the planned information packet data. Eventually introduces Poisson data into the hardware circuit.

Source processing module
The idle event slot length is a in the dual-priority stick-type CSMA protocol analysis, and the slot length when the information packet is sent is "1+a", which is an integer multiple of "a". But the idle event has the same slot length as the busy event in the data stream of the initial source, and there is no multiple relationship, so the initial source data needs to be processed.  Figure 5 is a source processing module, which is composed of an asynchronous FIFO [10] and a feedback counter. The asynchronous FIFO realizes read and write control of the site information flow according to the feedback data. The feedback counter not only has a monitoring function, but also has a slot length control function. Since the asynchronous FIFO read enable changes from valid to invalid, the output information will retain the last read value. According to this characteristic, when the feedback counter detects that the initial station information stream data is busy data, it immediately gives a low level signal to the read enable, and the pause time of the read enable is controlled by changing the counter value, which is the time slot length of the busy event. Finally we realize the controllable function of the length of the different state slots. Figure 6. Source processing module simulation timing diagram Figure 6 is a timing simulation diagram of a time slot length control module, and "do1" represents a real-time data transmission situation of a certain station, where the time slot length of the idle data "0" has an integer multiple relationship with the non-idle data "6", "7", which is designed with the original intention matched.

Channel multiplexing control module
The data streams are processed by the source processing module becomes two priorities. Priority 2 is divided into two parts (priority 2_1 and priority 2_2), where priority 2_2 is transmitted separately on channel 2, and priority 2_1 competes with priority 1 for one channel, so it is necessary to solve the channel multiplexing problem. In order to implement the competition mechanism of the persistent CSMA, the real-time situation of the priority 2_1 and the priority 1 is classified and controlled, and (0, 6, 7) and (1,8,9) respectively represent the priority 1 and the priority 2_1. (I, U, B) three states. When there is no data in both priorities, channel 1 is idle; when one of the two priorities is single data and the other is no data, channel 1 is in the successful transmission state. Channel 1 is conflict on the remaining real-time conditions, which reflects the control strategy of the persistent CSMA protocol on the multiplexed channel.

Selecting the reading module
Priority 2_2 is transmitted separately on channel 2, and there are two states in the channel: the channel is idle, the channel is busy (the joint event of success and collision); therefore, in order to achieve information packet competition in circuit design, information sites are divided into free sites and busy sites. The data of the two sites are from two Poisson data streams in Matlab, and the arrival rates are 1 λ , 2 λ , and . Such a Poisson data site with arrival rate O λ is generated. The information packet processing module selectively reads the information data of the idle or busy station according to the real-time data (I, U, B) on the channel bus, so that the system completes the function of the listening channel and realizes the mechanism of protocol control on the single-channel persistent CSMA.

Throughput detection module
The throughput detection module implements the function of correctly reading the information of the corresponding station.  Figure 7. Throughput detection module Figure 7 shows the throughput detection module. Since the channel utilization cannot be 100%, the module needs to filter the idle data. The function of the filter is that it compare whether the data on the channel is the same as the free data type. If it is different, the data enters the FIFO. If it is the same, it Equation (13) is the throughput statistics method. Where "t t " is the total duration of the simulation, "N U " is the number of successful time slots for data transmission in the circuit simulation, and "T BU " is the length of the time slot in the busy state of the channel. This time slot length is the length of an information packet transmission in the algorithm protocol ("TP"), the theoretical value is "1+a", and the success time slot length is "1", so the length of the calculation success state should be multiplied by a + 1 1 .

Simulation test
The simulation experiment is mainly for testing throughput and node power in dual-priority stick-type CSMA. The value calculated from the theoretical expression of the research protocol derived in Section 2 is the test criterion. The arrival rate λ value of the source can be adjusted by the Poisson function in Matlab. The numerical relationship of different time slots can be adjusted in the counter program of the source processing module. The experimental simulation parameter settings are shown in table 1.   relative error of the node average power value of 42.16mw and the theoretical value of 42.31mw is calculated to be relatively small, which indicates that the system design is reasonable.

Statistical analysis
Under the same working conditions, by taking multiple statistics of different simulation durations, according to the number of information slots, which are successfully sent, calculate the throughput statistics " S "on system channel 1 using equation (13), then calculate the statistical value " P " of the average power of the system node according to the power analysis. In table 2, the statistical value and the theoretical value are very close, as the working statistical duration increases, the statistical value gradually converges to the theoretical value, which is consistent with the theoretical reality.

Conclusion
According to the working characteristics of the nodes in the wireless sensor network, this paper uses FPGA to design the circuit of the dual-priority stick-type CSMA protocol. This circuit not only combines Matlab and Quartus software, but also introduces Poisson data stream into the circuit. At the same time, according to the characteristics of communication protocol algorithm, its working principle is mapped into the circuit system, which shows the double priority data transmission process. After experimental simulation test, under the set simulation conditions, the simulation values of the system's throughput rate and node average power are consistent with the theoretical values, which confirms the accuracy and rationality of the design. FPGA is a kind of hardware performance, FPGA realizes the communication protocol algorithm and can realize the real node transmission process on the hardware parallel circuit. It is a process from theory to practice. It is helpful for us to improve understanding of the theory of communication protocol algorithm.