Effect of Loss Distributions on the Balance of Capacitor Voltages in MMC Using Full Bridge Sub-Modules

With the development of power electronics technology, modular multilevel converter (MMC) has become a popular converter due to its high modularity and good output characteristics. In recent years, half-bridge MMC has been widely studied. Compared with half-bridge MMC, MMC using full bridge sub-modules is more competitive because of its excellent DC short-circuit fault ride-through capability. Furthermore, the balance of capacitor voltages of sub-modules has a crucial influence on the working performance of MMC. To figure out the influence of non-ideal factors on the balance of capacitor voltages, this paper analyses the difference of the capacitor voltages and compares the unbalanced degree of capacitor voltages under different conditions. Firstly, in an ideal situation, the analytical expressions of bridge arm current and capacitor voltage increments are obtained, revealing the dynamic balance process of capacitor voltages. Secondly, expressions in a non-ideal condition reveal the effect of on-resistances of switching devices on the capacitor voltages. Finally, the influence of loss distributions in sub-modules on the balance of the capacitor voltages is analysed theoretically. Simulation models are built in PLECS to verify the theoretical analysis.


Introduction
With the improvement of modern transmission and distribution networks, HVDC (High Voltage Direct Current Transmission) has gradually become a powerful complement to AC transmission and is widely used worldwide. In the field of DC transmission, flexible DC transmission is rapidly developed due to its independent adjustment of active and reactive power and the ability to supply power to passive networks, etc. [1]. And MMC is very suitable for the application of flexible DC transmission because of its high modularity, good waveform quality, fault tolerance capability and many other advantages.
Right now, most of the existing MMC projects use MMC with half bridge sub-modules (HBSMs). Although it has the advantages of simple structure and low cost, when a short-circuit fault occurs on the DC side, the converter will change into an uncontrolled rectifier bridge due to some freewheeling diodes in the converter. Even if turning off all the switching devices to make the converter locked, the short-circuit current will still feed current to the short-circuit point through the freewheeling diodes, resulting in the inability to extinguish the arc. If the short-circuit current cannot be quickly cut off in a  2 short time, the freewheeling diodes will be damaged by overcurrent, and the safety and stability of the system will be seriously affected.
In MMC using full bridge sub-modules (FBSMs), Each SM can output positive, negative, and zero levels. When a short-circuit fault occurs on the DC side, the switches in sub-modules are all turned off. Regardless of the direction of the short-circuit current, it flows through the capacitors in sub-modules, and the voltages of these capacitors provide back-electromotive forces. Because of the reverse interruption capability, freewheeling diodes can force the fault current to drop to zero or minimum rapidly, thus guaranteeing the rapid recovery of the system [2]. Due to this characteristic, the fullbridge MMC has gradually gained more and more attention.
In an MMC system, inserting in different numbers of SMs results in different levels of bridge arm voltages, which in turn produce varying AC side voltages and bridge arm currents. And capacitances in SMs will be charged or discharged according to the working states of corresponding SMs and bridge arm current, which will cause the capacitor voltages gradually become different, resulting in the imbalance of capacitor voltages. And the unbalanced degree will be more serious without control, which may cause excessive stress on some devices and thus affect the safety and reliability of the system.
At present, most full-bridge MMC adopts a similar operation mode as the half-bridge MMC. That is, the switching devices of one of the bridge arms in the FBSM are respectively in a constant conduction or constant off state, and on the other bridge arm switching devices are alternately turned on, thereby the FBSM output a positive level or a zero level. In this mode, there are great differences in the loss and temperature of switching devices [3], which will affect the bridge arm current and the balance of capacitor voltages. In paper [4], the loss distribution in a FBSM is studied, and the redundant switching states of FBSMs are used to optimize the loss distribution inside the sub-module. However, the influence of switches' on-resistances on the balance of capacitor voltages almost no literature involved. Therefore, this paper first analyzes the difference of capacitor voltages under ideal conditions and non-ideal conditions through an analytical method, and reveals the influence of the onresistances of switches. Basing on these analyses, the PLECS software is used to establish the simulation models.

A traditional operation mode of the FBSM
A FBSM can output three kinds of levels: positive, zero, and negative levels. In normal operation, a FBSM usually operates as similar as a HBSM, in which only two states are used to output positive or zero levels, inserted or bypassed. As shown in Fig. 1, S 3 on the right arm of the FBSM is always off, correspondingly S 4 is always on, while S 1 and S 2 on the left arm are alternately turned on to realize positive and zero outputs [5]. For the convenience of discussion, this paper defines this operation mode as the traditional operation mode.
The left arm The right arm The left arm The right arm The left arm The right arm The left arm The right arm

The difference of capacitor voltages in SMs under an ideal condition
The difference of the capacitor voltages of SMs indicates the unbalanced degree of the capacitor voltages in MMC. In this section, the variation of capacitor voltage U C in a SM and the difference of U C of adjacent SMs in one switching period T s are derived by an analytical method. To simplify the analysis, only the upper arm is discussed. When a SM is inserted, the bridge arm current i p flows  3 through the capacitor in the SM and charges or discharges it, thereby changing its voltage. Therefore, to analyze the variation of U C , the bridge arm current i p must be first analyzed [6].
The single-phase topology of MMC is shown in Fig. 2. The upper and lower arms are respectively composed of N SMs and an inductance. In a full-bridge MMC, each SM is a full bridge converter which can output +U C (inserted) and 0 (bypassed) in the traditional operation mode. In an ideal case, ignoring the on-resistances and other non-ideal parameters, the relationship of DCside voltage U dc /2, output voltage u s , and voltage of the inductance can be expressed according to the Kirchhoff's voltage law: Using the carrier phase-shifted PWM (CPS-PWM) modulation strategy, when the carrier frequency ratio (the ratio of the carrier frequency to the modulation wave frequency) is large, the output voltage u s can be approximated as a constant U s in a switching period T s . For ease of analysis, small changes of capacitor voltages during one switching cycle are ignored, capacitor voltages remain at the initial value U dc /N. Therefore, equation (1) can be expressed as equation (2), where n is the number of inserted SMs.
During one switching cycle T s , n alternates between N k (N k =1,2,3) and N k -1, and the bridge arm current i p changes accordingly, as shown in Fig. 3. To analyze the change of i p , T s is divided into N segments, and the time of each segment is T i =T s /N (i=1, 2, …, N). In Secti, the time when n is equal to N k and N k-1 is T i-and T i+ , respectively, and the change rates of i p are K i-and Ki+ [7], respectively.  It can be seen from equation (2) that, in an ideal case, the change rates of i p in T i-and T i+ are constant, respectively expressed by: Assuming at the start time of Secti t 0_i , i p is I p0_i , then i pi-in T i-and i pi+ in T i+ can be expressed as: And the expression of the voltage increment of the capacitor in SM i is: Therefore, the capacitor voltage increments in T i-and T i+ are respectively expressed by: In a switching cycle T s , the inserted time of each SM on the upper arm is the same, which can be expresses as (N k -1) *T i +T i-. Taking N k =1 as an example, the inserted time of each SM is T i-. It is assumed that SM i starts to be inserted from t 0_i , i p is greater than 0. At the time t 0_i +T i-, SM i is bypassed and the capacitor stops charging. Therefore, the increment of U Ci in one T s can be obtained by: The SM i+1 starts to be inserted at t 0_ i+1 , the voltage increment of its capacitor in a T s is: And the value of i p at the time t 0_ i+1 can be calculated as: Then the difference of capacitor voltages of SM i+1 and SM i in one switching cycle can be obtained as: Obviously, C onst in the formula (14) is a constant. Similarly, in the case of N k =2, 3, ..., N, there is: It can be seen from formula (15), under the ideal condition, although the capacitor voltages are different in each switching cycle, the difference values of their increments are the same. And the difference can be positive or negative, so the capacitor voltages can reach the same value at a certain point. Therefore, in the ideal case, the capacitor voltages are dynamically balanced. The trend is shown in Fig. 4.

The difference of capacitor voltages in SMs under a non-ideal condition
In a non-ideal case, due to the presence of the on-resistances of the switches, according to Kirchhoff's law, the KVL equation of the upper-arm loop becomes: The sum of R i is the sum of the on-resistances of switching devices which the bridge arm current flows through. In different time periods T i-and T i+ , the bridge arm current flows through different switching devices, so the sum of on-resistances is different. It can be seen from (16) that the change rate of i p is no longer a constant due to the sum of the R i . The expression of i p can be obtained by solving the differential equation (16): Therefore, i p-and i p+ during T i-and T i+ can be obtained respectively by: Among (20) and (21): Different SMs have the same constant A and B, but different initial bridge arm current I p0_i . Taking N k =1 as an example, supposing that SM i starts to be inserted at t 0_i , SM i+1 starts to be inserted at t 0_i+1 , and i p is greater than 0.
In the T i-period, the voltage increments of capacitors in SM i and SM i+1 can be obtained respectively by: Therefore, the difference of the capacitor voltage increments of adjacent SMs is: It can be seen from (26) that, in the non-ideal situation, the difference of the capacitor voltage increments of SM i and SM i+1 in a switching period is related to I p0_i which is the value of i p at the time t 0_i . As different SMs are inserted at different time, the bridge arm current I p0_i is different. Therefore, in the non-ideal case, due to the existence of the on-resistances of switching devices, the difference of the capacitor voltage increments of adjacent SMs in a switching cycle is no longer a constant. Capacitor voltages cannot reach the same value at a certain point, and the original dynamic balance process of the system is broken, as shown in Fig. 5.

Influence of loss distribution in SMs on unbalanced degree of capacitor voltages
It can be seen from the above analysis that in the non-ideal case, the presence of the on-resistances of switches will destroy the dynamic balance process, and the magnitude of the on-resistances is related to the difference of the capacitor voltage increments of adjacent SMs. The greater the sum of the onresistances is, the larger the capacitor voltage difference of adjacent SMs will be. In conclusion, the on-resistances affect the unbalanced degree of capacitor voltages.
When the full-bridge MMC works in the traditional operation mode, since there are constant-on and constant-off switching devices in SMs, the losses of the switches in a SM are different [8], so the temperature changes of them are not the same [9], which is inconvenient for the design of the heat dissipation system. In addition, the on-resistances change as the temperature changes, which in turn affect the difference of capacitor voltages.
To optimize the loss distribution in SMs and make the temperature of each switching device closer, another operation mode is proposed. That is, all the switching devices working at the alternating conduction state [10] . For the convenience of discussion, this paper defines this mode as the full operation mode. CPS-PWM is used as shown in Fig. 6.
To clarify the temperature increment of each switch under different operation modes, a thermal model is built in the PLECS software for observation as shown in Fig. g. Fig. h and Fig. i shows the temperature simulation results of the switches in the traditional operation mode and full operation mode, respectively. In the traditional operation mode, the temperature of S 2 is the highest, the temperature of the S 4 and S 1 is close, and S 3 maintains the initial temperature due to its constant-off working state. In the full operation mode, the temperature of each switch is relatively close, which reduces the degree of uneven heating inside SMs to a certain extent.  The temperature variation will change the on-resistances of switching devices. In the traditional operation mode, S 2 is severely heated, so its on-resistance is bigger than others. Therefore, the fewer the number of SMs being inserted, the larger the sum of on-resistances and the capacitor voltage difference of adjacent SMs are, which is unfavorable for the balance of the capacitor voltages.
However, in the full operation mode, the loss distribution in SMs is relatively uniform, the temperature of each switching device is similar, so the difference of on-resistances is small, which can be considered as same as the on-resistance of S 4 in the traditional operation mode. Therefore, the sum of the on-resistances is smaller than that in the traditional operation mode, and the change of the number of inserted SMs does not cause a significant effect on the sum of the on-resistances.
To observe the influence of the loss distribution in SMs on the unbalanced degree of capacitor voltages, a single-phase full-bridge MMC simulation model was built in the PLECS software. The variance of capacitor voltages is used as an indicator to judge the unbalanced degree of capacitor voltages. The larger the variance, the higher the unbalanced degree.
The simulation parameters are shown in the Table 1: The simulation results are shown in Fig. 8 below. It can be seen from Fig. 8 that, in the ideal condition, the variance of capacitor voltages fluctuates around 0, which means the capacitor voltages remain dynamically balanced. In the non-ideal case, due to the existence of on-resistances of switching devices, the variance of capacitor voltages shows an upward trend, and the dynamic balance of the capacitor voltages is broken. By comparing the waveforms in Fig. 8, the unbalanced degree of capacitor voltages in the traditional operation mode is greater than that in the full operation mode. In other words, the uneven loss distribution in SMs leads to an increasement of the unbalanced degree of capacitor voltages, which verified the correctness of theoretical analysis.

Conclusion
Starting from the traditional operation mode of full bridge MMC, this paper analyzes the difference of the capacitor voltages under the ideal condition and the non-ideal condition, respectively, and explains the influence of the on-resistances of switches on the unbalanced degree of capacitor voltages. Basing on these analyses, simulation models are built in PLECS to observe the temperature of switches in a FBSM and the variances of capacitor voltages in different conditions. And the simulation results show that optimizing the loss distribution in SMs can reduce the unbalanced degree of capacitor voltages, which further verify the correctness of the theoretical analysis.