Monolithic active pixel sensor development for the upgrade of the ALICE inner tracking system

ALICE plans an upgrade of its Inner Tracking System for 2018. The development of a monolithic active pixel sensor for this upgrade is described. The TowerJazz 180 nm CMOS imaging sensor process has been chosen as it is possible to use full CMOS in the pixel due to the offering of a deep pwell and also to use different starting materials. The ALPIDE development is an alternative to approaches based on a rolling shutter architecture, and aims to reduce power consumption and integration time by an order of magnitude below the ALICE specifications, which would be quite beneficial in terms of material budget and background. The approach is based on an in-pixel binary front-end combined with a hit-driven architecture. Several prototypes have already been designed, submitted for fabrication and some of them tested with X-ray sources and particles in a beam. Analog power consumption has been limited by optimizing the Q/C of the sensor using Explorer chips. Promising but preliminary first results have also been obtained with a prototype ALPIDE. Radiation tolerance up to the ALICE requirements has also been verified.

1 Introduction For the upgrade of the Inner Tracking System [1] of ALICE at CERN a monolithic active pixel sensor is under development.The objectives of the upgrade are to record Pb-Pb collisions at 50 kHz and proton-proton collisions at 1 MHz, while improving the impact parameter resolution by a factor 3, and the standalone tracking efficiency and pT resolution.Fast insertion and removal is necessary to allow yearly maintenance.To achieve these objectives a new ITS layout is foreseen with 7 layers instead of 6, all equipped with monolithic sensors, while reducing: 1.The material budget or the radiation length per layer X/X 0 from 1.14 to 0.3 % 2. The pixel size from 425×50 to between 20×20 to 30×30 µm 2 .
3. The radius of the first layer from 39 to 22 mm.
To reduce the radius of the first layer a beam pipe with outer radius of 19.8 mm is foreseen.Installation is planned for the Long Shutdown 2 of LHC currently foreseen for 2017-2018.
Important specifications (table 1) are integration time (<30 µs) and power consumption density (< 300 mW/cm 2 ).The ULTIMATE chip designed in a 0.35 µm CMOS process for the STAR experiment [2] achieves with a rolling shutter architecture 190 µs and 130 mW/cm 2 for a 20×20 µm 2 pixel.Splitting the pixel matrix in N equal sectors being read out in parallel in this architecture both reduces integration time and increases power density by a factor N. Therefore the product of power density and integration time is a good figure of merit.The ULTIMATE chip with 130 mW × 190 µs = 24700 nJ does not quite reach 300 mW/cm 2 × 30 µs = 9000 nJ.Also its radiation tolerance of 150 krad and a few 10 12 1MeV n eq /cm 2 is below ALICE specifications -1 -  (table 1).Therefore a deeper submicron CMOS technology was chosen for the ALICE ITS upgrade for improved transistor radiation tolerance [3], and development was started to also meet the other specifications.The TowerJazz 180 nm CMOS imaging sensor process [4] has been chosen as it is possible to use full CMOS in the pixel due to the offering of a deep pwell and also different starting materials.The deep pwell (figure 1) shields the nwell containing the PMOS transistors from the epitaxial layer and prevents it from collecting signal charge from the epitaxial layer instead of the nwell intended as charge collection electrode.The foundry also provides stitching to implement die larger than the reticle size.Transistor radiation tolerance well beyond ALICE requirements has been verified [5]. Figure 2 shows the drain current versus gate to source voltage before and after irradiation using 10 keV Xrays for a minimum size 1.8 V NMOS transistor.Only very small radiation-induced shifts can be observed up to a 10 Mrad(SiO 2 ) dose, which is well beyond the ALICE specification.
R&D on the monolithic sensor will be pursued during 2013-2014, with a full conceptual demonstration towards the end of 2013 and a production-ready prototype towards the end of 2014.Several developments based on rolling shutter architectures have been started, Mistral and Astral [6], and a continuation of the Cherwell development [7], and while they are expected to meet the ALICE specifications of integration time and power consumption, it would be very beneficial if the integration time could be reduced to only a few microseconds to obtain much less background, and if the power density could be reduced well below 100 mW/cm 2 to further reduce the material -2 - in the detector.The ALPIDE (ALICE PIxel DEtector) development described further in this paper was started in an effort to lower integration time and power consumption down to these values.It is based on a low power front end (20.5nA/pixel)with data-driven readout.The integration time of only a few microseconds is determined by the shaping time of the front end.
Prototypes of several types of pixel matrices have been submitted and tested.The EXPLORER series has been designed to optimize the pixel sensor, which has a direct impact on the analog power consumption.The pALPIDE chip contains a first version of the low power front end and data-driven readout to validate the ALPIDE approach.In the following these prototypes will be described together with measurement results.
2 Explorer chips to optimize the sensor

Chip design
Analog power consumption is determined by the collected charge over capacitance (Q/C) ratio, requiring pixel sensor optimization [8].An early prototype implemented on an 18 µm thick >1 kΩcm epitaxial layer in the chosen TowerJazz technology showed that changing the reset voltage of the detecting diode over a ∼1 V range drastically affects this Q/C ratio.A new prototype, the Explorer0 (figure 3), was submitted and measured [10], and allows reverse substrate bias similar to earlier ones in another technology [9].It contains two matrices, a 90×90 matrix of 20×20 µm pixels and a 60×60 matrix of 30×30 µm pixels.Each matrix is divided in 9 sectors, equipped with pixels with varying size and geometry of the collection electrode and/or varying distance to the surrounding pwell as detailed in table 1.Each pixel is equipped with two analog storage elements.After resetting the pixel, the analog level of each pixel is stored in its first memory cell, and then after some time, the integration time, the analog level of each pixel is stored in its second memory cell.Thereafter a readout can be initiated to sequentially read all analog storage elements.This architecture allows correlated double sampling and also to decouple integration time from the readout time.

Explorer0 measurement results
-3 - Table 2. Overview of the different sectors in the matrices in Explorer0.
Measurements showed [10] reverse substrate bias reduces input capacitance and average cluster size, and increases efficiency for a certain charge threshold.Figure 4 shows the cluster signal for single pixel clusters and all clusters from a 55 Fe source and illustrates the influence of reverse substrate bias and also that some degradation in signal occurs after a 10 13 n eq /cm 2 radiation, but that the signal remains well separated from the noise.This was also further confirmed in a beam test with 4-6 GeV/c electrons.
-4 -  Analysis showed further sensor optimization could be done, both through design but also using different starting materials.It was also observed that Explorer0 was penalized by too large a circuit input capacitance, which was reduced from ∼5fF down to ∼2fF in a new version, the Explorer1, which came back from fabrication recently.

Explorer1 measurement results and comparison with Explorer0
Figure 5 shows the 55 Fe spectrum obtained by one of the best sectors in Explorer0 and in Explorer1, and illustrates the signal increase.Measurements confirmed no significant change in noise, therefore effectively increasing the signal-to-noise ratio with the same factor.
The improvement is further illustrated in figure 6 comparing efficiencies between Explorer0 and Explorer1, measured both in a 6 GeV/c electron beam.For Explorer0 the result is plotted for one of the sectors with the best performance, sector 6, with an octagonal collection electrode of 3 µm diameter and about 1 µm spacing to the surrounding pwell.For Explorer1 all sectors have been included, and the fake hit rate has been plotted as well.For Explorer1 about 1% of the pixels affected by random telegraph noise were masked.This has only a very limited effect on the efficiency since clusters typically consists of more than one pixel.The horizontal axis plots the charge threshold expressed in multiples of the measured rms value of the noise and it can be seen that the efficiency remains near 100% for Explorer1 up to much larger threshold values.The positive influence of reverse substrate bias can also be observed.

ALPIDE development 4.1 General approach
The ALPIDE development is motivated by the benefits of reducing integration time and power consumption well beyond the ALICE specifications.As mentioned in the previous section, analog power consumption is significantly influenced by the Q/C ratio and thus by sensor optimization.Digital power consumption depends on the on-chip architecture and also on cluster size.As an alternative to the traditional rolling shutter architecture, the ALPIDE development investigates the use of a low-power in-pixel binary front-end in combination with a hit-driven readout.The binary front end is non-linear with a shaping time around 1-2 µs (for measured pulse shapes see figure 9).It is possible to send a trigger signal to the chip within that time after the event took place to allow hit pixels to write a 1 into their memory.After this hits can be read out sequentially by means of a priority encoder circuit, which provides the address of the first hit pixel in a sector, and subsequently resets it, so that during the next clock cycle the address of the next hit pixel is made available.This continues until all hits in the sector have been read out.Digital power is minimized as power is consumed only if hits are present.Very preliminary digital power estimates using this architecture are about 10 mW/cm 2 or less.Currently a full-scale prototype is under study, which should allow us to obtain a more precise number.The encoder is fully combinatorial and is structured as a tree where an element at one level implements the priority for four cells of the level below.A specific level therefore corresponds to two bits in the address, with the lowest level implementing the priority for four pixels and corresponding to the two least significant bits.
Figure 7 shows schematically how a full scale ALPIDE chip would be built: pixels are arranged in double columns, with a priority encoder per double column.This allows space to be used more efficiently for the priority encoder as it is routing dominated and several routing lines can be shared between the two columns.In fact, the pALPIDE prototype discussed below contains one priority encoder per column and figure 8 shows significant space is spent on routing.This guided the decision to opt for a priority encoder per double column in the full-scale chip.The pixel front end includes a storage element for hit information.At the periphery the chip is equipped with cluster information compression circuitry and a multi event memory.The final chip will also include a serializer to send the data off-chip.

Prototype ALPIDE or pALPIDE
A prototype matrix with 64 columns and 512 rows, the pALPIDE, was submitted for fabrication.It is equipped with the ∼40nW in-pixel binary front-end circuit and a priority encoder per column, generated using a standard digital design flow with automated place and route.To fit the digital part into the pixel using this approach, the pixel size was slightly increased to 22 µm×22 µm.The prototype is divided in four sectors: sectors 1 and 2 contain a square collection electrode, and 3 and 4 an octagonal collection electrode.Both collection electrodes are of minimum size still fitting -7 -  input transistor and resetting diode.Pixels in sectors 2 and 3 are equipped with charge injection capacitors, but only for 4 rows these are connected to a pad allowing an external pulse, for all other rows the injection capacitor is grounded.

JINST 8 C12041
Figure 9 shows the analog output of the front end of one pixel under 55 Fe exposure.The response is non-linear, with a decreasing peaking time with increasing signal amplitude.The minimal detectable charge has been measured to be about 130 electrons.At nominal bias and threshold setting (20.5nA/pixel), pixel threshold and noise distributions were measured (figure 10).The measured threshold spread is 17 electrons and the average pixel noise is 7 electrons.These measurement results are preliminary and many things still need to be fully understood.One example is that simulated noise values, obtained by Monte Carlo simulations in the time domain, are a factor 2 higher than measured.No issue with random telegraph noise was observed on the pALPIDE.

Serializer and LVDS driver
The ALPIDE chip also needs to be equipped with a serializer and LVDS driver to send the data offchip.Prototypes of the LVDS driver were submitted for fabrication, and first measurement results -8 - have become available.Figure 11 shows an eye-diagram at 1 Gb/s of the output applying a pseudo random binary sequence for a bias current of 2 mA.A jitter below 10% of the unit interval has been measured illustrating the driver can exceed 1 Gb/s.The LVDS driver still needs to be combined with a serializer.Recent investigation has shown data rate requirements should not exceed 1 Gb/s.

Conclusions
The ALPIDE development towards a monolithic pixel sensor for the upgrade of the ALICE Inner Tracking System is described.As an alternative to approaches based on a rolling shutter architecture, this development aims to reduce power consumption and integration time by an order of magnitude below the ALICE specifications, which would be quite beneficial in terms of material budget and background.The approach is based on an in-pixel binary front-end combined with a hit-driven architecture.Analog power consumption (∼ 40 nW/pixel or < 10 mW/cm 2 ) has been limited by optimizing the Q/C of the sensor.Digital power consumption is minimized using a priority encoder for reading the hit pixels.Preliminary first estimates of an upper limit on digital power are around 10mW/cm 2 .If the ALPIDE approach is successful, data transmission off-chip could be the dominant power contributor, but if data rates can remain well below 1Gbit/s for a 1.5 × 3 cm 2 pixel sensor, this may no longer be the case.Explorer chips were designed to optimize the sensor, and measurements illustrate progress from one iteration to the next, and promising but preliminary results have also been obtained with a prototype ALPIDE.Radiation tolerance of sensor and transistors up to ALICE specifications has also been verified.

Figure 1 .
Figure 1.The deep pwell prevents the nwell containing PMOS transistors from collecting signal charge from the epitaxial layer and therefore allows full CMOS within the pixel.

Figure 2 .
Figure 2. Log (ID) versus V gs characteristic of a minimum size 1.8 V NMOS transistor before and after a 10 Mrad(SiO 2 ) 10 keV Xray irradiation.

Figure 3 .
Figure 3. Floorplan (top) and schematic overview (bottom) of the Explorer prototype.

Figure 4 .
Figure 4. Signal for (a) single pixel clusters only and (b) for all clusters before and after irradiation.

Figure 7 .
Figure 7. Schematic block diagram of a full scale ALPIDE chip.

Figure 8 .
Figure 8. Die photograph of the pALPIDE with an illustration of its division in four sectors and a layout of a single pixel.

Figure 9 .
Figure 9. Analog output of the front end of one pixel under 55 Fe X-ray exposure.

Figure 10 .
Figure 10.Measured threshold (left) and noise (right) distributions for the pixels in the pALPIDE.

Figure 11 .
Figure 11.Eye-diagram obtained with an LVDS driver prototype.

Table 1 .
Overview of the main specifications.