Radiation hardness and quality validation of the on-detector electronics for the CMS Drift Tubes upgrade

In view of the High Luminosity LHC upgrade, the so-called Phase 2 upgrade, the electronics of the Drift Tubes (DT) subdetector of CMS will undergo a complete innovation. The requirements in terms of trigger rate will exceed the capabilities of the present electronics. Thus, all the on-detector electronics together with the associated back-end need to be replaced. Phase-2 on-detector electronics for DT consist of about 800 FPGAs (Field Programmable Gate Array) based boards called OBDT (On-detector Board for Drift Tubes). These boards are sub-divided in two different categories: 600 OBDT ϕ and 200 OBDT θ, targeting respectively the readout of DT wires parallel and normal to the LHC beams. Each OBDT ϕ is able to time-digitize 240 channels with sub-nanosecond resolution and upstream to the back end using multiple high-speed optical links running at 10.24 Gb/s. The choice of components known to have good resistance to radiation was a requirement in the design of the OBDT. The main component, the FPGA, is a flash-based PolarFire from Microsemi, already qualified in different facilities for radiation hardness tests. As a validation step, a campaign of radiation tests was carried out at the INFN-TIFPA Protontherapy Centre in Trento, Italy, using proton beams. The behavior of an OBDT ϕ board was evaluated during radiation exposure with a total dose much higher than expected to be integrated during 10 years of HL-LHC, which is 0.5 Gy.


Introduction
In view of the High Luminosity LHC (HL-LHC) upgrade, the so-called Phase 2 upgrade, the electronics of the Drift Tubes (DT) subdetector of CMS will undergo a complete innovation [1].The DT is devoted to muon identification, re-construction, and triggering: it is installed in the barrel region of CMS, and it is currently used to ensure precise spatial measurements.The requirements in terms of trigger rate will exceed the capabilities of the present electronics.Thus, all the on-detector electronics together with the associated back-end need to be replaced.On-Board Electronics for Drift Tubes (OBDT) [2] boards represent the main part of the electronics that will be deployed in the upgrade.An essential requirement for devices installed in this region of the CMS detector is the qualification in terms of radiation hardness; therefore, an accurate behavioral test in a radiation-controlled environment has been performed.This test has taken place at Trento Proton Therapy Centre (Italy) [3].
This facility, suitable for both radio biology and physics experiments, has two proton beam lines: one for patients' treatment during the day, and another one available in the evening for performing tests and measurements on various apparatuses.Figure 1 shows a picture of the experimental room, located at the end of that second beam line, which was used for the tests presented in the present work.The relevant beam parameters are: • Energy range: 70-230 MeV.
The two main goals of this irradiation campaign are: to assess the reliability of the components used in the last revision of the OBDT board , and to measure the Single Event Upset (SEU) rate of a reduced version of the final firmware running on the PolarFire MPF300TS FPGA1 under at least 10× HL-LHC [1] full lifetime fluence (10 11 protons/cm 2 ) [4].The proton energy to test an integrated circuit intended for use in the LHC environment has been set in the range of 60-200 MeV [5].We chose 148 MeV because the characterization of the beam (e.g.beam profile) used in the INFN-TIFPA facility was done at that energy, the typical one used in proton therapy.The total dose delivered to the electronics under test was 191.6 Gy.Furthermore, 95.1 Gy was delivered to the sole FPGA and 38.4 Gy to the Safety comparator chip.

OBDT board: the device under test
The OBDT electronics board will completely replace the readout and trigger electronics presently used in Phase 1 and will greatly simplify the current system complexity (figure 2).The overall functionalities are listed here: • It receives the accelerator timing reference from the timing backend electronics.
• It measures with high accuracy (800 ps) the time elapsed from a bunch crossing and a hit delivered by the drift tube front-end electronics.
• It transmits packed data through high-speed optical links (10.24Gb/s) to the readout and trigger backend electronics.
• It drives some ancillary controls (thresholds, bias, shaping) and monitor voltages related to the of the front end electronics.-2 -

JINST 19 C06001
860 OBDT boards are needed to fulfill the entire CMS Drift tubes subdetectors.Each board is able to read out 240 channels (one channel per wire); moreover, OBDT boards are developed in two flavors to accommodate the two types of drift tube chambers for the view Θ and the view Φ.

Experimental setup
Aside from the 7 cm diameter uniform spot of the proton beam-line set at the energy of 148 MeV, and a detector that counts the number of protons exiting the cyclotron shown in figure 3 as function of the acquisition time, other elements complete the experimental setup: • A remotely controlled moving frame (where the OBDT is firmly mounted) and fan cooling system allow setting a precise position of the device under test with respect to the beam line and to control the temperature during the irradiation sessions.
• A commercial hardware (Xilinx evaluation Board: KCU105) with custom firmware is used to control the device under test, to emulate the real Drift Tube chamber pulsing front-end OBDT  and to read out the data.
• A remotely controlled and monitored benchtop power supply has been used to deliver power to the OBDT.

NUMBER OF INCOMING PROTONS TIME [min]
Protontherapy Centre INFN-TIFPA CMS MUON preliminary The resulting fluence profile is shown in figure 4.

Test results
During the full radiation campaign no destructive event occurred.The only two components that showed anomalous behavior were the FPGA (Polarfire MPF300T) and one of the comparator (MAX4375) used in the internal safety circuit.In this section the two kinds of failures are reported and discussed.

Errors on FPGA
The firmware of the Polarfire FPGA tested under radiation is a preliminary version of the final one that will be deployed in CMS.For each channel, the input stage consists of a Time-to-Digital Converter (TDC) utilized to tag the front-end pulses with a nanosecond resolution.To sample the incoming pulses, an input de-serializer is used at a rate of 1.28 Gbps (equivalent to 640 MHz in double data rate).The clock frequency is then decreased using a deserialization factor of 1:8 and a shift register that arranges four consecutive bytes in a single word.The final output of the deserialization is a 32-bit word obtained at the LHC clock frequency of 40 MHz.At the output of the de-serializer, an edge detector analyzes the word and assigns a TDC measurement based on the position of the rising edge of the pulse.The output measurements of 240 TDCs are then bufferized and multiplexed on a single output link using a round-robin scheduler.The LpGBT [6] protocol has been chosen for the output high-speed serial link.The protocol works at 10.24 Gbps and is synchronous with the LHC clock, which means that both sides of the link rely on a clock distribution network capable of delivering the same clock frequency to both.
-4 -When assessing the number of errors that occurred during irradiation, we check the data payload received by the LpGBT link.Since the stimuli for the TDCs were generated periodically and injected into the input channels, it was possible to verify the correctness of the TDC measurement and the presence of all the excited channels (and also the lack of time measurement between two stimuli).Single Event Upset manifested as bit-flip or bit-stacked at value in the streamed data.80 channels out of 240 were stimulated at a rate of 5 Hz.The total number of bits of the payload checked was 1200, at a rate of 40 MHz.
Another kind of error was related to the distribution of the TDC measurements.The comparison between the spreading of the TDC measurement distribution during a dry run and during irradiation could be an indication of an induced error in the clock distribution.The source of that SEU-induced skew could be internal to the FPGA or due to an external clock fanout buffer used for providing the fast 640 MHz clock to all the banks.Indeed, the effect that was observed in the data was a specific shift of the time measurement affecting all the TDC of an entire bank.
Figure 5 shows the number of errors recorded for each run taking into account SEU on both the data payload and TDC errors due to the clock distribution.
The calculation of the cross section  was given by where  equiv is the equivalent fluence relative to the number of proton delivered on the actual surface .
Finally the cross section was re-scaled taking into account the full payload during data taking in CMS and the full number of inputs.The cross section of the Polarfire Flip-Flops (FFs) is given by  divided by the total number of FFs employed in the tested firmware.The components affected by this error and their measured scaled cross-section are shown in figure 6.The cross section found is about three times smaller than what found in bibliography [7].However, we were not sensitive to all the FFs employed, which means that SEUs occurring on some FFs have no chance of being detected.It should also be noted that block RAM elements were not used in this design, but only distributed RAMs.-5 -

Failures on safety comparator
The OBDT  has two power supply rails: 6 V and 3 V.Both rails embed an internal safety system that can cut the power in case of over current or over temperature.In this case, the only way to reactivate the power is through a power cycle because the safety system latches the error condition.During the full irradiation campaign the OBDT  went in protection 4 times: 3 times on the 3 V rails and once on the 6 V.The total radiation dose delivered to the safety comparators (MAX4375) was 38.4 Gy.The plot in figure 7 shows the current absorption over time for the two power rails during the irradiation of the region of the 3 V comparator.It is possible to see the sudden drop of current when the safety system starts due to excessive charge deposited on the comparator.In order to recover, a manual power cycle was required after each activation of the safety system.In figure 6 the position on the OBDT  of the two safety comparators is reported along with the calculation of their cross section given by eq.(4.1).-6 -

JINST 19 C06001 5 Conclusions
A radiation test has been carried out on the OBDT  board, which will be used during the next CMS upgrade in view of the HL-LHC.A total of 191.6 Gy has been delivered to the board during the full test hitting small part of the circuit with the beam spot.No destructive events occurred.Two main radiation induced adverse effects were observed: SEUs on the internal FPGA FFs that slightly corrupted the transmitted data, and single events on the safety system comparators that required a power cycle for restoring normal operation.The total failure rate has been calculated by normalizing the error encountered during the radiation test for the total radiation dose during HL-LHC and the total number of board members in the entire system.This led to a SEU rate in the FPGA of 0.7 errors/day and a failure rate of the internal safety system of 0.009 failures/day.Other electronic components, like power regulators, level translators, etc., did not show any visible malfunctioning state.The reprogrammability of the FPGA was successfully tested at the end of each test day and after the full delivered dose (95.1 Gy).

Figure 2 .
Figure 2. OBDT in the CMS final installation context.

Figure 3 .
Figure 3. Integrated number of protons incoming from the beam facility.Technical issues: the machine went into maintenance, hence no protons were delivered to target during this time range.

Figure 4 .
Figure 4. Computed distribution of the fluence accumulated on the OBDT during the irradiation test.

Figure 5 .
Figure 5. Number of Single Event Upsets occurred during the whole irradiation campaign.

Figure 6 .
Figure 6.Cross section of the two component that showed errors due to radiation.In red the Microsemi Polarfire MPF300TS FPGA and in blue the two Analog Device MAX4375 comparators.

Figure 7 .
Figure 7. OBDT  current absorption versus time.Three interesting points are highlighted: the internal safety system triggered due to single events.