Overview of the ATLAS High-Granularity Timing Detector: project status and results

The increase of the particle flux (pile-up) at the high-luminosity phase of the Large Hadron Collider (LHC) with an instantaneous luminosity up to L ≈ 7.5 × 1034 cm-2 s-1 will have a severe impact on the ATLAS detector reconstruction and trigger performance. A High Granularity Timing Detector (HGTD) will be installed in the forward region for pile-up mitigation and luminosity measurement. This detector, based on Low Gain Avalanche Detectors and custom ASICs, will provide a time resolution of 30 ps per track at the beginning of HL-LHC and 50 ps at the end. This proceeding paper will summarise the overall specifications of the HGTD as well as the project status.


High Granularity Timing Detector
The High-Luminosity phase of the Large Hadron Collider (HL-LHC) will start in 2029 with an instantaneous luminosity which will rise up to L ≈ 7.5 × 10 34 cm −2 s −1 .A direct consequence of this update will be an increased event rate: within the same bunch crossing, an average of up to 200 proton-proton collisions is estimated with ≈ 1.6 vertices per mm (at the LHC, the current pile-up is approximately 50 for the ATLAS detector [1]).Distinguishing between collisions occurring very close in space but separated in time is of the biggest challenges.
Figure 1 illustrates the hard scatter interaction (in red) and the distribution of pile-up interactions (in black) over time and along the  axis [2].Relying only on the position information, provided by the inner tracker (ITk), is insufficient to distinguish vertices associated with different interactions.Introducing time information becomes essential to narrow this window.Additionally, the resolution on the high precision tracking delivered by ITk deteriorates as the pseudo-rapidity increases.To address these challenges, the High Granularity Timing Detector was proposed.This novel detector aims to optimise pile-up mitigation and enhance object reconstruction in the forward region.-1 -

JINST 19 C04008
The HGTD is made of two circular detectors located at ±3.5 m from the nominal interaction point, located between ITk and the end-cap calorimeters as shown in figure 2. Each detector radius ranges from 11 to 100 cm with an active area between 12 to 64 cm and a pseudo-rapidity coverage of 2.4 < || < 4.0.The HGTD will provide a time resolution of 30 (50) ps per track and 35 (70) ps per hit at the beginning (end) of the HL-LHC.Each disk accommodates two layers with silicon-based modules and on-detector electronics mounted on the front and back of cooling disks.The HGTD architecture, visually represented in figure 3, provides a global view of the different components comprising a single HGTD disk.

HGTD module
One HGTD module is made of two silicon sensors bump-bonded to two front-end ALTIROC (ATLAS LGAD Timing Integrated Read Out Chips) ASICs.The module is connected to a peripheral electronics board (PEB) via a flexible PCB cable as displayed in figure 4.There are 8032 modules in the HGTD, for a total of 3.6 millions of channels.
Modules are installed as a ring structure on the front and back of the disk with a total of 3 rings per disk.Modules positioned on the front will overlap with those on the back of the disk in order to maximize the number of reconstructed track hits, to optimize detector performance.The inner ring (between 12 and 23 cm) has a 70% overlap while the middle ring (between 23 and 47 cm) has a 50% overlap and the outer ring (between 47 and 64) only 20%.
-2 -  Bench tests for modules with the ALTIROC2 on flex tail are ongoing.While bench tests for modules with ALTIROC3 (radiation-hard version of ALTIROC2) should start soon.

Sensors
The silicon sensors chosen for the HGTD are low gain avalanche detectors (LGADs).They are n-p silicon detectors with an additional p-type doping layer.The sensor features a 15×15 pads where each pad has a size of 1.3×1.3mm 2 for a thickness of 300 μm and active thickness of 50 μm.Thanks to the highly doped p-layer which enables fast timing, the time resolution of the silicon sensor is 30 (50) ps per track at the start (end) of the HL-LHC.Given the sensor design and the target time resolution, the collected charge is expected to be 10 (4) fC at the start (end) of the HL-LHC.
Tests are necessary to verify that the sensors meet all the performance targets in terms of time resolution, collected charge and hit efficiency which has to be of 97% (95% at the end-of-lifetime).To mimic end of the lifetime conditions, the sensors are exposed to fast neutrons (1 MeV neutrons at 2.5 × 10 15  eq /cm 2 for the results presented below).
Test-beam campaigns were realised with electron (DESY) and pion (CERN SPS) beams on different sensors.Results from a campaign on irradiated sensors coming from different vendors, FBK (green circle), USTC (purple losange) and IHEP (red star) are displayed on figures 5, 6 and 7 [3].Sensors were operating at −30 • C to mitigate the impact of radiation-induced damage.The bias voltages were kept lower than the value required to operate the sensors to avoid single event burnout which could damage or destroy the sensors.Figure 5 shows that after an irradiation at a fluence of 2.5 × 10 15  eq /cm 2 , the collected charge is above 4 fC which is the minimum required charge to have a good timing measurement.Figure 6 shows that all irradiated sensors have a time resolution better than 70 ps.The USTC and IHEP sensors can reach a 50 ps time resolution.While figure 7 shows an efficiency above 95% for all sensors which is the target efficiency at the end-of-lifetime of a sensor.
The sensor pre-production was launched and the next step will be to test the pre-production in order to check if the sensors still meet the performance targets.

Front-end ASICs
A custom front-end ASIC needs to meet the requirements on time resolution but also on radiation hardness.It provides the time of arrival and time over threshold but also transmits luminosity measurement (number of hits per bunch crossing).Time walk and jitter have an impact on the time resolution, the readout chip needs to have a small jitter to achieve a time resolution of 30 ps per track.The requirement for the ASICs is of 25 ps at 10 fC and less than 70 ps at 4 fC which corresponds to the end-of-lifetime.As for the time walk effect, the time over threshold is used to correct the time of arrival.
Figure 8 displays the jitter as a function of the charge for ALTIROC2 alone, ALTIROC2 bumpbonded to a LGAD sensor (hybrid module) and the expectation from analog front-end simulations [4].It is shown that the jitter of the hybrid module is higher than that of the ALTIROC2 alone, and does not meet HGTD requirements.After investigations, the most likely cause of these discrepancies was determined to be parasitic capacitances between the sensor and pre-amplifier.This limitation has been addressed in the design of ALTIROC3.The ALTIROC3 is currently being tested: bench tests were successful but the robustness of the hybridisation needs to be tested.A test-beam campaign is also ongoing to test ALTIROC3 ASICs bump-bonded to LGAD sensors to create full HGTD modules.The pre-production will start as soon as the design is approved (currently under development).

Peripheral Electronics Board
The Peripheral Electronics Boards (PEBs) are located on the outermost ring of the HGTD disk.This on-detector electronics boards are the signal processing stage between the front-end electronics and the off-detector back-end as summarised in figure 10.The PEB plays a role in managing the data transmission (for both timing and luminosity measurements), distributing power, controlling and monitoring the system (such as the sensor temperature or the ASIC voltage).This is achieved in particular using lpGBTs (Low Power Giga Bit Transceiver) which are CERN-developed radiation-tolerant data transmission ASICs, DC-DC converter or VTRX+ as shown on figure 11.
The characterisation of individual components of the PEB is ongoing while new prototypes are under fabrication.

Demonstrator
During the R&D phase, a set of intermediate prototypes, called demonstrators, are constructed in order to validate aspects of the final design and integration.The heater demonstrator (see figure 12) was used to develop the cooling of the detector where the thermal performance was studied with 13 silicon-based heaters (to emulate HGTD modules).The assembly procedure was also investigated, especially the validation of the module loading procedure.The DAQ demonstrator is used to develop the full chain readout for timing and luminosity data and to validate the PEB.The readout path was first exercised using up to 14 emulators simultaneously and then replace by a digital module (made out of two ALTIROCs but without LGAD sensors).
The full demonstrator will be used to validate the full system integration (mechanical support structures) and to test the electronics calibration.This demonstrator is a combination of the heater and DAQ demonstrators as 54 full modules (ALTIROCs+LGADs) on detector units will be mounted on a cooling plate and tested.

Summary
The HGTD is a project for Phase-II upgrade (High-Luminosity phase of the LHC) of the ATLAS detector with the goal of pile-up mitigation and precise timing and luminosity measurements.The active area of the detector is based on silicon sensors and front-end ASICs.The technology chosen for the sensors is Low Gain Avalanche Detector as it can provide enough gain for fast timing measurements.The readout of these sensors is done with custom ASICs (ALTIROCs).
The pre-production of sensors is ongoing and ALTIROC ASICs are being tested in order to finalise the design.Modules tests are also ongoing via bench tests and test-beam campaigns.In parallel, the characterisation of the peripheral electronics board is progressing and new prototypes are being developed.These prototypes can be used in the demonstrator program in order to validate the electronics and further develop the readout chain.

Figure 1 .
Figure 1.Visualisation of the truth interactions in a single bunch crossing in the z-t plane, showing the simulated Hard Scatter (HS)  t event interaction (red) with pile-up interactions superimposed (black) for a pile-up of 200.

Figure 2 .
Figure 2. Position of the HGTD within the ATLAS Detector.

Figure 3 .
Figure 3. Global view of one HGTD detector.

Figure 4 .
Figure 4. View of an HGTD hybrid module equipped with its read-out flex cable tail.

Figure 5 .
Figure 5. Collected charge as a function of bias voltage.

Figure 6 .
Figure 6.Time resolution as a function of bias voltage.

Figure 7 .
Figure 7. Efficiency, for a collected charge threshold of 2 fC, as a function of bias voltage.

Figure 8 .
Figure 8. Jitter as a function of collected charge.

Figure 9
Figure 9 presents the architecture of the final ASIC with 225 channels arranged in a 15×15 array.Each channel has a preamplifier with a discriminator (with minimum 2 fC for the threshold), two TDCs and a digital front-end block.Different versions of ALTIROC prototypes were produced and tested: ALTIROC0 with 4 channels in a 2×2 array with only pre-amplifier and discriminator, ALTIROC1 with 25 channels in a 5×5 array and digital components, ALTIROC2 with the architecture and functionalities of the final version (225 channels in a 15×15 array) and ALTIROC3 which is the radiation-hard version of ALTIROC2.

Figure 12 .
Figure 12.Heater demonstrator with silicon-based heaters mounted on a cooling system.