Development of the Continuous Readout Digitising Imager Array detector

The CoRDIA project aims to develop an X-ray imager capable of continuous operation in excess of 100 kframe/s. The goal is to provide a suitable instrument for Photon Science experiments at diffraction-limited Synchrotron Rings and Free Electron Lasers considering Continuous Wave operation. Several chip prototypes were designed in a 65 nm process: in this paper we will present an overview of the challenges and solutions adopted in the ASIC design.


Introduction
Detectors available today for Photon Science X-ray experiments are roughly divided between the ones optimized for Synchrotron Rings (SRs) and low-repetition-rate Free Electron Lasers (LR-FELs) and the ones optimized for high-repetition-rate FELs (HR-FELs).Detectors in the first category are typically capable of continuous acquisition up to a few k-frame/s (typical examples: [1,2]).A common approach for detectors in the second category ( [3][4][5]) is to acquire a "burst" of images and store them in an internal memory on the readout ASIC: the data are then read out slowly during the gap between adjacent FEL trains, while the image acquisition is paused.Thus they can achieve substatially higher rate (up to the MHz regime), but only for short (a few hundred images) bursts.
The upgrade of SRs toward the diffraction limit is expected to increase brilliance by 2 orders of magnitude and demands an upgrade of X-ray imagers to be proportionally faster, while maintaining their continuous acquisition capability.Such devices are also needed to exploit the potential of HR-FELs considering Continuous Wave operation, that will no longer provide gaps between trains which are long enough to read-out an internally-stored image-burst.

CoRDIA
The CoRDIA (Continuous Readout Digitising Imager Array) detector aims at providing a hybrid detector capable of photon discrimination at 12 keV (also compatible with high-Z sensors for higher energies), a substantial full well, a compact pixel size (∼110 μm), and continuous readout capability at a frame rate of ∼150 kfr/s.

Readout ASIC architecture
The imager is a hybrid pixel detector, where a sensor (n-on-p Silicon or High-Z material) is bumpbonded to a readout ASIC.The readout ASIC consists in a 2D pixel array containing a chain of analog (charge integrating) Front Ends (FEs), Analog-to-Digital converters (ADC), and readout (RO) stages.
The circuit stages are pipelined to obtain a Continuous Writing-Reading (CWR) sequence, where the chip readout does not impose pauses in the image acquisition.This has also the advantage of eliminating the need for a large embedded in-pixel memory, thus reducing the pixel size with respect to burst-mode imagers optimized for HR-FELs.Since the data readout needs to happen at a frequency compatible with the acquisition frame rate, high-speed drivers were included in the design, along with suitable circuits preparing the image data for high-speed readout.
-1 - Digital-to-analog conversion happens on a battery of ADCs distributed in the pixel array, as analog signals would not be suitable for high-speed readout.Both the data digitization and its readout require a non-negligible time, which would risk restricting the fraction of time during which the detector can react to new photons: the CWR approach overcomes this limitation by using a pipelined architecture (figure 1) of the charge-integrating and signal-processing circuits, so that while one image is being integrated by the FE, the former image is digitized by the ADC and streamed out.This approach reintroduces the need for a small memory inside the detector, to allow the two operations to happen in parallel; but since such memory depth is very small (just two images), it does not inflate the pixel size significantly.
The Analog FE receiving charge photogenerated in the sensor consists of an Adaptive Gain charge-integrating amplifier capable of extending its dynamic range by modulating its response on the basis of the incoming flux, in real time (as, for example, in [3]).The circuit integrates the charge alternating between two sets of capacitors so that, while one set is used to acquire an image, the other set, containing the integrated charge relative to the former image is used as an input for a Correlated-Double Sampling (CDS) circuit, and then an ADC.As soon as bits are produced by the ADC, they are encoded and streamed out through the RO stage.

Prototypes
Several chip prototypes (figure 2) were designed in TSMC 65 nm technology, and manufactured by means of Multi-Project Wafer (MPW) runs, to test and validate standalone blocks and circuit chains.
In 2021 a first (CoRDIA_01) prototype was designed and manufactured to validate the analog FEs.It consists in separate test structures for the Adaptive Gain circuit (based on a simple split-inverter preamplifier with feedback capacitors selected by a control circuit driven by a discriminator), a CDS block, a circuit to alternate between two readout sub-chains (to achieve CWR), and a full circuit chain of these blocks.The analog blocks described were designed in a Standard-Cell fashion for ease of re-usability and rearrangement, and sized to be easily interfaced to a digital Standard Cell array in the same technology.To improve the design yield, interconnection metal lines were designed wider and more spaced apart respect to the minimum dimensions allowed by the technology (at least twice the minimum for regular signals, and more for power distribution lines), and via redundancy was introduced in all metal layer changes.To improve circuit resilience to Total Dose Ionizing damage, RD53 recommendations regarding device sizes were followed.
Tests ( [6]) were made in 2022 at the expected frame rate of 150 kfr/s.They confirmed the expected behaviour for the Adaptive Gain circuit: the amplification modulation was found to be in line -2 -with the feedback capacitance ratio (45/1 between the Gain stages), and the power dissipation was confirmed to be about 20 uW/pixel.The noise level of the standalone FE block was not measured on this prototype, due to limitations of the test setup.The setup issue has now been solved, and the noise measurement of the FE+ADC chain is in progress, on the CoRDIA_02 prototype described below.We are aiming at noise of about 300e or below.
In parallel, a second (HSI_ADC01) prototype has been designed and manufactured.It included several ADC variants based on a 11 bit Successive Approximation Register (SAR) architecture.The ADC uses a conventional binary-scaled switched-capacitors digital-to-analog converter (CDAC), based on custom-made Metal-oxide-Metal (MoM) 0.94 fF capacitor cells.It has a modest power dissipation (about 24 uW/ADC) and area occupancy (80 μm × 330 μm).
In the CoRDIA design, one ADC is expected to serve serially 16 pixels, thus the ADC need to be capable of at least 16 × 150 k = 2.4 MS/s.Tests in 2022 ( [6]) confirmed the expected performance at 2.5 MS/s, while retaining a Effective Number Of Bits (ENOB) resolution higher than 10 bits, and confirmed the power consumption estimations.During 2022 a third (CoRDIA_02) prototype has also been designed, embedding multiple FEs and an ADC into a modular "superpixel" structure that can be repeated to form the pixel array.About half of the 400 μm × 400 μm "superpixel" layout is used for 16 FE circuits, one quarter is used for the ADC, and another quarter is reserved for a fraction of the common RO stage that is meant to encode and read-out the output of 128 ADCs (2 k pixels).The superpixels are arranged in a mirrored double-column fashion around the common silicon area reserved for the RO circuit.The bump-bond pads interfacing to the sensor are redistributed to a uniform 2D array to facilitate bonding: thus each 400 μm × 400 μm "superpixel" is interfaced as a 4×4 array of pixels with a 100 μm pitch (figure 3).We plan to relax this pitch to 110um in future designs, to be compatible with available sensors.Each FE circuit is also equipped with an internal calibration circuit that can be used to emulate the detection of a given number of photons, for fast characterization of the detector.
The goal of the prototype is to verify the signal-processing of images in a pipeline fashion; the prototype has been manufactured at the beginning of 2023.
To confirm basic (qualitative) circuit functionality, we have used the internal calibration circuits to inject charge in selected pixels (according to a programmable map), to produce recognizable patterns: we have verified that the charge injected in the selected pixels results in a variation of the output of the ADCs which is in line with the charge injection map (figure 4).Tests aimed at (quantitative) performance characterization of the circuit are in progress.
-3 -  During 2023 a further (CoRDIA_03) prototype has been designed, including two different variants of the RO circuit.The RO architecture has been developed by NIKHEF for the Timepix4 chip, and consists in a Physical Coding Sublayer (PCS) circuit to encode the signal (64b/66b) and a Gigabit Wire Transmitter (GWT) as a fast driver.The circuit topology has been extensively tested by the Timepix collaboration both at 5.12 Gb/s and at 10.24 Gb/s [7].Even at the lower bit rate (5.12 Gb/s) it would be suitable for the CoRDIA needs, as it is capable of streaming out the output of 128 ADC (2 k pixels) at the required frame rate.In this prototype, we have adapted the RO circuit to the fan-in expected within the CoRDIA structure, and we have adapted it to our layout constraints (so that the RO circuit fits in the space allocated for it in the "superpixel" structure).The prototype is being manufactured, and it is foreseen to be tested in 2024.
Given the prototype reduced dimensions, local drops of the supply voltage are not expected in these prototypes: design precautions were taken, however, to avoid such drops in the full-scaled chip.A mesh of high level (low resistivity) metal layers was used to distribute power and ground in the circuits: large line widths and redundant via arrays were utilized.
In its first iteration, the full-scaled chip will be contacted by wirebonds: it is planned to wirebond the chip from two opposite edges, to reduce the distance to the pads, and thus the risk of supply voltage drops.In its second iteration, instead, the full-scaled chip will be contacted by Through-Silicon Vias (TSVs) from the backside: this will allow an even more uniform 2D distribution of supply (and ground) contacts in the chip area.TSV landing pads were included in the layout of prototypes, that will result in a periodical structure (one bump-bond pad every 2×2 superpixels) in the full-sized layout.

Figure 3 .
Figure 3. Detail of the superpixel layout in the CoRDIA_02 prototype, showing the circuit blocks, the signal path, and the top-metal redistribution to an array of uniformly distributed bump-bond pads.