The End-of-Substructure (EoS) card for the ATLAS Strip Tracker upgrade — from design to production

The ATLAS Strip Tracker for HL-LHC is composed of individual modules that contain silicon sensors and front-end electronics. These modules are then mounted onto carbon-fiber substructures, hosting up to 14 modules per side. At the end of these substructures, an EoS card connects up to 28 data lines to the lpGBT ASICs and the VTRX+ module, which provide data serialization and 10 Gb/s optical data transmission to the off-detector systems, respectively. The EoS card is powered by a dedicated Dual-Stage DC-DC converter. With the EoS project moving into the production stage, this contribution summarizes the quality assurance and quality control performed during the pre-production phase.


Introduction
As part of the upcoming High-Luminosity Upgrade of the Large Hadron Collider (HL-LHC), the ATLAS Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) [1].This new tracker will consist of a silicon pixel detector in its innermost region and a silicon strip detector in the outer part.The ITk strip detector has a modular design that includes a barrel region composed of staves and two end-caps composed of petals.
At the end of each substructure (stave or petal), a pair of End-of-Substructure (EoS) cards are located [2,3], as illustrated in figure 1.These cards are called "main" and "secondary" respectively.Figure 2 shows an EoS barrel main card prototype.The ITk project requires 1552 EoS cards to be installed, along with approximately 5% spares.Each of these cards must meet various requirements and undergo thorough quality assurance/control (QA/QC) testing.
Section 2 provides a description of the EoS card and section 3 summarizes the QA and QC procedure that these cards must undergo.Finally, section 4 presents the current status of the project and the plans for the production stage.In particular, this section focuses on the efforts made to establish automatic testing setups and reduce the amount of effort dedicated to the QC procedure.-1 -

The EoS card
The EoS cards enable the transfer of data, supply of low voltage (LV) and high voltage (HV) power, and transmission of control signals between the modules and the off-detector systems.Figure 3 illustrates the block diagram of the EoS card.
As the inner barrel modules have twice the number of channels, each of their EoS card is equipped with 28 data lines, while the EoS cards in the outer barrel and end-caps only have 14 data lines.The data rate is of 640 Mb/s and is multiplexed and serialized by two (on the inner staves of the barrel) or one (in the outer region of the barrel and the endcaps) low-power Gigabit Transceiver (lpGBT) [4].The serialized data is then transmitted to the Versatile Link Transceiver (VTRx+) [5], which converts the 10 Gb/s electrical signals into optical signals (TX), and sends the data outside the detector via an optical fiber.Additionally, via the receiver fiber signal (RX) at 2.5 Gb/s converted into electrical signal, the first lpGBT recovers the LHC-clock signal and control data, and generates control signals of 160 Mb/s to the modules through the four Clock, Control, Reject (CCR) buses.
While the modules operate at 11 V, the lpGBTs and VTRx+ require 1.2 V and 2.5 V, respectively.Thus, to power the EoS cards, dedicated dual-stage DC-DC converters are used.
The EoS card consists of a 14-layer printed circuit board (PCB) which follows a hierarchical design with configurable and modular blocks.This hierarchical design allows for the reuse of modular blocks in the 14 different flavors of EoS cards required to meet the varying physical layout of staves/petals, flex lead geometries, and variants with one/two lpGBTs.Two layers in the PCB are dedicated to impedance-controlled signals.All these constraints, including radiation hardness, geometry dimensions, and the fine pitch of 0.5 mm of the lpGBT, have led to a vendor-specific design.More details about the EoS card layout can be found in [2].

Quality assurance and quality control
The unpopulated EoS cards manufactured in industry are received in panels.Each panel includes a Customer Test Coupon (CTC), which has similar dimensions and electrical properties as the cards.Initial electrical, bonding, soldering and pull tests are performed on the CTCs.Bonding quality, resistivities and impedances are compared with predefined tolerance values.If these tests are passed, the corresponding EoS cards are populated.The solder joints of the ball grid array (BGA) of the boards are investigated with X-ray imaging to detect potential defects and ensure long-term operation.
-2 - Figure 4 shows a 3D X-ray image of the solder joints arranged in a 0.5 mm grid.The 70 µm trace structures can be observed when the image is taken with a certain angle.One of the detective solder joints is highlighted in red, and it can be recognized by the gray bubble indicating air.A software able to identify and categorize the defects in the solder joints is being used.While the X-ray imaging is done by an external company, further tests are performed in the Detector Assembly Facility (DAF) at DESY.To reduce the testing duration, the tests are conducted on four different benches.
In a first test bench, the EoS card is identified by its printed numbers, Radio Frequency Identification (RFID) and lpGBTs serial numbers.Optical images of the front and back are captured, and the mechanical dimensions and flatness are measured.This ensures that the cards will fit properly and be securely glued to the carbon-fibers.Power consumption is recorded after turning on the card, and infrared images are taken to detect major electrical failures.The basic functional tests include VTRx+ configuration, lpGBT identification, configuration, ADC value reading, and cross-checking the values with the ones in the CERN database.Finally, the Cyclic Redundancy Check (CRC) test is used to verify the response of the lpGBT to the incoming optical signal.
A second test bench involves a thermal stress test.The card is placed inside a temperature chamber with dry air and cycled ten times from −35 • C to 30 • C. At the extreme temperatures, the card is turned on, and electrical and functional tests similar to the first test bench are performed.
During the high-voltage test on a third test bench, the HV lines on the EoS are checked to ensure that they can sustain the required module HV.The EoS receives 8 channels of HV up to 500 V from the off-detector supplies.The signal is filtered using T-type RCR filters and then transferred to the substructures and the modules responsible for biasing the silicon detectors.In this test bench, the EoS card is placed inside a box with an interlock system.Either one board with flex lead (with eight HV channels) or two boards without flex lead (with four HV channels) can be measured simultaneously.Each HV channel is ramped up to 1.1 kV, which is twice the nominal operation voltage, while the other channels are kept at ground level.The leakage current is monitored every two seconds for one minute.The leakage current must not exceed 5 nA.
A final test bench performs the complete electrical test and a bit error rate test (BERT) of all 640 Mb/s fast signals.Test points are located on the bottom part of the EoS card, near the bond pads on a grid of 0.7 mm.These test points are illustrated in figure 5.The BERT takes about 8 minutes -3 -  and the error rate must be lower than 10 −12 .Different needle probers are required for different EoS card flavors.In QA, optical eye diagrams are recorded with dedicated instrumentation for selected EoS cards.For QC, electrical eye diagrams are recorded with specially written code within the FPGA in parallel to the BERT, as shown in figure 6.Finally, in this test bench, it is also confirmed that the cards can be reset through the partner card.
Once the EoS board passes all the tests, it is packed into a specially designed ESD-proof sealed bag in a dry nitrogen atmosphere.A label with a QR code is printed to indicate the board identification and final status of the QA and QC.Finally, the card is shipped to the assembly sites that will mount the EoS card in the carbon-fiber structures (see figure 7), and perform a test of the full stave/petal.

Towards the production stage
The production throughput of EoS cards depends on factors such as the capability of the manufacturer, the availability of all the required components to populate the boards, or assembly sites requesting EoS cards.A tight production schedule is expected, requiring maximum automation and parallel testing.Due to the ten temperature cycles performed in the second test bench, the number of boards tested per -4 -day is limited to the capacity of the climate chamber that can hold up to 24 cards.While all 24 cards are connected to power supplies, the optical fibres are multiplexed and the boards have to be tested sequentially at a given temperature.The test sequence of ten temperature cycles with 24 board tests at each low or high temperature point (480 tests total) is fully automated and takes about 15 hours.The other test benches require an operator to handle the individual EoS cards.The operator will process a set of cards on testbench one, or two sets of cards in parallel on test benches three and four.
All the test results, including the ones performed with the DC-DC converter not described in this contribution, are recorded in the ATLAS ITk Production Database.

Conclusion
The design and prototype testing, described in this contribution, of the 14 flavors of EoS cards have been proven to meet all the necessary ITk requirements.As a consequence, the EoS project is moving into the production stage.As the next step, the production schedule needs to be updated according to the capabilities of the manufacturer and requesting boards from the assembly sites.Additionally, the database containing all card components and the QA/QC test results for each performed test is currently being finalized.

Figure 1 .
Figure 1.Sketch of the EoS cards located at the end of the carbon-fiber structure in a petal (top) and stave (bottom).Reproduced from [1].CC BY 4.0.

Figure 2 .
Figure 2. A barrel EoS main card prototype with two lpGBT and space for Dual-Stage DC-DC.

Figure 4 .
Figure 4. On the left is a 3D X-ray image of the solder joints of the BGA from the top view.A defective solder joint is highlighted in red.On the right, the same image is captured from a different angle.

Figure 5 .
Figure 5. Needle prober with an EoS card.On the top, the 0.7 mm grid of test points is shown.

Figure 6 .
Figure 6.Eye diagram of the 10 Gb/s outgoing optical signal.

Figure 7 .
Figure 7. Petal fully loaded with the EoS card mounted.