The DMAPS upgrade of the Belle II vertex detector

The SuperKEKB collider will undergo a major upgrade to reach the target luminosity of 6 × 1035 cm-2 s-1 during the long shutdown (LS2) foreseen to start around year 2027. We are developing a new vertex detector (VTX) to replace the current one (VXD). This new pixel silicon tracker aims to be both more robust against the higher level of machine background and more performant in terms of precision on the decay vertices and standalone track finding efficiency. The baseline layout consists of two layers composing the inner part (iVTX) and three outer layers (oVTX), all arranged in a barrel-shaped geometry, with minimal material budget. All layers will be equipped with dedicated depleted monolithic active CMOS pixel sensors (DMAPS) named OBELIX, designed in the TowerJazz 180 nm technology. This paper will review all the aspects of the project: the detector specifications and the baseline design, the expected improved performance, the OBELIX features and its design status, including the tests of the forerunner chip TJ-Monopix2, and the fabrication and tests for the iVTX and oVTX ladder prototypes.


Introduction
The Belle II experiment [1] aims to search for possible effects beyond the Standard Model in flavor, tau, electroweak and dark sector physics.Data taking started in 2019 at the asymmetric  +  − collider SuperKEKB [2], operating at the center of mass energy of the resonance Υ(4S).SuperKEKB has reached the world record instantaneous luminosity of 4.7 × 10 34 cm −2 s −1 in June 2022, and in order to achieve the expected physics sensitivity of the experiment it will need to increase by an order of magnitude the peak luminosity, with the target of 6 × 10 35 cm −2 s −1 .This will require an upgrade of the collider, that is planned during the Long Shutdown 2 (LS2), around years 2027-2028, which might also foresee a major redesign of the interaction region (IR).The current silicon vertex detector (VXD) of the Belle II experiment is composed of two layers of DEPFET pixels (PXD) [3] and four layers of silicon double-sided strips (SVD) [4].VXD is performing very well but it has limited safety margins for running at the target luminosity, due to the high machine related background levels predicted with large extrapolation uncertainties: some degradation of the performance are expected due to the high occupancy.An upgrade with a new pixel vertex detector (VTX) is now proposed to improve the robustness against the harsh future machine backgrounds, the track finding efficiency and resolution, and match a possible new IR re-design.

VTX requirements and baseline design
The most demanding requirements for the new vertex detector concern the layer closest to the interaction point and thus exposed to the largest track density.The radiation levels to withstand are 100 Mrad (Total Ionising Dose) and an equivalent 1 MeV neutron flux of 5 × 10 14 n eq /cm 2 (NIEL).The maximum average hit-rate to sustain is 120 MHz/cm 2 .A much faster integration time (50-100 ns) and a finer segmentation (33 μm pitch) will allow to reduce the occupancy by a factor 200 with respect to the Layer 1 in VXD.
To limit the detrimental effect of the multiple scattering, a very low material budget (less than 2% / 0 in total) is required, becoming less strict for the longer ladders of the external layers.
-1 -All these requirements are matched by choosing a Depleted Monolithic Active CMOS Pixel Sensor (DMAPS) [5] as a unique building block for the whole vertex detector, made of five straight fully pixelated barrel layers.The VTX baseline design features an envelope close to the current vertex detector, spanning from radii of about 14 mm to 135 mm.The layout consists of two identical layers composing the inner part (iVTX) in a silicon self-supporting structure, with air cooling to minimize the material, and three outer layers (oVTX).Due to the longer dimensions in oVTX, its ladders must be supported by a stiff carbon fiber structure and provide an active cooling system to evacuate the dissipated power.The specific power of the chip will be 200 mW/cm 2 .

Improved vertexing and tracking performance
A key ingredient in evaluating the capabilities of this new detector is the expected level of hits caused by the machine background the detector must withstand.So far in absence of the final design of the new interaction region, the impact of the machine background on the physics performance is evaluated assuming three different levels of background, providing respectively an optimistic, nominal and conservative background scenarios: hits from the different background scenario are overlaid to signal events to study the impact on a specific channel.For instance in the "golden channel"  0 → /  the new VTX results to have a 35% better vertex resolution than the current VXD and it shows to be quite insensitive to the different levels of background.
-2 -In the current VXD detector the tracks reconstructed with the hits in SVD and the drift chamber are extrapolated to the PXD to find and add PXD hits.Instead all VTX layers will provide information to the trigger system and will be used in track reconstruction.
VTX provides better tracking efficiency than VXD especially at low momentum: as shown in figure 1 soft pions from  * are reconstructed with high efficiency down to a transverse momentum of 50 MeV/c.

The OBELIX chip
A dedicated depleted-MAPS CMOS sensor named OBELIX (Optimized BELle II pIXel sensor) is under design and it will equip all the layers of VTX.This is an approximately 2 cm × 3 cm large die designed in the TowerJazz 180 nm technology, featuring a 33 μm pitch, whose pixel matrix and the column drain architecture are inherited from the TJ-Monopix2 sensor originally developed for the ATLAS experiment [6].The core specifications on readout speed and maximum rate are matching the Belle II needs.OBELIX will include a new digital periphery for the trigger logic and the needed memories: 30 kHz is the average trigger rate to sustain with 10 μs trigger delay and a maximum hit rate of 120 MHz/cm 2 .
Other noteworthy design features implemented are: the counter used for the timestamp of the hits (also called Bunch Crossing Id, 20 MHz) is transmitted to all pixels by the End-of-Column logic; signal amplitude information is provided with the Time over Threshold (7 bits ToT, 20 MHz); a 3 bit threshold tuning is available at the pixel level to reduce the threshold dispersion.The column drain readout of the matrix is able to sustains a peak hit-rate greater than 600 MHz/cm 2 .Sensor peripheral and trigger unit logic is able to handle an average hit-rate of 120 MHz/cm 2 (340 Mbps throughput).OBELIX additional features implemented in the matrix periphery are the TTT, track trigger transmission, that could provide a coarse but fast information to the Belle II trigger system, and the PTD, periphery time to digital, which can be used for precision timing of the pixel hits in the external layer, using a faster clock than the BCID, available in the periphery.This will allow to attach to the tracks some hits with a finer time resolution and will be beneficial to improve the rejection of off-time background tracks, without increasing the main BCID timestamp resolution, and consequently the power consumption.
With the small pixel pitch of 33 μm, and the timestamp of 50 ns, the estimated power consumption of the OBELIX chip could be kept below 200 mW/cm 2 up to an average hit rate of 60 MHz/cm 2 , that is a factor two higher than what is expected in the Layer 1, assuming the conservative background extrapolation scenario at the target luminosity.
A first complete version of the sensor has been designed [7] and it is expected to be submitted to the foundry in the first quarter of 2024 after passing the final verification phase.
Extensive tests have been performed on TJ-Monopix2 chip, considered as a "proof of principle" of the prototype sensor for the Belle II VTX.
The chip, implementing different pixel front-ends in four regions, has been fully characterized on bench in the laboratories of the institutes of the VTX collaboration.S-curve tests with internal charge injection have been performed, by tuning the sensor for low threshold and low dispersion, obtaining an average threshold of about 280  − with a threshold dispersion of 17  − and an equivalent noise charge of 8  − , as shown in figure 2. The absolute calibration of the injection capacitance, performed with X-rays emitted by the radioactive source  55 , agrees well with the design value, with measurements of the conversion factor ranging in the interval of 8.5-10  − / .
-3 - For resolution and efficiency measurements we have conducted a number of test-beam campaigns at the DESY facility [8], with electrons of 4 GeV energy.In the first test-beam in June 2022 an un-irradiated chip has shown a cluster position residual of 9.15 μm (slightly better than the pure digital resolution) and a hit efficiency above 99% for 500  − threshold.During the test-beam in July 2023 lower threshold settings of about 300  − have been applied and a scan on the incident angle has been done.Data analysis are ongoing and it is worth reporting that very encouraging preliminary results have been obtained for the hit efficiency on an irradiated chip with an equivalent neutron fluence of 5 × 10 14 n eq /cm 2 .
Further tests to asses the level of radiation hardness (NIEL and TID) are in progress.

Ladder concept and prototypes
The design structures of the ladders differ in the various layers due to their active length, varying from 12 to 70 cm to cover the required angular acceptance (17 The two innermost iVTX layers are based on an "all-silicon ladder" concept aiming for a material budget of 0.1% / 0 per layer.They are placed at radii 14 and 22 mm respectively.Three aspects concur to the possibility to build such a light ladder by making the air cooling a viable solution: the moderate overall area of these two layers (below 400 cm 2 ), the low power dissipated by the chip and the very few connections needed to operate it.Assuming a specific power density of 200 mW/cm 2 , thermal simulations on a single ladder have shown that a flow of dry air at temperature 15 • C and speed 10 m/s results to be effective in keeping the temperature of the single ladder uniform at about 20 • C. Currently a test bench facility to evaluate the efficiency of an air-cooling system has been built as shown in figure 3), implementing a mock-up of the iVTX.The total power to evacuate is 80 W, unidirectional and bidirectional air flow is under study, as well as the measurements of the mechanical vibrations that are eventually caused by the high air speed.
Four contiguous OBELIX chip blocks are diced out of the production wafers and the back side of the sensor regions are thinned down to 50 μm.
In more detail, a post-processing step deposits additional metal strips on a so called redistribution layer (RDL) to interconnect sensors along the ladder and to provide a unique connector at one ladder -4 - end.The RDL will be produced in a thin-film process with photo lithographic structuring of polymer dielectric and metal layers.Vias connect the sensor bond pads to the metal traces, which route power and data via impedance-controlled transmission lines to the end of the ladder, where a flex cable is connected.Exposed pads are created on top of the RDL to mount surface mounted components (SMD) like bypass capacitors.After the RDL has been processed, the backside of the ladder will be thinned selectively.A thickness of 50 μm is foreseen underneath the active sensor area, while the ladder remains un-thinned for mechanical rigidity on the outer perimeter.Mounting holes will be opened via laser-cutting.The first ladder demonstrator is currently under production to explore the feasibility of the two techniques (see figure 4): a large size RDL on top of the sensors and the selective backside thinning of the ladder.
The first demonstrator is based on a silicon wafer processed with dummy heater structures in place of the sensors, allowing to characterize the electrical, mechanical and thermal performance of the ladder prototype.This is the first step of a working plan developed together with IZM (Berlin) which foresees to gradually increase the complexity of the process up to the electrically working final ladder.A more traditional approach has been followed for the ladder concept of the outer layers (oVTX), inspired by the design successfully developed for the ALICE ITS2 [9].
-5 -Each ladder (see figure 5) is made of a light carbon fiber support structure, a cold plate including pipes for liquid coolant circulation by negative pressure, a row of sensors glued on the cold plate and finally two flex circuits connecting each half-ladder to a connector.For the Layer 3 a single flex exiting on one side of the detector can be foreseen.
Depending on their radius, the material budget of individual oVTX ladders ranges from 0.3 to 0.8% / 0 , matching the requirements set in section 2. The exploded view with the parts composing the Layer 5 ladder is reported in figure 6.
To ensure that the  −  overlap between adjacent ladders is at least 10 pixel pitches for all the ladders, the clearance between two adjacent ladders in the radial direction is the order of 1 mm.Two versions of the Layer 3 ladder have been designed at radius 3.9 and 6.9 cm respectively to optimize the efficiency in reconstructing the vertex of   .The green region on the chips corresponds to the periphery, i.e. the not sensitive area.
A prototype of the longest and thus most challenging ladder of the Layer 5 has been realized and mechanically characterized: a sagitta of about 250 μm has been measured adding a weight equivalent to the final assembly, distributed uniformly on the prototype.
The vibrational analysis found the first resonance frequency of the assembly at 250 Hz, a value much greater than the typical frequencies involved in an earthquake.
For the thermal characterization kapton heaters have been glued on top of the cold-plate, mimicking the chip power dissipation.A liquid coolant circuit under negative pressure to prevent spilling out, with inlet and outlet on the same side was able to cool uniformly the ladder with a maximum temperature gradient along the module of Δ max = 3.A significant amount of the total material of the oVTX ladders is taken by the traditional flex circuits used to distribute power and for data output.To match the limited material budget, evolving in parallel with the chip design, a new flex circuit will be realized in aluminum, allowing to be connected to the OBELIX chip in an electrically working half-ladder prototype of the Layer 5.
-6 - Due to the high cost of the process in aluminum, a first prototype power bus has been designed and realized on a four-layer process in copper, to distribute positive voltage and ground line pair to each OBELIX chip, with the same maximum voltage drop (200 mV, according to the requirements) for all the chips along the ladder.Signal integrity tests performed on this copper flex assessed a bandwidth larger than the needed baseline data throughput.The Layer 4 and 5 ladders are naturally divided in two electrical units and so the services (electrical connections and cooling) are provided both on forward and backward sides.For integration simplicity of the Layer 3 ladder a solution with the only access on one side has been investigated.

Conclusion
The SuperKEKB collider is planning a major upgrade to reach the design luminosity.An all-layer monolithic vertex detector, more performant and resilient against higher machine backgrounds, might be installed during the shutdown, proposed to start around 2027.The target specifications of the vertex detector in terms of material budget, spatial resolution and timestamp resolution have been identified, together with the baseline chip technology TJ-180 nm.Evolving from the design of the chip TJ-Monopix2, the CMOS sensor OBELIX is expected to be submitted the first quarter of 2024.
The realization of prototypes for the inner and outer layers are ongoing, submitted to the mechanical, thermal and electrical characterization.
The Conceptual Design Report of the Belle II Upgrade is reaching its finalization phase.

Figure 1 .
Figure 1.Reconstruction efficiency for the benchmark channel  0 →  * −  +   as a function of the transverse momentum of the  − soft from the  * − →  0  − decay (with  0 →  −  + ).The figure reports the performance for the Belle II VXD (indicated as nominal Belle II, with v2 level of background, i.e. nominal background) and for VTX in the three background scenarios (optimistic: v1, nominal: v2 and conservative: v3).The pion reconstruction efficiency as a function of its momentum is shown in the plot for the various conditions.The shaded blue histogram displays the momentum spectrum of the  − in arbitrary units.The bottom plot shows the ratio between the current Belle II and VTX with the nominal background v2.

Figure 2 .
Figure 2. TJ-Monopix2 test results: on the left S-curve characterization of threshold, on the right calibration by charge injection by internal capacitor and with photons from a Fe 55 source.

Figure 3 .
Figure 3. Left: distribution of the temperature on a single iVTX ladder with flushing dry air (from thermal simulation).Right: the thermal test-bench with the pipes supplying the dry air to the mock-up of iVTX.

Figure 4 .
Figure 4.The concept of the iVTX ladder.

Figure 5 .
Figure 5. Drawings of the oVTX ladders for the Layer 3, 4 and 5.Two versions of the Layer 3 ladder have been designed at radius 3.9 and 6.9 cm respectively to optimize the efficiency in reconstructing the vertex of   .The green region on the chips corresponds to the periphery, i.e. the not sensitive area.
3 • C, well below the 5 • C difference in a single chip according to the specifications.With a  = 20 • C temperature of the environment and an inlet temperature of  in = 10 • C, the maximum temperature along the ladder results  max = 26 • C, assuming the nominal specific power.

Figure 6 .
Figure 6.Left: exploded view of the Layer 5 ladder.Right: cut view of the whole VTX.