New electronics for the HADES MDC drift chambers

The drift chambers of the HADES experiment at SIS-18 at GSI, Darmstadt/Germany, form the main tracking system of the spectrometer. Designed more than twenty years ago, the whole front-end electronics chain is being replaced with state-of-the-art electronics to cope with the increasing failure rate of the old electronics and with advanced requirements of the experiment, e.g. the trigger rate. The new analog signal processing is based on the PASTTREC ASIC, developed for the Straw Tube Tracker of the PANDA Experiment. The digitization of data happens in FPGA-based TDCs. The main challenges of the project are the strict spatial constraints given by the experiment setup to place the front-end boards and the noise sensitivity of the large area gas detectors. In addition, the power consumption needed to be kept low due to thermal constraints.


Introduction
HADES is a di-lepton and hadron spectrometer located at the SIS18 synchrotron at GSI Helmholtzzentrum (Darmstadt, Germany) [2].This facility delivers beams with kinetic energies up to 2 AGeV for heavy nuclei, 4.5 GeV for proton and 2 GeV for secondary pion beams on a fixed target.HADES consists of six identical sectors surrounding the target area covering polar angles from 18 • to 85 • .Each sector features two drift chambers in front and two behind, respectively, of a toroidal magnetic field of up to 1 T. The 24 trapezoidal and low-mass Mini (-cell) Drift Chambers (MDC [1]) form the central tacking system of the spectrometer comprising about 27000 read-out cells with active cross-sections ranging from 5×5 mm 2 to 14×10 mm 2 .The space available to be occupied by the front-end electronics is defined by the spectrometer's azimuthal coverage of 85%, constrained by the coil boxes of the magnet.
The front-end electronics being used since 20 years employs the ASD8 [3] ASIC for amplification, shaping and discrimination and semi-customized CMOS TDC ASICs for digitization.Besides the drift time, the charge signal, typically several pC, is exploited by means of a time-over-threshold measurement, yielding a dE/dx information of the traversing charged particle.
The increasing failure rate of hardware installed, the speed of data processing no longer keeping up with the already upgraded HADES DAQ components and the need to measure several signals per event to increase the cell's detection efficiency did motivate the development of the new MDC read-out presented here.This new electronics will further improve the signal-to-noise ratio of individual cell signals, the precision of the dE/dx measurement and optimize the power scheme, stability and maintenance of the system.-1 -

Analog front-end
The signals arriving to the front-ends from the drift chambers through flat cables are first fed into a filter and protection stage.A simple, passive circuit (shown in figure 2) provides impedance matching, AC coupling and over-voltage protection.This circuit needs to withstand voltage spikes up to 2 kV that can occur due to discharges within the detector.
Subsequently, the signals enter the active electronics, based on the highly configurable 8-channel PASTTREC2 ASIC chip (CMOS), designed for the straw tube detectors of PANDA experiment [4].The signals are amplified (charge sensitive preamplifier), shaped with tail cancellation (CR-RC followed by pole zero cancellation, baseline holder loop, fine-tuned by DACs) and discriminated with a common threshold as shown in figure 2. PASTTREC has a number of programmable settings, such as gain (0.67, 1, 2, 4 mV/fC), peaking time (10, 15, 20, 35 ns), four individual shaper parameters and a common threshold for all eight channels.Furthermore, each channel features a baseline correction setting, which can be considered as an individual threshold fine tuning.The input impedance varies between 35 and 65 Ω, depending on the shaping time set, the power consumption is 35 mW/channel.PASTTREC has been originally optimized for an application with straw tubes.In contrast, the HADES drift chambers have a lower charge generated per hit and a faster drift velocity so that the parameter set had to be re-adjusted [5], yielding 4 mV/fC and 10 ns for the gain and peaking time, respectively.

Time measurement and readout
The discriminated signals are sent as LVDS signals to an FPGA (Lattice ECP5-45) that contains the digitization and data acquisition logic.The timing precision of drift chamber detectors is in the order of 2 ns so that no high-precision TDC circuitry is needed.The chosen technology is a 312.5 MHz clock sampling TDC, using eight different clock phases.The resulting average bin size is 400 ps with a measured effective precision of 140 ps (RMS).This design allows for a small footprint implementation that leaves ample space for additional features.The TDC is used to measure both time-of-arrival and time-over-threshold (ToT) to contribute to particle identification during analysis.Signals with a ToT of less then 15 ns are immediately discarded to save bandwidth as they don't correspond to physical hits but are generated by noise.
-2 -Each board houses an additional, identical FPGA acting as a network interface to connect the board to the rest of the HADES DAQ system [6].For data transmission a dedicated network protocol (TrbNet, [7]) combines triggering, data transport and control access in all parts of the detector on optical and electrical links running at 2 Gbit/s.Off-the-shelf SFP or SFF transceivers are employed in the MDC electronics.Several other options of transceivers with lower power requirements were evaluated but ultimately rejected due to mechanical stability, noise immunity, transmission speed or price.

Mechanical design
The form factor of the electronics had been fixed during the design of the detector chambers by the arrangement of signal outputs: the front-end boards need to have a width of no more than 4 cm and lengths of 24 and 31 cm with a channel count of 64 and 96, respectively.The height is restricted to the insensitive areas of the detector and cannot exceed 3 cm.Likewise, the location of the connectors to accept the input signals from the sense wires on flex printed cables is fixed within few centimeters.
The long and narrow module shape with all supplies located at one end posed some challenges for the board design: high-speed digital links for clock and data transport have to be routed along the full board length, but need to avoid regions with weak analog signals going towards the analog front-end ASIC.The discriminated input signals are required to respect the same keep-out areas as they use differential lines to be sent into the FPGA for time measurement.This resulted in a dense routing scheme across major parts of the PCB.The choice of board technology also needed to take into account the various low-impedance power planes for different system components.The result was a still manageable twelve-layer stackup with two layers of blind vias on both sides.
The original design consisted of a stack of three PCBs due to the space constraints given by IC and connector sizes.For the new iteration this could be reduced to a stack of two boards: the main board (MBO) containing all active electronics, analog input boards for 16 channels each (daughter boards, DBO) and an add-on with the optical transceiver and power connectors, as shown in figure 3.
While the setup with stacked boards could not be avoided due to the limited board area available, it also provides advantages during installation and possible later maintenance: in the tight space between detectors connecting cables to a large board with many connectors would be very difficult.As all cables are placed on small add-on boards handling is very much simplified.These small boards can be easily plugged into the main board after connections have been made, eased by a set of guide pins.For the interconnect between boards a connector with high retention force (Samtec LSHM series) has been selected to avoid the necessity to fix the boards in place by screws.Nevertheless, nylon has been chosen as the material for all nuts and bolts to reduce the risk of damage to detectors in the case of dropping them during maintenance.

Reliability features
Apart from the obvious features to ensure proper operation of the electronics such as voltage and temperature monitoring, several features have been included to simplify restart procedures and increase reliability.
Automatic configuration.The expected radiation environment in the experiment is low enough to not require TMR or partial reconfiguration features for the programmable logic, but is still causing a noticeable amount of errors, e.g.due to single event upsets.These issues shall be easy to mitigate by a simple power off/on cycle for individual boards through the remotely controllable power supplies.To reduce the total downtime of the sub-system in these cases, all configuration settings, e.g.parameters for the analog ASIC, are stored in the on-board Flash ROM that also contains the FPGA bit stream.At power-up these settings are read and converted to write accesses on the internal control data bus.In a second step an automated routine configures the ASICs by issuing the relevant commands on their SPI configuration interface [9].Dual boot.Many of the boards will be installed in areas that are difficult to access.At the same time it is foreseen to remotely upgrade the FPGA firmware and use the Flash ROM to store configuration data that are likely to be updated from time to time.To counter the risk of inadvertently destroyed FPGA firmware, a dual boot functionality was implemented.The first generation of FPGA boards contained two Flash ICs, one of them in read-only mode.These could be selected using a control line from the FPGA.This proved to be an obstacle because interaction with the FPGA was required to select the proper Flash ROM during boot.
In this upgrade the selection mechanism was changed to an independent, purely analog timing circuit: at power-up it selects one Flash ROM, but switches to the other after few seconds.Another quick power cycle doesn't change the selection, but an extended power down (about 15 seconds) changes it back.That is, both memories can be selected externally, depending on the duration of a power cut.The corresponding circuit is shown in figure 4. two levels of linear regulators, one directly on the front-ends and one on an intermediate board.The voltage levels on the latter could be adjusted manually via trimming potentiometers.This scheme proved to be impractical due to variations over time that required repeated adjustments.
Using a powering scheme relying purely on linear regulators again would lead to a strongly increased power dissipation: the power draw of the new electronics is similar to that of the old one, but operating at greatly reduced voltages.As a consequence a hybrid, adjustable powering scheme was implemented.While the front-end boards only contain linear regulators, an intermediate powering board was located at the edge of the detector.State-of-the-art low-noise switching regulators (Analog Devices LT8650S) could be placed there without negative impact on the detector performance.These boards are fed from the power supplies at a higher voltage (e.g.20 V) and produce two voltage rails for the front-ends of about 1.6 V and 3.8 V, greatly reducing the overall losses in the power distribution system.
From these boards the remaining distance to the front-ends is still substantial and varies between 0.5 m and 4 m, resulting in an expected voltage drop of up to 1 V. Adding a dedicated sense line would need an additional wire pair per board in a densely populated space.To cope with this, all DCDC converters are adjustable by means of switchable voltage divider resistors in the feedback line.These can be controlled remotely through an Espressif ESP32 micro-controller and Ethernet.It also provides the interface to power down individual front-ends and all monitoring of the voltage distribution system.

Performance results and conclusion
The readout system has been tested with a full-size HADES drift chamber, equipped with 10 MBO boards.The chamber was exposed to a 1.92 GeV proton beam, provided by the COSY accelerator at Research Center Jülich.The intrinsic feature of self-tracking between two adjacent wire layers, featuring a well defined spatial relation to each other, was employed to obtain the time precision of the combined detector and read-out system, amounting to 3.6 ns, see figure 5.
Based on these promising results, mass production has been started and the upgraded electronics will be deployed during 2024.-5 -

Figure 1 .
Figure 1.The main board of the new MDC electronics with all active components on the top side and connectors for add-on boards on the back.

Figure 2 .
Figure 2. Schematic view of the signal input stage including decoupling capacitor, discharge resistor and protection diodes (left) and the internal circuits of the PASTTREC ASIC [8] (right).Acronyms used: PZCpole-zero cancellation, TC -tail cancellation, LED -leading edge detection.

Figure 3 .
Figure 3. Left: part of the backside of the main board with two attached input and filter boards (DBO).Right: the add-on with optical transceiver and connectors.

Figure 4 .
Figure 4.The analog timing circuit that selects one of two on-board Flash ROMs to prevent failure due to corrupted memories.

Figure 5 .
Figure 5. Measurement of arrival times in two adjacent detector cells hit by the same proton.The difference vs. sum of arrival times between cells 4 and 6 (left) and their projection (right) is shown, allowing to extract the single cell precision of  single =  raw,2 / √ 2 = 3.6 ns.