Real-time signal processing and data acquisition for the Electric Field Detector (EFD-02) on the CSES-02 satellite

The Electric Field Detector (EFD-02) on board the second China Seismo-Electromagnetic Satellite (CSES-02) will measure the electric field components at a Low Earth Orbit (LEO) over a wide frequency band (DC – 3.5 MHz) and with 1 μV/m sensitivity in the Low Frequency band. EFD-02 will measure the voltage differences between pairs of probes installed at the tips of four booms deployed from the satellite. In this article, we describe the Zynq System on Chip (SoC)-based digital hardware subsystem dedicated to signal processing, and the selected implementation strategy, which successfully complied to the specific requirements of the space mission. Furthermore, we present a comprehensive overview of the assessed instrument performance.


Introduction
The China Seismo-Electromagnetic Satellite (CSES) mission aims to monitor the dynamic disturbances in a LEO-polar orbit (∼ 500 Km) in terms of electromagnetic field, plasma parameters, and particle distributions in order to explore potential links with seismic events [1].Another key objective of the mission is to investigate the interaction between the solar wind and the magnetosphere-ionosphere system [2].The CSES-02 mission is scheduled for launch in 2024, with an expected operational lifespan of 6 years.The Electric Field Detector (EFD-02), on board CSES-02, will measure the differences in electric potential between different pairs of probes mounted at the tips of 4 booms deployed at 4.5 m from the satellite.Electric field (E) components are obtained as the difference between two probe voltages divided by their relative distance (8.1 m on average).
The main EFD parts consist of the Electric Field Probes (EFPs) and 5 electronic boards, as shown in figure 1.The EFPs are 4 spherical sensors of same diameter, each placed at the end of one of the satellite booms.They have the task of detecting the electric potential with high precision.The electronic boards include: the Analog Processing Unit (APU) which operates the analog-to-digital conversion and pre-filtering of the signals; the Digital Processing Unit (DPU), which performs the signal processing and data acquisition tasks.-1 - The APU board receives signals from the 4 probes, performs a preliminary division into three frequency bands (Low, Medium and High Frequency -LF, MF, HF respectively) and applies a configurable probe-pair signal difference for MF and HF bands, in order to have a direct measure of the 3 electric field components.Each channel is then digitized by a set of on-board ADCs and routed to the DPU board, which in turn sends the data collected to the satellite.

The Digital Processing Unit (DPU)
The DPU, which is based on a Zynq-class Xilinx FPGA, is organized into several logic and functional parts, illustrated in the block diagram in figure 2. Its main tasks are: a) managing interfaces towards the APU board, such as ADCs configuration and data decoding, clock management; b) the implementation of the DSP logic block, performing final band division and downsampling by means of cascading FIR filters, according to the scheme shown in table 1; this block also applies a 2048-point Fast Fourier Transform on selected bands, with Hann windowing and final amplitude calculation; c) the implementation of the control and data acquisition block, which is in charge of packing payload's data, applying a scheduling acquisition rate, adding a system-wide timestamp, and send the data to the DMA channels towards the on-board processor memory.It also performs a complete system configuration using memory mapped registers; d) the implementation of the CPU, memory interface and satellite interface block, which uses the ARM processor of the Processing System equipped with a space-grade real-time operating system [3] in order to send payload data to the satellite through an RS-422 interface.In order to comply with the stringent data payload constraint (82 Gbit/day), the DPU performs two kinds of data reduction strategies: a) a time-based scheduling, according to band type and mission mode (survey/burst); b) specifically for FFT signals, a set of average, standard deviation -2 -and kurtosis values is packed and sent.Providing both standard deviation and kurtosis together with the averaged samples of an FFT sequence ensures a better identification of signals against the background noise, in particular for the detection of occasional events, or for catching the lack of expected signals.Averaging over 50 sequences ensures a reduction factor of 3  50 of the data payload (implying a data reduction of 94%).The real-time calculation of these functions is offloaded in the Programmable Logic part of the Zynq SoC, so as not to overload the ARM Processor System with tasks other than satellite communication and system control.

Hardware implementation
Due to the large number of concurrent channels (3) and bands (3) that need an independent hardware implementation of the calculation of statistical functions, it is crucial to design this operation with the least possible impact on the amount of resources used.
If we define   [ ] as the j-th sample (with  = 0 . . .1023) of the i-th FFT sequence, and M=50 as the number of sequences we consider, then we use the definition of average, standard deviation and kurtosis, respectively as: Directly implementing these definitions into hardware would lead to store all the samples   [ ] before knowing [ ], which in turn could lead to an excess of local memory resource usage.
Taking advantage of basic polynomial properties, the standard deviation can be rewritten as: and the kurtosis as: which are linear combinations of the four powers of the summation of   and  [4].
From an hardware perspective these quantities are much easier to be evaluated in a parallel and pipelined architecture, which represents a natural fit for a real-time streaming acquisition system like this one.As shown in figure 3 the four summations can be computed in parallel with identical blocks, based on a BRAM of 1024 memory locations to store intermediate data and an addition operator to sum stored value with the incoming data value.After 50 sequences, the values are divided by 50 and sent to the subsequent pipeline stages.The 8 stages of the pipeline perform terms multiplication and addition/subtraction according to equation (3.1) and (3.2).Final operations are the root square for the standard deviation, and the division by  4 [ ] for the kurtosis.
This architecture is capable of processing one data input per clock cycle.Registration stages are put on purpose in order to synchronize data to the j-th sample, and each pipeline stage has a proper latency in order to have timing requirements met.Two hardware versions have been developed, one with integer fixed point arithmetic operators, and one with single precision floating point arithmetic -3 - operators [5].In table 2 it is shown the difference in resource usage for the complete system using either operator version.With floating point arithmetic there is a larger use of resources, in particular the DSP type, but it is still sustainable for this project.
Due to data payload constraints on bit width, which lead to 16 bits for VLF and VLFe data and 12 bits for HF, the final stage of the architecture implements data casting.For the integer version, data width is reduced according to table 3.For the floating point version two normalization strategies have been tested: a) float to integer conversion, according to the same integer format as before; b) float to a custom-defined float conversion, where the custom floating-point definition is adapted from half precision definition (5 MSB for the exponent) without sign bit and modifying significand width (11 LSB for the 16 bit type, 7 LSB for the 12 bit type).

Figure 1 .
Figure 1.Left: arrangement of all the boards inside the metal rack.Right: block diagram of the connections between the various EFD-02 components, with the 4 Probes (EFP), a Splitter to manage the hot and cold redundand electronics and for each section an Analog Processing Unit (APU), a Digital Processing Unit (DPU) and a Low Voltage Power Supply and Control Unit (LVPS & Control or PWR).

Figure 2 .
Figure 2. Digital Processing Unit internal organization.

Table 1 .
Band division performed by DPU.For VLF, VLFe and HF bands also a 2048-point FFT is generated.Type is reported as output in Burst/Survey acquisition mode that can be different in the VLF bands.

Table 2 .
For the AMD Xilinx xc7z045 device, comparison of percent resource usage between integer fixed point and floating point arithmetic implementations.

Table 3 .
Data format for integer fixed point representation: int.frac indicates the number of bits used for integer part and fractional part of the number.

Table 4 .
The dynamic range is the ratio between the maximum measurable signal in that band and the standard deviation of noise: 20 log 10 (  max  ).Some values are expressed in a range because measures can be different for each channel.