First measurements with monolithic active pixel test structures produced in a 65 nm CMOS process

The Inner Tracking System (ITS) of the ALICE experiment at CERN will undergo an upgrade during the LHC long shutdown 3, in which the three innermost tracking layers will be replaced. This upgrade, named the Inner Tracking System 3 (ITS3), employs stitched wafer-scale Monolithic Active Pixel Sensors fabricated in a 65 nm CMOS process. The sensors are 260 mm in length and thinned to less than 50 μm then bent to form truly half-cylindrical half-barrels. The feasibility of this process for the ITS3 was explored with the first test production run (MLR1) in 2021, whose goal was to evaluate the charged particle detection efficiency and the sensor performance under non-ionising and ionising radiation up to the expected levels for ALICE ITS3 of 1013 1 MeV neq cm-2 (NIEL) and 10 kGy (TID). Three sensor flavours were produced to investigate this process: Analog Pixel Test Structure (APTS), Circuit Exploratoire 65 (CE65) and Digital Pixel Test Structure (DPTS). This contribution gives an overview of the MLR1 submission and test results, describing the different sensor flavours and presenting the results of the performance measurements done with particle beams for various chip variants and irradiation levels.


Introduction
The importance of Monolithic Active Pixel Sensors (MAPS) for use in high energy physics experiment vertex and tracking detectors has been established in the last decade.The most recent implementation of a large-area MAPS detector was for the ALICE Inner Tracking System 2 (ITS2) [1] at CERN, which used the ALPIDE chip [2,3].This chip was fabricated in the TowerJazz 180 nm CMOS process and showed excellent performance in terms of detection efficiency (≫99%) and spatial resolution (about 5 µm).
During the LHC Long Shutdown 3 (2026-2028), the ITS2 will undergo an upgrade called the ITS3, where the three innermost tracking layers will be replaced.The ITS3 employs wafer-scale MAPS with a length of 260 mm that are thinned to <50 µm and bent to radii of 18 mm, 24 mm, and 30 mm to form cylindrical half-barrels.To obtain sensors of this length, a process called stitching is employed.In this process the reticles of the CMOS imaging process are joined together to produce a larger single sensor, removing the need for electrical services in the detector.By utilising the natural stiffness of the cylindrical geometry, the majority of the mechanical support can also be removed, using only carbon foam spacers as support structures.Finally, the very low power consumption (<20 mW/cm 2 ) of the chip will allow the detector to be cooled by air.These reductions in the material within the sensitive volume will enable the ITS3 to have a very low material budget of <0.05% X 0 per layer.Altogether, these upgrades will provide exceptional tracking and vertexing capabilities leading to an improvement in the pointing resolution of the current detector by a factor of two.
Due to the challenging design that the ITS3 poses, the Tower Partners Semiconductor Co. (TP-SCo) 65 nm CMOS imaging process [4] was chosen as the starting point.The first submission in the 65 nm CMOS process, in conjunction with the CERN EP R&D on monolithic pixel sensors [5], was called MLR1 and contains many different test structures to fully explore the CMOS process.

MAPS in the 65 nm CMOS imaging process
By using a smaller CMOS process node compared to the 180 nm CMOS process of the ITS2, more possibilities will be open, such as: • the ability to have complete coverage along the beam axis (z-direction) in the detector with a single stitched sensor produced on 300 mm wafers; • lower power consumption when moving to deeper submicron processes.
However, moving to a new process also provides challenges, such as optimising the design for sensor yield, the charge collection, and testing and verifying the radiation harness.
Three main sensor flavours produced are the Analog Pixel Test Structure (APTS), Circuit Exploratoire 65 (CE65), and Digital Pixel Test Structure (DPTS), each measuring 1.5 mm × 1.5 mm in size and highlighted in Fig. 1.In addition to three sensor flavours, three process options were also explored to investigate the charge collection properties of the CMOS process.These processes, shown in Fig. 2, are called standard, modified, and modified-with-gap and are similar to those used in the 180 nm CMOS process [6].In the standard process, the epitaxial layer is only partially depleted, so some of the charges will undergo diffusion, and this process is expected to have the largest charge sharing.For the modified process, a low-dose n-type implant is added across the length of the pixel.This enables the epitaxial layer to be fully depleted and increases the lateral electric field to the collection diode.Thus, it better collects the signal charge and accelerates the carriers towards the collection diode.This lateral electric field is further increased in the modified-with-gap process where a gap in the low-dose n-implant is added at the edges of the pixel and results in a similar depletion region to the modified process.The main goals of the MLR1 submission were to verify that the detection efficiency was 99% and that the radiation hardness could reach the expected levels for the ITS3 (10 13 1 MeV n eq cm −2 and 10 kGy).

Analog Pixel Test Structure
The APTS incorporates a 6 × 6 pixel matrix with direct analogue readout on the central 4 × 4 pixels.Two versions of the output buffer were implemented: a source-follower (APTS-SF) and a fast operational amplifier (APTS-OA) whose focus was on time resolution.In addition, the sensor was produced in four different pixel pitches ranging from 10 µm to 25 µm.The goal of the APTS was to explore the different sensor designs and processes.
The in-beam measurements of the APTS-SF shown in Fig. 3 (left) demonstrate the impact of the different process types on the detection efficiency.While all three can reach the desired 99%, it is clear that the standard process has a reduced performance at larger thresholds compared to the other two due to the improved charge collection in the modified processes.The modifiedwith-gap process shows the largest detection efficiency over the whole measured threshold range.Comparing the detection efficiency for different pitches, Fig. 3 (right), it can be seen that below a threshold of 200 e -, there is minimal difference among the pitches.However, above this value, larger pitches result in higher efficiencies.Timing measurements were also performed with in-beam measurements of two APTS-OA, resulting in a timing resolution of (77 ± 5) ps, Fig. 4.

Circuit Exploratoire 65
The CE65 is a "large"-area chip consisting of an analogue rolling shutter readout with an integration time of 50 µs.One type of the pixel matrix consists of 64 × 32 pixels implemented with a pixel pitch of 15 µm and split into three subvariants that differ by their in-pixel amplifier: AC, DC or SF.The other type of pixel matrix contains 48 × 32 pixels implemented with a pitch of 25 µm.The goal of the CE65 was to study the pixel matrix uniformity.Figure 5 shows the seed pixel distributions obtained from in-beam measurements of the different CE65 variants.There is a clear distinction between the standard and the modified-with-gap processes, with the latter having a larger most probable value (MPV), signifying a larger charge collection depth.The difference between the amplifiers is minimal for the modified-with-gap process.However, for the standard process, it can be seen that the AC-coupled amplifier has a larger MPV.

Digital Pixel Test Structure
The DPTS features a 32 × 32 pixel matrix with a pitch of 15 µm implemented in the modifiedwith-gap process and contains a full digital front-end with asynchronous readout [7].The sensor is controlled by a set of external reference currents and voltages and read out via a current mode logic (CML) output [8,9].All the pixels are read out simultaneously via a differential digital output that time encodes the pixel position and Time-over-Threshold (ToT).The goal of the DPTS was to study the in-pixel full-digital front end.
The performance of DPTS chips for various irradiation levels taken at a temperature of +20 • C was evaluated using in-beam measurements of positive hadrons at 10 GeV/c, the results of which are shown in Fig. 6.For all irradiation levels, the sensor shows an excellent detection efficiency of 99% and a spatial resolution below the binary resolution (pixel pitch / √ 12) while preserving a fake-hit rate below 10 pixel −1 s −1 .For the detection efficiency, it can be seen that non-ionising irradiation leads to a decrease in detection efficiency while ionising irradiation leads to an increase in the fake-hit rate.For the spatial resolution, there is a negligible impact of the irradiation on the performance of the tested irradiation levels.Whereas the average cluster size shows a slight decrease with increasing non-ionising dose.In-beam measurements using positive hadrons at 10 GeV/c were also used to investigate the cause of the detection efficiency loss in the sensor by measuring the particle hit position within a pixel.The detection efficiency was studied as a function of the reconstructed track position relative to the nearest pixel centre for a sensor irradiated to 10 15 1 MeV n eq cm −2 with a threshold of 160 e -, as shown in Fig. 7.It can be seen that the further the track is away from the collection diode, in the centre of the pixel, the smaller the detection efficiency is, an effect becoming particularly acute in the corners of the pixel.

Summary
The performance of the MLR1 chips was evaluated through extensive characterisation in the laboratory and with in-beam measurement.The measurements show that the MLR1 was a success thanks to the large number of operational prototypes that allow the parameter space of the CMOS process to be mapped out.Furthermore, the MLR1 structures exhibit excellent performance in terms of detection efficiency (>99%) and spatial resolution (3-4.5 µm) from the in-beam measurements for all three sensor flavours considered.The radiation hardness is demonstrated by the sensors maintaining a detection efficiency of 99% for chips irradiated with a dose at the expected ITS3 levels, 10 13 1 MeV n eq cm −2 (NIEL) and 10 kGy (TID).The radiation hardness actually exceeds this goal as the desired performance is maintained even for sensors irradiated up to 10 15 1 MeV n eq cm −2 and operated at +20 • C. In addition, the APTS-OA has demonstrated a time resolution of (77±5) ps.
From the results of the MLR1, the detection efficiency and radiation hardness have been validated and represent an important milestone in the R&D for ALICE ITS3.The next step towards a wafer-scale bent sensor is the second submission in the 65 nm process designated ER1, whose goal is the validation of stitching and yield via the full-scale sensor prototypes.

Figure 2 .
Figure 2. The three process options implemented in the MLR1 chips: standard (left), modified (middle), and modified-with-gap (right).

Figure 3 .
Figure 3.Comparison of the detection efficiency vs. threshold for an APTS-SF sensor for the three processes (left, see text for details) and different pixel pitches (right).

Figure 4 .
Figure 4.The time residual distribution of two APTS-OA sensors fitted with a Gaussian function to extract the timing resolution.

Figure 5 .
Figure 5.The in-beam seed pixel distribution comparing the response of the different CE65 variants.

Figure 6 .
Figure 6.Top: the detection efficiency (filled symbols, solid lines, left axis) and fake-hit rate (open symbols, dashed lines, right axis) vs. threshold.Bottom: the spatial resolution (filled symbols, solid lines, left axis) and average cluster size (open symbols, dashed lines, right axis) vs. threshold.Both plots are for DPTS chips irradiated to various levels [7].

Figure 7 .
Figure 7.The in-pixel detection efficiency for a DPTS sensor irradiated to 10 15 1 MeV n eq cm −2 with threshold set to 160 e -, measured with 10 GeV/c positive hadrons.The grey circle represents the tracking resolution of the telescope used to reconstruct the tracks [7].