Multichannel integrated circuit for time-based measurements in 28 nm CMOS

This paper discusses the application-specific integrated circuit prototype dedicated to readout of hybrid pixel X-ray detectors. The circuit is fabricated in 28 nm CMOS technology and occupies 1.1 × 1.1 mm2 of silicon area. Each of 8 × 4 pixels present in the prototype includes an analog front-end and a digital block with two ring oscillators and their supporting circuits. The circuit can operate in single-photon counting mode or time-based measurement mode. The paper discusses in detail the design decisions that influenced the final in-pixel ring oscillator architecture and layout. Measurement results are presented which demonstrate the performance of ring oscillators as well as regular operating modes of the chip: single photon counting and time-over-threshold measurement.


Introduction
The scientific community continues to push forward the requirements and state of the art for hybrid pixel X-ray detectors to make them suitable for a wide range of experiments across different domains, such as medicine, electron microscopy, antimatter research and solid-state physics.Depending on the character of a given experiment, techniques such as single-photon counting (SPC) may be applied, in which photons of given energy are counted.This technique may be extended to multiple discrimination levels or in-pixel analog-to-digital conversion to provide spectral resolution.Another branch of experiments requires precise timing information, especially Time-of-Arrival (ToA) and Time-over-Threshold (ToT), when the first one gives information about a time span between the occurrence of a common trigger and the moment the photon hits the detector, while the second one measures the output front-end amplifier pulse width at a given threshold, allowing for indirect photon energy computation.Application-specific integrated circuits dedicated to detector readout, which provide such time measurement capability, are continuously developed and have found applications in various fields of science [1][2][3][4][5][6][7][8].
This article is a continuation of our work on the design and characterization of a multichannel integrated circuit dedicated for time-based measurements, fabricated in 28 nm CMOS technology [9,10].On the following pages, it focuses on discussing the design of in-pixel ring oscillators, introducing measurement results aimed at correction of front-end paremeters using different criteria and comparison of SPC mode versus time-based mode of operation.
The article is organized as follows.Section 2 includes a brief overview of the chip architecture, the available modes of operation and the structure of the recording channel.It also describes the schematic-and layout-level design of in-pixel ring oscillators.Section 3 presents the measured ring oscillator frequency control characteristics.It also introduces measurement results for two regular modes of chip operation.Section 4 concludes the article.

Chip description
The chip consists of 8 × 4 square pixels with 50 µm pitch, and has dimensions of 1.1 × 1.1 µm 2 .Each pixel contains the analog recording channel, two ring oscillators, several counters (37 bits in total), and asynchronous digital circuits, which together with oscillators and counters, form a Vernier time-to-digital converter (TDC).

Recording channel
The detailed description of a recording channel of the designed chip can be found in [10].Its simplified schematic is shown in figure 1.It consists of a front-end amplifier with capacitive feedback and Zimmerman feedback [11,12].The feedback capacitance is controlled using GAIN<0:1>, while the effective feedback resistance is controlled using the FEED<0:5> configuration bits.The amplifier is AC-coupled to the discriminator, whose input DC level is set by an external  TH1 voltage.Discriminator offset can be corrected using two methods: either by controlling the current flowing through R TH2 resistor by using I_CTR<0:5> configuration bits, or by controlling the number of input unit transistors on one of the discriminator inputs (SELD).In the current prototype, the recording channel is equipped with calibration circuitry (CAL).It allows the application of voltage pulses with externally controlled amplitude (using calP and calN pads) to the internal 3 fF capacitance.This enables simulating the occurrence of events of photons (with different energies) hitting the sensor.
The chip is capable of working in two basic modes of operation.The first is a single photon counting (SPC).In this mode, pulses at the output of the front-end amplifier are compared with the threshold set at the input of the discriminator.If the pulse crosses the threshold, the digital pulse occurs at the output of the discriminator, and it is counted by the digital circuitry.To characterize the front-end in this mode, usually a so-called "threshold scan" is performed (figure 2a), in which the discriminator threshold voltage is swept in a wide range and for each value of this voltage a known number of calibration pulses are generated.The effect of such a scan is a curve from which the -2 - The second mode of operation is the time measurement mode.This chip uses a single in-pixel ring oscillator to measure Time-over-Threshold (ToT), that is, the time during which the signal at the output of the front-end amplifier is above the discriminator threshold (figure 2b).In the final application, this mode's purpose is to measure the energy of photons hitting the detector.There is also another time-related parameter, Time-of-Arrival (ToA) -the time that elapses from the common trigger signal to the moment the photon hits the detector.This parameter usually has stricter accuracy requirements than ToT, and that is why the Vernier Time-to-Digital converter [13] has been implemented using two in-pixel oscillators.This TDC is aimed at measurement of ToA [14].
This remaining part of this paper mostly focuses on the design, simulations, and measurement of ring oscillators, as being one of the core blocks determining time measurement accuracy.

Oscillator overview
To implement Vernier TDC in all pixels, each of them includes two independent ring oscillators.Such an application imposes several tight requirements, including: reducing the area consumption to no more than tens of square micrometers per oscillator with all supporting in-pixel callibration circuits, guaranteeing reasonable power consumption, provided that the operating frequency on the order of several gigahertz is expected, and minimizing jitter to provide sufficient time measurement accuracy (tens of picoseconds for ToA mode).Taking into account power and area consumption requirements, a three-stage ring oscillator with current-starved gates (NAND gate for enable signal and two inverters) was chosen.In 28 nm CMOS technology, this means that the core of the oscillator can be squeezed into the area of approximately 4 µm 2 , which leads to significant oscillator frequency mismatch between channels.To address this problem, several techniques were implemented: • The oscillators were divided into two groups: "slow" oscillators and "fast" oscillators.Oscillators in each group share one of two respective global 8-bit DACs for coarse frequency control • Each oscillator is accompanied by its own local 6-bit DAC, which, together with global 8-bit DAC, limits the current flowing into the oscillator core from the power supply line -3 - • Load capacitance of each of three internal oscillator nodes can be controlled using a set of MOS switches connected to MOM capacitors An additional issue addressed by the oscillator design is that the voltage signal swing at the output of the three oscillator stages is limited to about half the oscillator power supply voltage and the buffered signal duty ratio is significantly lower than 50% with typical buffers.To deal with this, an output of each stage is buffered by a skewed inverter.

Oscillator schematic
The oscillator schematic is shown in figure 3, and the parameters of the transistors visible in the schematic are summarized in table 1.The oscillator core consists of M 1 -M 8 transistors.Ultra-low  T transistors were selected to minimize the power consumption-to-frequency ratio.Transistor dimensioning was selected in the iterative process with multiple simulated versions of layout, taking into account power consumption, jitter, and frequency control range achieved using the capacitance bank.This capacitance bank consists of three (one per each oscillator phase) groups of binary-scaled MOS switches (M 12 -M 14 ) and custom-made MOM capacitors.The LSB switch uses the minimum possible dimensions.Each output stage is buffered by the skewed buffer, consisting of M 15 and M 16 transistors.This buffer uses ultra-high  T for the PMOS transistor and ultra-low  T for the NMOS transistor, which results in the duty ratio 50% of its output signal in the nominal corner, while reducing its gate area by approximately 30%.Finally, M 9 -M 11 transistors are a part of current mirrors controlled by global and local DAC.Their dimensioning, as well as bitness of DACs was selected to ensure, together with capacitance banks, a sufficient frequency control range and resolution.References for global and local DACs are available externally on chip pads; therefore, their current range can be changed by the user.
-4 - All oscillators, together with their frequency control circuits, are connected to a separate power supply domain,  DDR , independent of the supply of the analog front-end and digital circuits (both of which are also separated).Therefore, this voltage may also be used to roughly pre-set the range of oscillator operating frequencies.

Oscillator layout
Oscillator layout design decisions took into consideration: • the requirements of low power and area consumption as a direct consequence of putting two oscillators in each pixel • the need to separate oscillators (and digital circuitry) from the analog part of the pixel to not degrade front-end parameters • the need to provide good-quality power supply for the oscillators to maintain stable frequency over time To achieve these goals, three power supply domains were separated (analog, oscillators with their supporting circuits, and digital).Additionally, the pixel was divided into three vertical sections: analog part placed directly on the substrate, oscillators and their DACs put in separate deep N-well, and digital part (logic, coincidence circuit, counters, and configuration register) placed in a second deep N-well.Significant amount of work was focused on minimization of area consumption of the circuits to make as much area as possible in the pixel for the decoupling capacitors.The layout of the pixel, with oscillator-related circuits zoomed in, is shown in figure 4. The oscillators are placed in the center of the pixel, neighbored by local DACs and surrounded by decoupling capacitors on three sides.On the right side there is a digital part, isolated by 3.5 µm distance beetween deep N-wells.The oscillator core occupies approximately 3.5 µm 2 of area and is accompanied by a capacitance bank with similar area, consisting of three blocks.Finally, the layout of individual custom-made MOM capacitances is presented.These were iteratively refined in series of layout (re)design, extraction and post-layout simulation cycles to achieve the best oscillator frequency control linearity, desired control range and granularity.

Capacitance bank layout design considerations
Before finalizing the capacitance bank layout in the form shown in figure 4(e), multiple alternatives were considered.The basic principle was to be able to connect additional capacitances between each of the oscillator output nodes and the ground using some kind of switch.At the beginning of the process, the design was proposed in which the switch was implemented as a transmission gate and the capacitance consisted of two complementary MOS transistors connected as capacitors [15].Soon it became clear that the capacitance added to the oscillator nodes with such a solution was too large, limiting the achievable frequency to 2.5 GHz in post-layout simulations or requiring significant increase of power to push this frequency range to higher values.Therefore, to reduce the minimum -6 -added capacitance, transmission gates were replaced with single NMOS switches, and the MOS-based capacitance approach has been abandoned in favor of custom-made MOM capacitors.Some of the considered configurations (called V1, V2, and V3) are illustrated in figure 5.The first version (V1) is the closest to the final version.It differs from V2 and V3 in that one of the metal capacitor plates is always connected to the ground, while in the other two the capacitance is placed between the oscillator output node and the drain of the NMOS switch transistor.V2 and V3 differ in the area of MOM capacitors -this comparison was inspired by the simulation results obtained for V2.The general conclusion is that for such small MOM capacitors, the effective capacitance seen from the oscillator output node is dominated by the parasitic capacitances of MOS transistors.As a result, the capacitance of LSB (C 0 ) is visibly small.For more significant bits, MOS capacitances are reduced by connecting drain areas of neighboring fingers, so respective MOM capacitances have to be larger to provide linear frequency control characteristics.To draw further conclusions, post-layout simulations have been conducted for each of three layout variants.The result is visible in figure 6 The oscillator output frequency was plotted as a function of the global 8-bit DAC control word, for each of 8 possible combinations of the capacitance bank switches' settings and for each of the layout variants considered.The results show that V2 -although resulting in the highest achieved frequency -does not provide any reasonable control range.Increasing the capacitance of MOM capacitors (V3) also does not make the result satisfyingly better.The only acceptable choice is V1, that is, the variant in which the maximum achievable frequency is a bit smaller, but the control range is at least several times wider than in the other two variants.As a result of these simulations, it was decided that the MOM capacitor will be put between the source of the MOS switch and the ground in a configuration that minimizes the number of vias (metal 2 connected to the ground and metal 1 connected to the MOS switch).

Measurement results
The photograph of the chip is shown in figure 7. It is connected by wire bonds to the PCB.Digital I/O communication with the chip configuration and data registers, as well as the generation of analog voltages for the setting of thresholds and the front-end calibration circuit, is realized using the NI-USB 6341 card.

Frequency control of oscillators
To enable oscillator frequency calibration, the chip has the possibility to connect external digital signal with known pulse width.To characterize oscillators, 1 µs-wide pulses were generated.The measurement results of the frequency control characteristics of an exemplary oscillator are shown in figure 8(a).To obtain these characteristics, the global DAC was set to code 31 to set the oscillator frequency range around 4 GHz at  DDR equal to 1 V.Then, three remaining independent parameters were controlled.First, two different values of the supply voltage  DDR were used in the tests: 1 V and -8 -0.65 V. Second, a three-bit capacitance bank was used to control the loading of internal oscillator nodes (cap_ctrln<2:0>).Third, 6-bit, per-oscillator, local DAC was used to control the current of current-starved gates (dac_wordn<5:0>).Furthermore, power consumption was assessed in post-layout simulations (figure 8(b)) and it was confirmed that the results closely match the power value measured at the frequency 4 GHz.

Recording channel characterization
To characterize the recording channel, analog front-end offset correction was performed as a first step, based on threshold scan results and using two offset control methods described in section 2.1 [10].
Next, two procedures of analog front-end configuration correction were performed: • threshold scans were measured in which configuration settings responsible for setting the amplifier gain were being changed.Based on these results, an optimal setting of GAIN<0:1> and FEED<0:5> was selected to minimize the spread of the gain across the channels for the selected value of the calibration pulse amplitude.
• ToT was measured for the parametric sweep of the same parameters as in the previous case.Based on that result, optimal settings were selected to minimize the measured pulse width spread between channels for the same "photon energy" simulated by the calibration circuit.
Having prepared in such a way two sets of analog front-end parameters, optimized using different criteria, measurements were done to compare the performance of single photon counting (ability to count photons of selected energy, depending on the gain uniformity) as assessed from the threshold scans.Next, measurements were made to determine the accuracy of the time measurement (ToT), which relies on the ability of a front end to output voltage pulses with the same pulse width as a response to the identical injection of charge from the calibration pulse in all channels.

Threshold scan measurement
Figure 9 illustrates the results of threshold scan measurements (performed according to principles introduced in figure 2a), where measured signal amplitude is plotted against the charge injected through  -10 -

Time-over-Threshold measurement
In time-based mode tests, ToT was measured as a function of the effective charge injected through the calibration capacitance.To obtain the results presented, the frequency of the oscillators was set at 4 GHz. Figure 11

Conclusion
The presented results indicate that the proposed architecture of the analog front-end is capable of amplifier output signal shaping with pulse widths on the order of several to dozens of nanoseconds, which makes it a promising choice for applications with large beam intensities.The results of the low-area and low-power in-pixel ring oscillator architecture measurements show the effectiveness of implemented techniques, namely: careful design of capacitance bank with custom MOM capacitances, using skewed buffers, layout parasitics optimization, and cross-talk reduction using separate deep N-wells for analog part, oscillators, and digital part.Combining the techniques discussed allowed for ToT measurement with 0.25 ns time step and approximately 1.2 ns standard deviation.Comparison with threshold scan measurement results shows that each use case (amplitude measurement using threshold scans and ToT measurement using the ring oscillator) requires separate analog front-end configuration optimization to minimize mismatch between channels.Further work will be focused on ToA characterization, investigating sources of current non-idealities in ToT characteristics, and applying the conclusions in the second circuit prototype.

Figure 1 .
Figure 1.Schematic of the recording channel followed by digital part of the chip with oscillators.

Figure 2 .
Figure 2. Illustration of measurement principle for two basic chip operation modes: (a) single photon counting and threshold scan-based front-end characterization, and (b) time measurement (ToA and ToT).

Figure 3 .
Figure 3. Schematic of ring oscillator with frequency callibration circuits.

Figure 4 .
Figure 4. Layout of pixel with ring oscillator components marked: (a) pixel area with oscillators and their supporting circuits in the center, (b) oscillators, 6-bit DACs and their surroundings (decoupling capacitors and digital part of the pixel), (c) oscillator and capacitance banks: 1 -oscillator core, 2 -capacitance bank, 3 -buffer of dEnable signal, 4 -skewed buffers, (d) capacitance bank with three phases shown, (e) zoom at single oscillator phase capacitance bank with custom-made MOM capacitors marked.

Figure 5 .
Figure 5. Selected three of considered versions of capacitance bank layout.

Figure 6 .
Figure 6.Oscillator frequency control postlayout simulations for three versions of capacitance bank layout as a function of global 8-bit DAC word.Different colors mean different setting of capacitance bank control word.

Figure 7 .
Figure 7. Photograph of the chip with wire bonds visible.

Figure 8 .
Figure 8. Performance of an exemplary oscillator: (a) measurement of frequency control characteristics and (b) corresponding post-layout power consumption results.

Figure 9 .
Figure 9. Amplitude measurement result computed from threshold scans and plotted against effective charge value for two analog front-end parameter correction methods: (a) amplitude-based (from threshold scan), and (b) time-based (from ToT).

Figure 10 .
Figure 10.Gain histograms computed from threshold scans for effective charge value equal to 4500 e − for two analog front-end parameter correction methods (amplitude-based and time-based).
(a) shows the results of the time-based correction of the AFE parameters.The histogram of the spread of ToT measurement between the channels for a charge equal to 9.4 ke − is shown in figure 11(b).The average value of ToT values presented on this histogram is 12.3 ns with  = 1.17 ns (or, when the outlier case visible in figure 11(b) is excluded from the statistics, the average ToT value is 12.1 ns with  = 0.48 ns).

Figure 11 .
Figure 11.ToT measurement result for time-based analog front-end parameter correction: (a) ToT plotted as a function of charge injected through calibration capacitance.The area around each point is a standard deviation for 200 repetitions per point.(b) ToT histogram for charge equal to 9.4 ke − .

Table 1 .
Parameters of transistors presented in the schematic of the ring oscillator.