Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.


Introduction
In modern and newly designed particle physics detection systems, there is a growing demand for detectors with ever-increasing speed, high granularity, and high channel density.The key part of such a detector is a dedicated multi-channel readout Application-Specific Integrated Circuit (ASIC), which has gained increasing functionality in recent years, slowly becoming a System on Chip (SoC).In particular, the speed of signal processing is increasing; each channel is required to measure the amplitude or time (or both) and convert the result to a digital form.As the number of bits of information increases, so does the demand for faster data transmission.With the above requirements and increasing channel density, ultra-low power consumption per channel is a must.
A fast, ultra-low power, area-efficient Analog-to-Digital Converter (ADC) is one of the indispensable components of a SoC-type readout ASIC.An ultra-low power ADC with a sampling rate of 40 MSps or more, medium-high resolution, and small pitch is required for multi-channel readout ASICs in modern and future LHC or other experiments.Recent developments of such complex readout ASICs are a 128-channel SALT ASIC for the LHCb Upstream Tracker, which contains an analogue front-end and a 6-bit 40 MSps ADC in each channel [1], or a 72-channel HGCROC ASIC for the CMS High Granularity Calorimeter, which contains an analogue front-end, a 10-bit 40 MSps ADC and a precision TDC in each channel [2].In fact, a fast 10-bit ADC is one of the most requested and used blocks in the readout of various detector systems [2][3][4][5][6].These and other readout ASICs for LHC and other experiments have been developed in the 130 nm CMOS process, which has been studied in the past and selected for use in High Energy Physics (HEP) experiments many years ago due to its very good performance and good radiation tolerance [7].
For medium-and long-term future experiments, newer CMOS processes will be used, not only because of the higher speed, density, and lower power, but also because of the limited availability in time of current technologies.One of such technology that has already been verified, also in terms of radiation hardness, is the 65 nm CMOS process [8].Several developments of complex readout ASICs in CMOS 65 nm have already started [9][10][11] and this process will be dominant for the next 5-10 years until a newer one, probably CMOS 28 nm, will take place.For the highest density ASICs, e.g.pixel detectors, the transition to 28 nm CMOS will be much faster.
The aim of this work is to develop a fast, ultra-low power ADC in CMOS 65 nm, ready for integration into a multi-channel readout ASICs for future experiments.The main goals for ADC are: a sampling rate of at least 40 MSps (but possibly significantly higher), 10-bit resolution, ultra-low power consumption of around 500 μW at 40 MSps, small pitch per channel below 100 μm, and easy implementation in a multi-channel readout ASIC.

ADC design
The demand for ultra-low power ADC naturally leads to a Successive Approximation Register (SAR) architecture with a capacitive Digital-to-Analog Converter (DAC), shown in the block diagram in figure 1.A fully differential ADC architecture was chosen, comprising a pair of bootstrapped switches, a differential capacitive DAC, a dynamic comparator, and asynchronous control logic [12].Moreover, the control logic was implemented as dynamic to increase the speed of the ADC and, at the same time, to reduce power consumption.Due to technological limitations in minimum capacitance available in the Process Design Kit (PDK), a split DAC architecture with split capacitor   was used to reduce the DAC input capacitance.As a result, the effective unit capacitance is much lower than the minimum physical one used in the DAC design.For additional power savings, all blocks were designed to dissipate power only during conversion, eliminating all static power.Asynchronous logic was used to increase speed and eliminate the fast bit-cycling clock distribution, greatly simplifying the design of a multi-channel ASIC and significantly improving the power budget.
To explore and optimise ADC performance, several versions of SAR ADC have been developed.The ADCs differ in the DAC switching scheme, the implementation of the DAC capacitors, and the power dissipated by the SAR logic.All ADC versions use the same bootstrapped sampling switch [13,14] and dynamic comparator [15].The designed comparator, shown in Figure 2, consists of two gain stages and an output latch.To symmetrise the circuit and minimise the effect of parasitics, a decision stage (generating the Valid signal) was added to the comparator core.

Switching scheme and DAC
Numerous DAC switching schemes have been proposed for SAR ADC to achieve the highest power efficiency [16].In this work, two very efficient schemes have been used.The first one, the Merged Capacitor Switching (MCS) scheme [17,18] shown in figure 3 (left), uses three reference voltages Vref+, Vref-, Vcm, but the accuracy of the DAC does not depend on the accuracy of the reference common voltage Vcm.Another great advantage of this scheme is that the DAC output common voltage is constant and equal to Vcm during conversion, which makes comparator operation easier.In the sampling phase, all DAC switches are connected to the Vcm voltage (as shown in figure 3 (left)).After the first decision of the comparator, the upper/lower MSB switch (connected to 32 C) of DAC changes to Vref+/Vref-or Vref-/Vref+ depending on the result of the comparison.Such changes occur after each bit has been converted, so that at the end of the conversion there is no switch connected to Vcm.
The second switching scheme shown in figure 3 (right), called HL (HighLow) for brevity, is a modification of the scheme proposed by Sanyal and Sun [19].The difference from this scheme is the use of Vref+, Vref-voltage references for all bits down to the least significant one, and omitting an additional common-mode reference Vcm.The consequence of not using Vcm is an additional capacitive branch of DAC, and thus doubling of the DAC capacitance.A disadvantage of this scheme is that the DAC output common mode voltage is not constant during conversion.In the sampling phase, all DAC switches, except the MSB bit, are connected to the Vref+ voltage, Block diagram of differential 9-bit DACs with the MCS switching scheme (left) and the HL switching scheme (right).There are two types of capacitors available in the 65 nm CMOS process, MIM and MOM, so each version of DAC has been implemented using both of them.The MIM capacitor has a higher minimum value than the MOM, but its advantage is a lower parasitic capacitance of the top plate.The MIM DAC was designed with a 6-bit sub-DAC for the most significant bits and a 3-bit sub-DAC for the least significant bits, as shown in figure 4 (left).The MOM DAC, for which a smaller minimum capacitance was available, was designed with a different split, using a 7-bit sub-DAC for the most significant bits (using 64 C in the MSB branch) and a 2-bit sub-DAC for the least significant bits (using 2 C in the MSB branch).The comparison of both DAC splits is shown in figure 4; for the sake of clarity, only half of the DAC is presented.

Asynchronous SAR logic
The asynchronous design allows individual control of the time of subsequent conversion steps, providing the ability to find the best trade-off between effective ADC resolution and speed.In the first phase of the ADC operation, the sampling of the analogue input signal is performed in capacitive DAC.Then the main phase, analogue-to-digital conversion, is started.The sequence, which is repeated for each bit conversion, consists of the following steps: During the last bit conversion, after step 2, the DAC is reset to the initial configuration and ADC is ready for the next conversion.Although steps 1 to 3 should be as fast as possible, the duration of step 4 can be optimised to find a compromise between a long enough settling time sufficient for the required ADC precision and the shortest possible time for the fastest ADC conversion.Since the required precision (and thus the settling time) is the highest for the MSB bit and the lowest for the LSB bit, the duration of step 4 can be optimised separately for different bits.
To achieve the best compromise between the highest effective resolution and the highest conversion rate, a variable delay has been introduced that adjusts the settling time of DAC.It may be optimised separately for different groups of bits, similar to what was done in [20].The concept of this solution is shown in figure 5.There are four delays for four groups of bits: one for the most significant bit 9, denoted Del9, the second for bits 8-7, denoted Del87, the third for bits 6-5, denoted Del65, and the last for the remaining bits 4-0, denoted Del40.During conversion, the 2-bit Sel_Group signal selects the appropriate delay for the subsequent bit.Each of these delays can be set to eight different values (typically longer for more significant bits) controlled by a 3-bit register.The delays should be set experimentally to achieve the best performance of the given ADC prototype, and can be reused for all ADCs from the same production batch.
The SAR logic of the MCS and HL ADCs is very similar but adapted to correctly control the switches to Vref+, Vref-, Vcm in the MCS version and the switches to Vref+, Vref-in the HL version.As the SAR logic is the largest contributor to the ADC power consumption, two versions of asynchronous control logic have been designed, focusing on the lowest power or the highest sampling rate.For the lowest power version, an additional condition was set to achieve a minimum sampling rate of 40 MSps.The logic implemented in both versions is functionally the same; the only difference being the transistor sizing.

Design summary and layout
In total, eight different SAR ADC versions were designed that differed in: DAC switching scheme (MCS, HL), DAC capacitor type (MIM, MOM), and standard or low-power (lp) consumption.The prototype ADCs were fabricated in 65 nm CMOS technology, which has been proven to be a radiation hard technology.An additional basic precaution has been taken in the design of not using transistors of minimum size to improve ADC immunity to radiation damage.

MOM version
One of the key design tasks was to draw a layout of capacitive DAC that would guarantee good ADC linearity.To achieve this, the guidelines listed below were followed.
1. First, it is crucial to minimise parasitic capacitance seen from the LSB subDAC top plate (see figure 1) to all constant potentials, as this parasitic directly degrades the DAC linearity.
2. Next, you need to ensure that the values of all parasitic capacitances, parallel to subsequent capacitors in DAC, scale proportionally to them to maintain binary weighting.
3. Finally, the parasitic capacitance seen from the top plate of the MSB subDAC to any constant potential should be reduced, but only in a way that does not affect the previous optimisations, since this parasitic only reduces the ADC input range, but has no effect on the DAC linearity.
The ADC layout was drawn in 60 μm pitch to facilitate the implementation of a multi-channel readout ASICs.The size of ADCs with MIM DAC is 330 μm × 60 μm and with MOM DAC 235 μm × 60 μm, as shown in figure 6.The blocks from left to right are: bootstrap switches, capacitive DACs, comparator, switches to reference voltages for subsequent DAC bits, and SAR control logic.

ADC measurements
A dedicated FPGA-based setup was built as shown in figure 7 to characterise the performance of ADC prototypes.The Agilent B1500 semiconductor parameter analyser delivers the power supply, reference voltages, and measures the corresponding currents.It also generates input signals for static measurements.The Agilent 81160A generates the sampling clock and input signals for dynamic measurements.The data acquisition system was built based on the Xilinx Virtex-5 FPGA incorporated into the Genesys evaluation board.
Using this setup, standard static measurements, that is, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL), as well as basic dynamic metrics, that is, Signal-to-Non Harmonic Ratio (SNHR), Total Harmonic Distortion (THD), Spurious-Free Dynamic Range (SFDR), Signalto-Noise-and-Distortion ratio (SINAD), and Effective Number of Bits (ENOB), were obtained.Due to the limitations of the setup, the dynamic metrics were measured at the 0.1 Nyquist input frequency, so the effective number of bits at lower input frequencies, called ENOB LF was calculated.

Internal delay optimisation and static measurements
In the first series of measurements, the static DNL and INL errors were measured at a sampling frequency of 10 MHz for different settings of ADC internal delays.The delays for each group of bits were tuned to achieve the best ADC performance, with the goal of eliminating missing codes (not always possible) and obtaining the best compromise between acceptable DNL, INL errors (it was not always possible to get it below 1 LSB) and the shortest possible delays.
After optimisation, performed separately for each ADC version, the internal delays were set as shown in table 1.These settings were used for all the following measurements.It should be noticed that unit delays of standard and low power versions are different, so the delay settings cannot be compared directly.
The results of DNL and INL errors obtained for all ADC versions are shown in figures 8 and 9 respectively.
Analysing the results, one can observe several features.
• Analysis of table 1 allows to formulate some tentative conclusions.The MCS-MIM configuration is expected to be the fastest as its total delay is the smallest.Furthermore, there is potential room for future improvements in ADC performance by shortening delays because some less significant bits (mainly Del65 and Del40) have delays set to zero.On the other  hand, Del9 for the HL-MIM-lp version is 7, suggesting that the maximum delay is too small and results in many missing codes (DNL< −0.9) as seen in figure 8.
• ADCs with the HL switching scheme show worse linearity (spikes in INL and DNL) than the MCS versions, for which both INL and DNL errors show good performance remaining always below 1 LSB.For ADCs with the HL switching scheme, except for HL-MOM, there are always one or two missing codes and one or two codes with absolute INL or DNL errors  The comparison of SINAD and ENOB for all ADC prototypes (except HL-MIM-lp and HL-MOM-lp) is shown in figure 11.The HL-MOM-lp ADC version is not shown and will not be used in future studies because its effective resolution is 1-2 bits worse than for other versions shown.The HL-MIM version of the ADC, although it has worse non-linearity errors, shows ENOB LF like the other versions.The two codes with worse INL and DNL errors do not significantly affect ENOB LF for this version.As expected, the standard versions of ADC are much faster than the low-power versions.In fact, MCS-MIM has an ENOB LF of 8.9 bits up to 90 MHz, while the HL-MIM and HL-MOM versions have an ENOB LF of more than 9 bits up to 80 MHz.The best versions of the low-power ADCs, MCS-MOM-lp and MCS-MIM-lp keep ENOB LF above 9 bits up to 50 MHz.

Power consumption
Power consumption was measured for different ADC versions as a function of the sampling frequency, up to the frequencies at which the ADC performed well (lower for low-power versions of the ADC).Contributions to the total power of key ADC blocks are presented in figure 12 for the MCS-MIM and MCS-MIM-lp ADC versions.As expected, the power consumption is proportional  to the sampling rate, and the different power contributions of the MCS-MIM and MCS-MIM-lp versions overlap, except for the digital part (and so the total power).Total power is extremely low, reaching 1 mW at about 80 MHz sampling frequency for MCS-MIM ADC.About two-thirds of the total power comes from the digital ADC part, while less than a third comes from the analogue part (comparator and bootstrapped switches), and the smallest contribution comes from the reference voltages.
The comparison of the total power for different ADCs is shown in figure 13.Two groups of straight curves are clearly visible, the curves for standard and low-power ADCs.The power consumption of standard ADC versions is slightly above 500 μW at 40 MHz sampling frequency and slightly above 1 mW at 80 MHz.The low-power ADCs are slower and work well up to about 55 MHz sampling frequency, but their power consumption at 40 MHz is only about 400 μW, more than 20% less than the standard ADCs.

The ADC figure of merit
Using the effective ADC resolution and the power consumption, the well-known Walden ADC Figure of Merit (FOM) [22] can be calculated:

Comparison to the state-of-the-art
In table 2 the key parameters of the standard (HL-MOM) and low-power (MCS-MOM-lp) ADC versions are compared with the state-of-the-art ADCs with the same resolution and similar sampling rates (but at least 40 MSps), designed in similar size CMOS technologies.The FOM LF of the state-of-the-art ADCs is between 15-30 fJ/conv.-stepand the designs presented in this work also stay well in this range.This is due to the fact that the most important parameters, such as power/frequency or effective resolution, obtained in this work are similar to the state-of-the-art ADCs.Furthermore, the ADC size (plus small pitch) of this work compares very well with other designs, which is particularly important considering applications in multi-channel ASICs.Since all the above designs strive to achieve maximum speed with minimum power and minimum area, this comes at the cost of the resulting ENOB, which is noticeably lower (at least 0.7 LSB) than the nominal (10 bits).

Conclusion
The design and measurements of a fast ultra-low power 10-bit SAR ADCs in CMOS 65 nm process have been presented.The measurements performed confirm very good ADC functionality, reflected in ENOB LF of about 8.9-9.1 bits up to maximum sampling frequencies of 80-90 MHz, ultra-low power of about 1 mW at 80 MHz, and excellent FOM LF of 24-26 fJ/conv.-step at 80 MHz.The low-power ADC versions work well up to about 50 MHz sampling frequency, achieving an ENOB LF of about 9.3 bits at 40 MHz with a power consumption of about 400 μW, corresponding to very low FOM LF below 16 fJ/conv.-step.Measurements have shown that the prototype ADCs are fully functional with both the MCS and HL switching schemes, although the MCS version is more robust to non-linearity errors.The designed ADCs are ready for implementation in multi-channel readout ASICs.
One of the ADCs (MCS-MIM version) has already been implemented in the monitoring subsystem of the Low Power Giga Bit Transceiver (lpGBT) ASIC [28], the common serialiser/deserialiser device for the Large Hadron Collider (LHC) detectors.As this application does not require high sampling rates, while the design was added directly to the production version of the lpGBT before the ADC prototype was available and verified, in the actual implementation, for safety, the asynchronous SAR logic was replaced by an automatically synthesised synchronous control logic.The lpGBT tests confirmed the very good performance of the ADC and showed that it works correctly during irradiation up to at least 3.8 MGy dose [28].

Figure 1 .
Figure 1.Block diagram of a fully differential 10-bit SAR ADC with split DAC architecture.

Figure 2 .
Figure 2. Schematic diagram of the dynamic comparator

Figure 4 .
Figure 4. Comparison of DAC split used for MIM (left) and MOM (right) capacitors; for the sake of clarity only half of the DAC in MCS is presented (in HL the Vcm is omitted).

Figure 5 .
Figure 5. Simplified block diagram of the variable delay block.

Figure 6 .
Figure 6.Layout of the ADC with MIM (top) and MOM (bottom) DAC.

Figure 7 .
Figure 7. Setup for static and dynamic ADC measurements.

Figure 8 .
Figure 8. DNL error for all ADC versions measured at 10 MHz sampling frequency.

Figure 10 .
Figure 10.Measurement of dynamic ADC metrics in function of sampling frequency at 0.1 Nyquist input signal frequency, for the MCS-MIM ADC version.

Figure 11 .
Figure 11.Comparison of SINAD and ENOB as a function of sampling frequency for different ADC versions.

Figure 12 .
Figure 12.Contributions to power consumption as a function of sampling frequency for the standard MCS-MIM and the low-power MCS-MIM-lp ADC versions.

. 1 )Figure 13 .Figure 14 .
Figure 13.Comparison of total power consumption as a function of sampling frequency for different ADC versions.

Table 1 .
Optimised internal delay settings for all ADC versions.

Table 2 .
Comparison with the state-of-the-art ADCs.
a Power consumption of the reference voltage is not included (either external or internal).