Recent developments in the IGNITE project on front-end design in CMOS 28-nm technology

The IGNITE project (INFN Ground-up INITiative-on micro-Electronics developments) is developing solutions on integrated micro-systems aimed at the next generation of high-luminosity experiment at the LHC. A test ASIC, designed in CMOS 28-nm technology and named Ignite-0, has been submitted for fabrication. It integrates circuital solutions suitable for pixels with timing having a pitch ranging from 45 to 55 µm. The present paper describes the criteria used in the design choices, and the expected ASIC performance as output from post-layout simulations. Perspectives on subsequent design work on 4D-tracking devices following the Ignite-0 development are also briefly described.


Introduction
Vertex detectors of the next generation of collider experiments will have to cope with an increased amount of tracks per event.To solve the problem of event pile-up, trackers must operate with pixel sensors having high space-time resolution.Typical requirements are space resolutions of about 10 µm and time resolutions below 50 ps rms per hit [1].Such time resolution requirement includes all the jitter contributions of the read-out chain, summarized as: where  sens is the sensor r.m.s.time resolution,  AFE the analog front end jitter,  TDC the conversion time resolution, and  clk is the jitter of the system mater clock, also acting as time reference.The time resolution requirement must be satisfied also while the system devices accumulate increasing Total Ionizing Dose (TID), causing a gradual drift of the device performance towards worse operation corners.Consequently the system must be designed with suitable performance margins.Furthermore, the system must operate at high input hit rates (hundreds of kilohertz per pixel), while keeping the total power density under control, typically around 1.5 W/cm 2 , and preferably less, which typically corresponds to a power budget per pixel of less than 25 µW.
In the framework of the IGNITE project, we are developing a tracking system for future highluminosity experiments, implementing high resolution timing facilities at the level of each pixel (4D-tracking).The system under development integrates timing sensors, front-end ASICs and readout ASICs for high-bandwidth optical data transmission, exploring 3D integration solutions, based on the use of Though Silicon Vias (TSV) Face-to-Face (F2F) and Face-to-Back (F2B) bonding techniques.
The system ASIC is based on an elementary structure, an 8 × 8 pixel tile (shown in figure 1(a)), with an analog front-end (AFE) and one time to digital converter (TDC) per pixel.The tile is surrounded by service spaces, separately for analog and digital circuits, and for biasing as well.Tiles can be assembled to create larger structures.In particular, they will be replicated in a 4 × 4 structure to create a larger 32 × 32 matrix.This new structure will have the periphery for wire-bonding on two sides, and buttable on the remaining two sides.The empty spaces between one basic 8 × 8 pixel tile and the adjacent ones can be used for global services, for routing and for TSV insertion.
-1 -  The 32 × 32 matrix structure can in turn be used to create a 64 × 64 pixel matrix, for abutment on the two free sides, as shown in figure 1(b).

The Analog Front End (AFE)
The general scheme of the AFE is based on an inverter-based CSA preamplifier with a Krummenacher feedback [2] and a discriminator.
We have designed several versions, all geometrically and electrically compatible, in order to test different solutions both for the Preamplifier and the Discriminator.For the preamplifier we have designed two versions, one with a cascoded input stage and one with a non-cascoded input stage.
The discriminator is also made in two versions.The first version implements a discrete-time offset compensation system (figure 2(a)) [3].The circuit can self-correct its internal offset while saving the desired baseline on a capacitor.The advantages of such a solution is the need of only two global voltages for the self-calibration of the entire matrix.As drawbacks, the offset-compensating procedure must be strobed and repeated periodically, introducing some dead time.Moreover, it increase the jitter by a factor √ 2. The second version of the discriminator uses a local DAC for each pixel to compensate for the offset and thus calibrate the threshold (figure 2(b)).In this case the calibration is static and does not have to be repeated systematically, and no additional contribution to time jitter is introduced.However, this solution requires extra circuitry (DAC) and configuration registers to store the calibration.It also requires a calibration procedure, for each pixel, to calculate the correction to be applied.
Figure 3(a) shows results obtained from post-layout simulations, reporting the behavior of the time jitter as a function of the input charge.The solutions that adopt offset compensation have a slightly higher jitter, as expected.The same can be seen in the figure 3(b) which shows the jitter trend as a function of power.

The Time to Digital Converter (TDC)
The TDC measures the Time of Arrival (TA) of an incoming signal with respect to a reference clock running at 40 MHz, measuring at the same time the Time Over Threshold (TOT) to correct the signal Time Walk to improve the TA measurement.
The TDC developed is an evolution of the one designed for the TimeSPOT project [3] and is based on a Vernier architecture [4], with two identical Digital Controlled Oscillators (DCOs) working with a small difference in frequency.
The DCO is made with a tapped delay line with starved delay units (figure 4).The power consumption refers to the conversion phase, while during stand-by both DCO's are stopped, saving power (power consumption kept below 2 µW).This choice helps to minimize the dynamic IR drop and therefore also the induced jitter.Moreover keeping the DCOs switched off helps to mitigate the effects -3 -  on the nearest analog front-end.Post-layout analog simulations with TDC parasitics show results within specification, while evaluation of system-level behavior with multiple TDCs operating simultaneously will be done during chip testing.Table 1 summarizes the characteristics both of DCO and TDC.

The Phase-Locked-Loop (PLL)
For this work we designed a PLL, tailored for a specific frequency (40 MHz), to reduce the clock jitter up to less than 5 ps.Furthermore, this PLL provides a multiplied 640 MHz clock starting from the 40 MHz one.To reduce the jitter we designed a digital control logic with few standard cells and an efficient Low-Pass (LP) filter.The PLL is composed by: 1) Digital Controlled Oscillator (DCO) with starving architecture; 2) Clock Frequency Detection (CFD) circuitry based on delayed Flip Flops and simple logic gates; 3) toggle counter (divider) for the generation of multiplied frequency clocks; 4) charge pump with a starving scheme.5) LP filter based on resistances and capacitances.Post-layout simulation results (with clock input jitter ranging from 0 to 25 ps) demonstrate that this design generates an output clock signal with a jitter less than 2 ps in all worst cases.

The Ignite-0 ASIC
The fundamental cells described in the previous sections have been implemented in the Ignite-0 integrated circuit.The ASIC size is 1 mm 2 .An 8×4 pixel (half tile) was created, integrating one AFE and one TDC for each pixel.Other key circuits, necessary to the implementation of a 4D-tracking ASIC have been integrated in Ignite-0.They are designed in a preliminary version, optimized for testing.Ignite-0 contains different PLLs for clock generation and filtering (40 MHz and 640 MHz), and test -4 -DACs for bias setting.An I2C-like interface has also been integrated, used as configuration and read-out manager, which can collect data from the TDCs.Data are concentrated in a FIFO and then conveyed to SLVS differential outputs.Figure 5 shows the full chip layout.The main ASIC blocks are highlighted.

Conclusion
We presented the Ignite-0 ASIC, designed in CMOS 28-nm technology.The ASIC has been submitted in July 2023.The purpose of the ASIC is the test and full characterization of the design structures which will be part of a larger pixel matrix (64×64 channels), being developed by IGNITE for 4D-tracking applications.The 64×64 ASIC will be the first in a series of modular ASICs featuring pixel matrices of different sizes, targeting the full satisfaction of the challenging requirements posed by future trackers at high-luminosity colliders.We showed results from post-layout simulations on some crucial design parameters, and in particular power consumption and time resolution.The results show that the due specifications can be met.Ignite-0 will be tested in the coming months, as the dies are foreseen to be received in November 2023, when the characterization tests will start.
(a) Discriminator scheme with Offset Compensation.(b) Discriminator scheme with Fine Tuning DAC.

Figure 3 .
Figure 3. Post-Layout simulation results of Jitter with respect to Input Charge (on the left) and Power (on the right).In the legend FT/OC indicates the Fine Tuning/Offset Comp.solution, while CAS/noCAS indicates the input stage cascoded/non-cascoded solution.

Figure 5 .
Figure 5. IGNITE0 layout, with the main functional blocks highlighted.

Table 1 .
DCO and TDC characteristics extracted from Post Layout simulation in Typical condition, with Transient Noise Analysis.Power Cons.-1.0 MHz Input Data rate 7.5 µA Power Cons.-500 kHz Input Data rate 3.9 µA Power Cons.-200 kHz Input Data rate 2.3 µA