Abstract
This work presents design and measurement results of FRIC—a prototype ROIC for fine resolution hybrid pixel detectors. The chip was manufactured in 40 nm CMOS process and contains an array of 64 × 64 pixels with 50 μm pixel pitch. It implements a very versatile analog front-end, capable of energy resolution of 0.71 keV FWHM and an estimated dead-time of 50 ns. The chip also features a Pattern Recognition algorithm together with signal summing for charge sharing correction. Low power consumption makes this circuit applicable in large-area detectors.