Abstract
Silicon Tracking System (STS) and Muon Chamber (MUCH) are components of the Compressed Baryonic Matter (CBM) experiment at FAIR, Germany. STS will be built from 8 detector stations located in the aperture of the magnet. Each station will be built from double-sided silicon strip detectors and connected via kapton microcables to the readout electronics at the perimeter of each station. The challenging physics program of the CBM experiment requires from the detector systems very high performance. Design of the readout ASIC requires finding an optimal solution for interaction time and input charge measurements in the presence of: tight area (channel pitch: 58 μ m), noise (< 1000 e- rms), power (< 10 mW/channel), radiation hardness and speed requirements (average hit rate: 250 khit/s/channel). This paper presents the front-end electronics' analysis towards prototype STS and MUCH readout ASIC implementation in the UMC 180 nm CMOS process and in-system performance with the emphasis on preferable detector and kapton microcable parameters and input amplifiers' architecture and design.