BSIM3 parameters extraction of a 0.35 μm CMOS technology from 300K down to 77K

In this work, we present a commercial 0.35 μm/3.3 V CMOS technology behaviour study of both linear and gate-enclosed transistors from room temperature down to 77 Kelvin. Cryogenic setup used to complete this study is first described. Measurement results are then discused and a model based on a BSIM3 parameters extraction is proposed.


Introduction
At low temperature, MOSFETs behaviour is modified. Gain and charge carrier mobility modifications as well as thermal noise and parasitic effect reductions are observed. Accurate knowledge of transistors behaviour is essential to design fully integrated instrumentation electronics and to achieve the best performances of integrated circuit in many fields like space instrumentation or nuclear science. Unfortunately, simulation models available from industrial foundries are meant to work only from −40˚C to 150˚C. Previous works have investigated technology behaviours at low temperature. For instance, in [1] an evaluation of AMS 0.35 µm CMOS technology to be implemented in Mars landers is presented but the study is not going below 165K. However the knowledge of the transistors behaviour at low temperature is required for many other space applications for wich cryogenic environment can help improving performances [2,3]  For each size, both linear and gate-enclosed transistor geometries have been studied. Gateenclosed transistors [4] show a better resistance to ionising radiation which is an asset for space applications. This design removes gate's edges and reduces leakage currents due to the bird's beak effect [5]. Figure (1a) shows the layout of a linear NMOS 50 µmx10 µm while figure (1b) shows the equivalent gate-enclosed transistor.  Figure (2) shows the cryogenic test bench. The circuit under test is inserted inside a cryostat immersed in a liquid nitrogen tank. Vacuum is maintained inside the cryostat to prevent air condensation and freeze on the device. A metallic frame is used to keep the cylinder in place during measurements. The cryostat immersion depth in the liquid nitrogen tank is controlled thanks to a micro-controller and a PT100 thermistor positioned on the device side. During  (3)). All instruments are controled by IC-CAP 2 software controls. Measurement points are corrected from the parasitic resistances of the drain and the source according to the temperature [6]. BSIM3v3 model parameters are extracted for each transistor category with IC-CAP using a precise extraction flow. An optimisation phase is then performed to improve the model's precision using Levenberg-Marquart algorithm which presents the best performance compared to other available algorithms.

Thermal study
To obtain a valid model describing the transistors behaviour around 100K, characteristics have been measured at 77K, 100K, 150K, 200K and 300K as a comparison.  Figure 3: CV measurement representation schematic.

Current-voltage measurements
Foundry model is meant to work from −40˚C to 150˚C. Figure (4) shows a transistor drain current temperature dependency for a given size and polarisation. On the same graph are plotted the foundry model simulation, the measurements and the extracted model. Below −40˚C a divergence between measurement and foundry model is observed. This divergence is growing as the temperature decrease so that around 100K the foundry model can not be used anymore. One of the most important temperature dependant parameter is the threshold voltage. Threshold voltage V th 0 defines the gate polarisation voltage split between two transistors states. Before threshold voltage, the transistor is in off mode, corresponding to a low current from drain to source. Conversely, after threshold voltage, the transistor is in linear or saturate mode. Table  (2) shows the threshold voltage variation with temperature. The absolute value of the threshold increases as the temperature decreases. This implies that for cryogenic temperature, the lowest transistor polarisation has to be greater than at room temperature. For PMOS transistors, a drift of half a volt is observed from room temperature down to 77K and reaches the value of −1.2V. Furthermore, silicon conductance is modified and evolves conversely to the temperature as shown on figure (5) by the output conductance curves, g ds , which quantify the drain current variation with a drain-source voltage variation while keeping the gate-source voltage constant (1). Figure 5: G DS = f(V DS , T) for a 50 µm × 10 µm NMOS.

Capacitive measurements
Capacitive measurements are useful to extract physical parameters of BSIM3's model. Figure (6) shows the capacity between the gate and drain-source-bulk in function of its polarisation. Besides a slight offset due to V th drift no significant difference in capacitive measurements between 300K and 77K is observed.  Figure 6: C G−DSB temperature dependence for V G−DSB sweep for a gate-enclosed 50 µm × 10 µm PMOS transistor.

Physical interpretation: freeze-out effect
The diminution of temperature provokes an increase in electron's mobility which is observed by an increase of the drain current. In the meantime, there is a diminution on charge carrier density with temperature [7]. When the density is too low, a drop in transistors current is observed. This well known freeze-out effect corresponds to a charge carrier gel and depends on the doping concentration. Figure (7) shows the electron density according to the temperature. The dots correspond to the electron density and the Fermi energy at 77K. The electron density decreases about two order of magntitude from 300K to 77K. As a result the current flowing in transistors decreases rapidly according to the temperature.   [8] does not take in account low temperature physical effect like the freezeout effect. Whereas some works present new models in order to take the freeze-out effect in account [2,9] we have adjusted BSIM3 physical parameters to bypass this lack. Figure (8) shows I D V G and I D V D curves between measurements and simulations based on extracted model at 100K. Both simulations and measurements are in good agreement.

Conclusion
We presented a cryogenic study of a commercial standard 0.35 µm bulk CMOS technology for both normal and gate-enclosed layout between 77K and 300K. For this purpose, an integrated circuit with transistors, resistors and capacitors of several dimensions and geometries has been designed, as well as a dedicated cryogenic set-up. Current-voltage capacitive measurements and parameters extraction have been performed using IC-CAP (Keysight TM ) software. As expected, a deviation, growing with decreasing temperature between measurements and foundry based models simulations is observed and is being assigned to physical phenomena, like freeze-out effect. Around 100K, deviation is such that models become unusable for a large variety of integrated circuit design. A model based on a BSIM3 parameters extraction has been proposed. Ready to use Cadence libraries have been developed. Librairies are suitable for the accurate design of cryogenic circuits in a wide temperature range from 300K down to 77K and for given transistor sizes.