Performance tests of a power-electronics converter for multi-megawatt wind turbines using a grid emulator

A vast increase of wind turbines (WT) contribution in the modern electrical grids have led to the development of grid connection requirements. In contrast to the conventional test method, testing power-electronics converters for WT using a grid emulator at Center for Wind Power Drives (CWD) RWTH Aachen University offers more flexibility for conducting test scenarios. Further analysis on the performance of the device under test (DUT) is however required when testing with grid emulator since the characteristic of the grid emulator might influence the performance of the DUT. This paper focuses on the performance analysis of the DUT when tested using grid emulator. Beside the issue regarding the current harmonics, the performance during Fault Ride-Through (FRT) is discussed in detail. A power hardware in the loop setup is an attractive solution to conduct a comprehensive study on the interaction between the power-electronics converters and the electrical grids.


Introduction
In the last decades, a vast increase of wind energy penetration into the electrical grids has forced WT to support the grid operation. Hence, WT nowadays must undertake grid compliance tests to prove if WT can perform as required by the grid codes. One crucial test is the so-called Fault Ride-Through (FRT) test. In this test, the capability of WT to remain synchronized with the electrical grid is proven as it is required by todays grid codes [1] [2].
Typically, FRT tests are performed by means of a shunt-impedance-based fault generator [3] [4]. Another test method using a power-electronics-based grid emulator has been developed for the 4 MW WT test bench at the Center for Wind Power Drives (CWD), RWTH Aachen University [5]. Compared to the first method, it offers a higher flexibility to the test conditions due to the controllability of the grid emulator. However, the tests using grid emulators might result in a different performance as compared to the conventional method. The voltage harmonic distortion due to switching of the grid emulator converters might result in an undesired harmonic interaction with the DUT. Moreover, the impedance formed by the passive elements of the grid emulator could lead to a different voltage reaction at the PCC during the FRT tests. This paper focuses on the analysis on the behavior of the DUT when operating with the grid emulator, particularly the harmonics interactions and the performance during FRT tests. The analysis in this paper is conducted based on the simulation of the system using the software MATLAB/Simulink and PLECS which provides preliminary evaluation of the design of the newly developed grid emulator and DUT as well as the expected interaction prior to the operation.
At first, the improved power-electronics-based grid emulator for the WT test bench at the CWD is described. Afterwards, the construction of the considered DUT as well as its main features are presented in detail. Before discussing the FRT tests, the harmonics interactions related issues in the operation of the DUT with the grid emulator are briefly discussed. This delivers an important information if the passive components and switching of the grid emulator will harm the components of the DUT after synchronization.
Finally, the behavior of the DUT during the FRT tests using the grid emulator is analysed. The results of the FRT tests are then compared with the typical FRT tests conducted using a shunt-impedance-based fault generator. Beside showing if the construction of the grid emulator leads to instability during emulated grid faults, it provides the basic characteristic of the grid emulator in comparison to the conventional test method.

Grid emulator
In principle, the grid emulator provides a controllable 50 Hz ac grid at the point of common coupling (PCC) to the DUT. It actively regulates the voltage at the PCC according to the grid conditions to be emulated. For the test bench at CWD, a power-electronics-based grid emulator is used. As shown in Fig. 1, the grid emulator is constructed by three parallel medium-voltage (MV) converters with Three-Level Neutral-Point-Clamped (3L NPC) topology [6]. Thereby, a controllable ac voltage of 3 kV (line-to-line) can be generated with a 5 kV dc bus. The grid-emulator converters (GEC) are parallel connected via a multi-winding transformer TR GE that steps the voltage up to 20 kV at the PCC. To minimize the filter size that is required to improve the voltage quality, the GEC are interleaved switched resulting in a higher effective switching frequency. This concept allows a grid emulation with high dynamics which is necessary to realistically emulate grid faults on the test bench. In order to minimize the harmonics caused by switchings of the grid emulator converters, filter components are installed to a tertiary winding of the grid emulator transformer that has a rated voltage of 6 kV. Thereby, the series inductance from the filter branch to the PCC can be minimized resulting in a better control of the emulated voltage. To minimize the circulating current between the grid emulator converters due to the interleaved switching strategy, a three-phase series inductor L f,GE is installed in between every converter and the transformer windings. In Table 1, the specifications of the grid emulator are summarized.

Device under test
A grid-connected converter system designed for a 2.75 MW research wind turbine is considered as the DUT. It comprises three parallel-connected power blocks and a control unit that controls the entire converter. Each power block consists of a grid-side converter (GSC) and a machine-side converter (MSC) based on a low-voltage two-level voltage-source converter topology. Because the power blocks are switched synchronously, the system can then be treated as one unit converter system with a larger capacity.
In the research wind turbine, the MSC drives a 2.75 MW asynchronous generator and provides the necessary electromagnetic torque to control the WT. On the grid side, the GSC is equipped with a passively-damped LC-filter that forms with the stray inductance of the transformer TR DUT an LCL-filter. During the operation, the DUT converter synchronizes the voltage on the low-voltage (LV) side of TR DUT that steps the voltage up from 690 V to 20 kV at PCC. Detailed parameters of the DUT are listed in Table 2.  The grid filter has been designed to meet the harmonics criteria given in the BDEW grid code [2]. Care must be taken when connecting the GSC to a converter-based grid emulator. Current harmonics produced by the grid emulator due to switchings might additionally stress  the filter components of the DUT. Additionaly, current harmonics produced by the grid emulator might also falsify the measured harmonics of the DUT at the PCC [7]. It depends on the available series impedance between grid emulator and DUT. Detailed analysis on this issue is presented in section 4. The DUT has been designed to fulfill the recent grid code regarding the FRT requirements. Besides staying synchronized with the grid during the fault occurance, the converter is able to deliver reactive current I PCC,R (in p.u.) to the grid according to (1). It depends on on the residual grid voltage V PCC,res as well as the factor k. The resulting I PCC,R is negative in case of grid faults V PCC,res < 0.9 p.u. indicating an overexcited operation. The adjusted factor k is to be coordinated with the grid operator prior to the initial grid connection and can vary from 0 up to 10. In case the combination of V PCC,res and k results in |I PCC,R | > 1 p.u., the magnitude of the reactive current is limited to 1 p.u. (1)

Harmonics interaction 4.1. Stress on filter components
Grid filter components of the DUT, C f,DUT and R f,DUT , are dimensioned according to the current harmonics that occur due to switchings of the power-electronics converters. Usually, the grid voltage is assummed to be harmonics free such that only the switching of the DUT converters contribute to the stress of the filter components C f,DUT and R f,DUT . When operating the DUT on a test bench with a power-electronics-based grid emulator, additional stress due to the produced harmonics by the grid emulator converters (GEC) might occur. Therefore, it must be ensured that C f,DUT and R f,DUT are not overstressed during the operation with the grid emulator. To study this issue, the power loss mainly in the R f,DUT is analysed and compared to the value the R f,DUT is designed for. Figure 3 shows the frequency spectrum of the emulated grid voltage V PCC on the low-voltage (LV) side of TR DUT obtained from the simulation with two possible grid emulator setups. The setup 1 applies the specification given in Table 1. For the setup 2, a higher carrier frequency f car,GE = 1050 Hz is used and the entire filter components C f,GE and R f,GE are disconnected. Both setups result in a voltage total harmonic distortion THD V lower than 5 % as required in [3] which can be obtained using (2).
It must be noted that the given equation for THD V considers a frequency range only up to the 50 th harmonic for a 50 Hz power system (2500 Hz). Thereby, the grid emulator setup 2 still fulfills the THD V requirement even though the grid emulator filter branch is disconnected. Due to the increase in the carrier frequency f car,GE , the voltage harmonics are shifted outwards the evaluated frequency range in (2). This can potentially overload the installed filter components in the DUT.
To obtain the power loss in the filter resistance R f,DUT , simulations of the entire system including the grid emulator and the DUT have been carried out using the software PLECS. Besides with the aforementioned grid emulator setups, a simulation with a reference grid has also been conducted. The reference grid is a simplified grid model that incorporates an inductive grid impedance with a short-circuit power of 110 MVA. Since the voltage of the reference grid is assumed to be free of harmonic distortion, the power loss occur in the R f,DUT is solely due to the GSC of the DUT. The total power loss in the DUT's filter resistances P f,DUT obtained from simulation with different grid setups and grid voltage magnitudes V PCC is displayed in Fig. 4. As can be seen in Fig. 4, the influence of the grid emulator on the P f,DUT is relatively low. When operating the DUT with the grid emulator, only 5 % higher power loss P f,DUT can be observed compared to with the reference grid. This increase of power loss is still within the acceptable range for a safe operation of the DUT. Even with the grid emulator setup 2, only a slight increase occurs in the P f,DUT . This indicates that the series impedance formed by the stray inductance of the TR DUT , stray inductances of the TR GE and L f,GE provides a sufficient attenuation for the harmonics produced by the GEC to avoid an overload in R f,DUT . Figure 4 also reveals the dependency of the P f,DUT on the V PCC . Besides the power at fundamental frequency, the harmonics produced by the power-electronics converters also contributes to the variation in the P f,DUT . According to [8], these harmonics are affected by the applied dc-link voltage as well as the modulation ratio of the GEC. Thereby, the contribution of the switching harmonics of the GEC to the increase in the P f,DUT is also slightly higher. However, due to the the series impedance between the DUT and grid emulator, the increase of P f,DUT is still kept below 5 %.

Current harmonics at PCC
Prior to the connection of wind turbines to an electrical grid, the injected current harmonics must be evaluated according to the valid grid code. When tested with the grid emulator, the resonance introduced by the passive elements of the grid emulator can amplify the current harmonics injected by the DUT to the grid. In addition, the harmonic contents present in the emulated grid voltage V PCC can falsify the measured current harmonics of the DUT at the PCC [7]. These two issues need to be investigated seperately.  Fig. 5(a) is used. Beside with the grid emulator setup 1, the frequency response with the reference grid, which is the assumed grid condition while designing the grid filter of the DUT, is also plotted. It can be seen in Fig. 5(a) that no significant difference between both grid setups is observed in the attenuation around the carrier frequency of the DUT (3.2 kHz), where the harmonics are mainly located. At this frequency, the impedance of both grid setups is relatively small compared to the impedance the stray inductance of the TR DUT . Thereby, the influence of the grid emulator setup on the PCC current is negligible at this frequency. In addition, no amplification caused by the passive components of the grid emulator can be seen in Fig. 5(a) since it is well damped by the R f,GE . Hence, it can be concluded that the grid emulator setup has a negligibly impact on I PCC .
Besides the impedance of the grid emulator, the voltage distortion of the grid emulator can affect the obtained current harmonics at the PCC I PCC . Figure 5(b) presents the frequency spectrum of I PCC on the LV side of TR DUT obtained from the simulation with two different grid setups. In the upper graph, the current harmonics of the DUT with the reference grid are displayed. Since the reference grid is free of harmonic distortion, the harmonic content in I PCC with the reference grid is solely due to the DUT. However, the harmonic content caused by the DUT is significantly affected by the harmonic distortion caused by the GEC as displayed in the lower graph of Fig. 5(b). When the current harmonics of the DUT needs to be determined on the test bench with the grid emulator, the current harmonics caused by the DUT need to be calculated based on the measured V GSC and the system admittance I PCC V GSC as in Fig. 5(a).

Fault ride-through (FRT) tests
As previously mentioned, several advantages can be gained when performing FRT tests of the DUT with the grid emulator. In the following subsections, the dynamic behavior of the grid emulator will be firstly characterised. Afterwards, typical fault voltage waveforms for the certification of wind turbines [3] [9] are emulated at the PCC and the simulated performance of the overall system is analyzed. Lastly, the behavior of the DUT during grid faults is compared with the field test results performed using a shunt-impedance voltage divider. For the following analysis, only the grid emulator setup 1 as defined in Table 1 is considered.

Characteristics of the grid emulator
Before performing the FRT tests with the grid emulator, it must be ensured that the emulated fault voltage represents what the DUT might experience in the field. To conduct this evaluation, standard IEC 61400-21 [3] is used as a reference. It provides a standardized waveform for fault voltages in the root-mean-square (RMS) domain that can be used to perform certification regarding the FRT capability. Figure 6(a) shows the emulated three-phase grid fault voltage with a residual voltage V PCC,res = 0.5 p.u. and a fault duration t fault = 100 ms. In the Fig. 6(b), the corresponding rms waveform is plotted along with the tolerance area according to the standard IEC 61400-21.  As projected in Fig. 6(b), the dynamic of the grid emulator is high enough to realistically emulate grid faults. The rms waveform lies within the tolerance area for the entire fault duration. At the fault occurance as well as fault recovery, the voltage reaches its final value within less than 20 ms as required by the standard IEC 61400-21. A small oscillation observed at the beginning of the voltage transient is mainly due to the resonance formed by the filter capacitor C f,GE , the filter inductor L f,GE and the stray inductances of TR GE . The oscillation is damped by the resistances in the system mainly by R f,GE such that it lasts only less than 2 ms and does not siginificantly influence the rms waveform of the voltage.

Simulation of FRT tests
To observe the behavior of the entire system while performing an FRT test, a grid fault scenario is simulated using in the simulation platform MATLAB/Simulink. The DUT supplies an active power of 1 MW when a grid fault with V PCC,res = 0.39 p.u. and t fault = 600 ms occurs at the PCC. For this test, k = 2 has been selected such that a reactive current I PCC,R of 1 p.u. is supplied by the DUT during the fault event.   Figure 7 presents the behavior of the DUT during the occurance of the grid fault. The upper graphs show the instantaneous PCC voltages and currents measured on the low-voltage side of the TR DUT whereas in the lower graphs the rms voltage and currents are plotted. Negative active and reactive currents indicate a current flow towards the grid. Immediately after the fault occurs, the DUT stays synchronized with the grid and the active current is increased up to 0.7 p.u. to compensate the dropping grid voltage. As expected, the reactive fraction of the grid current I PCC,R also rises towards 1 p.u. due to the pre-programmed k factor. It results in a current magnitude higher than 1 p.u. which is still permitted regarding the stress on the installed semiconductor devices.
As a result of the voltage support functionality via I PCC,R within the fault duration, the V PCC slightly rises to about 0.46 p.u. from 0.39 p.u. at no-load leading to a slight reduction of I PCC,R to 0.9 p.u. This voltage increase is caused mainly by the voltage drop over the stray inductance of the TR DUT , stray inductance of TR GE and the filter inductor L f,GE . Due to the relatively small size of C f,GE and the relatively low PCC voltage throughout the grid fault, the filter branch of the grid emulator does not significantly contribute to the voltage variation. It can be concluded that the emulated grid fault using the grid emulator reflects a fault situation where the fault impedance is relatively small. Due to the relatively high impedance of TR DUT compared to the impedance of the grid emulator at the PCC, the DUT can stay synchronized with the grid emulator without any instability problems.
In order to have a comparison on the behavior of the DUT at the PCC, a practical FRT test using a shunt-impedance-based fault generator has been carried out in the test field of Siemens AG in Ruhstorf a. d. Rott, Germany. The schematic of the fault generator [10] and the measured fault voltage at no-load are presented in Fig. 8. To apply the fault at the PCC, the switch CB 1 must be firstly opened to limit the influence on the public grid during the test via the X sr . Afterwards, the switch CB 2 is closed and a short-circuit via the impedance X sc occurs at the PCC leading to a voltage dip. X sr and X sc must be selected according to the desired residual voltage V PCC,res . In the conducted test, a fault with V PCC,res = 0.39 p.u. for t fault = 2500 ms is applied while the DUT operates with an active power of 1 MW. The residual voltage is proven at no-load condition ( Fig. 8(b)) to exclude the influence of the DUT. k = 2 is selected in the DUT controller so that the DUT is expected to deliver reactive current I PCC,R of 1 p.u. throught the fault duration. The voltages and currents measured on the low-voltage side of TR DUT are plotted in Fig. 9.  Through an FRT test with the shunt-impedance-based fault generator, a similar behavior of the DUT can be identified. The active current rises proportionally to the dropping V PCC and the reactive current support I PCC,R is activated. However, only 0.6 p.u. of I PCC,R can be observed from Fig. 9. Due to a relatively high fault impedance formed by the reactances in the fault generator circuit, the reactive current I PCC,R forces the PCC voltage to rise significantly from 0.4 p.u. to 0.6 p.u. Due to the voltage rise, the DUT has to adjust the I PCC,R accordingly.

Power-Hardware-in-the-Loop (PHiL) Setup
Both FRT tests are implemented with a standardized voltage curve. In case of the grid emulator the reference to the converter comes from data generated offline. Due to this implementation only the effect of the fault impedance on the behavior of the DUT can be shown. In reality the behavior of the DUT during a grid fault is determined by the complex grid structure. One solution to consider the grid structure in the FRT tests without connecting DUT to the real grid is by means of the so-called Power-Hardware-in-the-Loop (PHiL) setup depicted in Fig. 10. It allows further critical tests of the DUT as well as comprehensive interaction studies between the DUT and the electrical grids. PHiL describes a process, where a part of a system is simulated and another part of the system exists in real, described as device under test (DUT). A PHiL setup always requires a power interface. In this case the grid emulator is the power amplifier of the system [11][12] [13]. The grid emulator acts as a controlled voltage source which obtains the output of the real-time grid simulation as reference voltage and provides the appropriate voltage at the PCC for the DUT. The current at the PCC is measured and fed back into the real-time simulation. The real time digital simulator (RTDS) is used for the implementation of a real-time simulation of the power grid [14]. The RTDS is part of the real time laboratory at the Institute for Automation of Complex Power Systems (ACS). The challenge in this setup is the distance between the ACS real-time laboratory and the test bench at the Center for Wind Power Drives (CWD) since a low latency between the RTDS and the grid emulator is necessary for the stability of the PHiL setup. Fiber optic cables are used as communication link between the two locations, which have a distance of 2 km to each other.

Conclusions and Outlook
The performance of a power-electronics converter for WT might be influenced by the behavior of the power-eletronics-based grid emulator. The analysis has shown that the DUT can be safely operated without any overstress in the filter components although the measured harmonics at the PCC are strongly influenced by the grid emulator. Regarding the FRT test, the grid emulator shows a relatively low grid fault impedance which results in a significant different behavior of the DUT during grid faults compared to the test results with the shunt-impedance-based fault generator. Hence, the influence of the DUT on the PCC voltage is relatively minimum compared to the conventional method. PHiL setup developed for the 4 MW Wind Turbine Test Bench at CWD RWTH Aachen University is an attractive solution for the comprehensive interaction study between power-electronics converters for WT and the electrical grids. Although the evaluation is based on simulation results, it also provides the preliminary characteristics of the newly developed grid emulator and its expected interaction with the DUT. Since the test bench is currently being commissioned, the verification of the presented evaluation will be presented in a future paper.