Study on TSV insulating medium based on SACVD process

TSV silicon switching board technology has the advantages of short global interconnection, small delay, low power consumption and high integration. The dielectric insulation performance in the TSV hole will directly affect the signal integrity and power integrity of the TSV silicon switching board. The insulating dielectric layer of TSV requires good forming ability and step covering, and lower leakage current and good heat resistance reliability. In this paper, the filling capacity of SACVD process is analyzed, the coverage rate of SACVD process is studied under different process parameters, and the leakage current of silicon dioxide film is measured by planar capacitance structure. Finally, the leakage current test of the TSV pairs is carried out online. Before the substrate thinning, the leakage current of the two blind hole TSV pairs is measured by the probe station. The voltage ranges form 0 to 50V, and the leakage current ranges from a few pA to a few hundred pA.


Introduction
Moore's law with the development of semiconductors,more and more to the limit.Advanced packaging technology(wafer-level packaging, SiP, 3D multi-chip packaging), through a system-level chip can support more and more functions, reduce the cost of the chip, improve the equivalent integration of the circuit, to continue the life of Moore's law.TSV silicon converter board technology based on vertical through hole interconnection, RDL, micro-convex and other processes is one of the best ways to realize microsystem integration due to its advantages of short global interconnection, small delay, low power consumption, and high integration [1][2].3D integration of homogeneous or heterogeneous chips and passive devices is realized through TSV through-silicon holes, which is applied to RF microsystem integration products [3].
The insulating dielectric layer in the TSV hole is used to realize the insulation between the silicon substrate and the transmission channel in the hole, preventing the leakage between the TSV through the hole and the signal crosstalk between the TSV.The insulation performance of the dielectric in the TSV hole directly affects the signal integrity and power integrity of the TSV silicon switching board, which is one of the key processes to ensure the TSV switching board of the micro-system [4].With the development of 3D packaging technology towards high density and small size, as the size of TSV is smaller and the depth to width ratio is increased.The traditional insulation layer preparation technology can no longer meet the process requirements.With the development of TSV technology to a higher frequency, higher requirements of silicon switching board are put toward for the performance of the insulation layer, requiring it to have good forming ability and good step coverage.At the same time, it should has low dielectric constant, low leakage current, high breakdown voltage, low stress and good heat resistance reliability [5].In terms of process, there should be lower costs and lower temperatures.

SACVD process
Studies have shown that silicon dioxide and silicon interface have fewer interface defects, better passivation performance on silicon surface, and lower leakage current.So silicon dioxide is preferred as the insulating dielectric layer of hole wall [6].At present, the commonly used preparation methods of insulating dielectric materials for TSV hole walls include thermal oxidation, PECVD, SACVD, LPCVD, ALD, etc. [7].PECVD process can achieve a low deposition temperature and has low requirements on the surface state of the chip source, but the hole wall step coverage of vertical TSV holes with small aperture and large depth and width is poor.The silicon dioxide layer prepared by thermal oxidation process has dense structure, high pore wall step coverage and high process temperature, usually above 1000℃.LPVCD process temperature is high, generally above 700℃, deposition rate is slow, hole wall step coverage rate is high.ALD process hole wall step coverage can reach more than 80%, but its depositon rate is too slow.SACVD process can be used in the same equipment as PECVD process, the deposition temperature can be reduced to 400℃.Also, the hole step coverage is much better than PECVD process, and the deposition rate is faster.SACVD process is used to prepare silicon dioxide, and TEOS and O3 react at 400℃.A small amount of O3(2%) can greatly reduce the deposition temperature, easily decompose oxygen atoms, promote surface mobility, and improve filling capacity [8].FIG. 1 shows the SEM cross-section of dioxide dielectric layer prepared in the TSV hole.The thickness of dioxide dielectric layer at the top of the TSV hole is relatively large, and the dioxide film deposited along the inner wall of the hole gradually decreases, and the holes are completely covered with dioxide dielectric material, with no missing area of silicon dioxide.

SACVD process coverage rate
The high aspect ratio trench was filled by SACVD process, and the deep hole coverage was significantly improved compared with PECVD process.FIG. 2 shows the schematic diagram of TSV blind hole coverage, in which the depth to width ratio of groove is defined as h/w, the bottom step coverage is defined as b/a, and the top side wall step coverage is defined as c/a [9].When the groove step coverage is carried out by SACVD process, the bottom is the thinnest for TSV blind hole, and the middle is the thinnest for TSV through hole double-sided coverage.

FIG.2 Schematic diagram of TSV blind hole coverage[9]
O3 concentration, process pressure and process temperature are the key parameters affecting TSV hole coverage.For TSV hole coverage experiments were carried out in this paper according to different process conditions, and scanning electron microscope(SEM) testing method was used for testing.The SEM testing instrument was HITACH su8230.The experimental wafer was etched by ICP device, the ratio of aperture depth to width was 200μm:30μm, and the ICP device was SPTS Rapier.The data obtained under different O3 concentration conditions are shown in Table 1.As O3

Film leakage current test
In this paper, the leakage current of 200nm silicon dioxide films with the O3 concentration of 5%, 9%, 12.5% and 15.5% was measured by the planar capacitor structure.The voltage excitation was 0-50V, and the current limit was 1mA.The semiconductor parameter tester used for the test was TEKTRONIX 4200-SCS, and the probe station was CASCADE 12000B-S.The measured leakage current I-V curve of the silicon dioxide film is shown in FIG. 3. The leakage current increases with the increase of the loading voltage.Under 50V excitation of the silicon dioxide film with O3 concentration of 9%, 12.5% and 15.5%, the maximum leakage current is 25pA.The leakage current of silicon dioxide film with 5% O3 concentration under 50V excitation is slightly larger than that under other conditions, with a maximum of 1nA.
FIG. 3 Leakage current I-V curves of silicon dioxide films with different concentrations of O3

TSV leakage current test
In conventional processes, process steps such as CMP removal of electroplated copper covering, back thinning and back growing insulation may cause defects in TSV insulation, resulting in poor TSV insulation and large TSV leakage current.In the process of TSV leakage current test, the problems existing in the converter board can be found in time, also improve efficiency and reduce cost.No active device is made on the TSV adapter board.The measurement of TSV-related leakage current is concerned with the leakage current between two adjacent TSVs through the side wall insulation layer and the substrate [10][11].Before the substrate thinning, the leakage current of two blind hole TSV pairs is measured by the probe station, and the loading voltage is from 0 to 50V.The I-V characteristic curve can be obtained, which can effectively judge whether the insulation layer of two TSV blind holes has defects, and obtain the qualified insulation resistance of TSV.FIG.4(a) shows the leakage current test diagram of the TSV pairs.Semiconductor parameter analyzer and probe station are used.The probe is pressed on Port1 and Port2 of the TSV, and the increasing ramp voltage from 0 to 50V is loaded to measure the corresponding current value.FIG. 5 The leakage current of TSV pairs at different bias voltages For TSV pairs with different pitch from 100um to 3300um, the paper also tested the leakage current of TSV pairs.As shown in FIG.6, the I-V characteristic curve of leakage current is consistent when the pitch of TSV pairs is different.The leakage current increases with the increase of the loading voltage, and the leakage current is less than 100pA when the final 50V voltage is loaded at different pitch.
FIG. 6 The leakage current with different voltage bias in which different pitch of TSV pairs

Conclusion
The insulating dielectric layer of TSV requires good forming ability and step covering, and low leakage current and good heat resistance reliability.Experimental data show that the coverage rate of TSV insulating dielectrics increases with the decrease of O3 concentration and the decrease of CSMNT-2023 Journal of Physics: Conference Series 2740 (2024) 012051 chamber process pressure.For optimizing the concentration and the chamber process pressure parameters, which can obtain the stepwise coverage of 20% and 7%, respectively.The leakage current of the silicon dioxide thin film is measured by the planar capacitor structure.Finally, the leakage current test of the TSV pairs is conducted online.The leakage current of the two blind TSV pairs is measured by the probe station.The voltage is loaded from 0 to 50V, and the leakage current is several pA to several hundred pA, which can effectively determine that the insulation layer of the two blind TSV pairs is free from defects.At the same time, the leakage current of TSV pairs with different pitch from 100μm to 3300μm is measured, and all of them are less than 100pA, which has completed the preliminary exploration of TSV insulation performance.

FIG. 4
FIG.4(a) Schematic diagram of TSV test on leakage current (b) Leakage current test diagram of TSV pairs By testing the leakage current of TSV pairs one by one, the typical curve of leakage current changing with voltage as shown in Figure 5 can be obtained.Loading 0 to 50V voltage, leakage current increases with the increase of voltage, and the final leakage current ranges from tens of pA to

Table 1
the coverage rate of TSV holes.The experimental data corresponding to different process pressure conditions are shown in Table2below.As the process pressure decreases, the coverage rate of TSV insulating dielectrics increases.