Development of a low-power SAR ADC for analog front-end readout circuit of hydrophones

A low-power 16 bit 250KSa/s successive approximation analog-to-digital converter (SAR ADC) is designed. The capacitor array consists of a 2-segment sub-capacitor array and high sampling makes the coupling capacitance a unit capacitance, solving the problem of fractional capacitance mismatch. The power consumption is reduced by introducing a common-mode voltage during the switching process of the capacitor array. The circuit uses a 4-stage pre-amplifier and adds a dynamically latched comparator using output misalignment calibration to ensure high accuracy resolution. Simulated in DB Hitek 0.18 μm process, the Fast Fourier Transform(FFT) simulation results for 4096 points show that the signal-to-noise distortion ratio (SNDR) of the ADC can reach 90.2 dB and the effective number of bits (ENOB) can reach 14.69 bit. The average power consumption is 2.507mW at a supply voltage of 5 V, and this holds significant significance for the long-term deep-sea detection capabilities of sonar systems.


1.Intorduction
Due to the growing enthusiasm of the world's countries for ocean development, the hydroacoustic industry has gained unprecedented development [1,2] .As the preferred equipment for underwater detection, sonar has become a powerful weapon for marine development and an indispensable part of warships and civilian vessels [3] .As one of the main components of the sonar, the hydrophone analog front-end readout circuit has also become an important research topic in China's hydroacoustic technology.
The traditional hydrophone analog front-end system uses discrete low-noise low-distortion operational amplifiers and filters to achieve detection, and then with the analog-to-digital converter to form a board-level system .This system is large in scale and susceptible to external environmental interference, with lower detection accuracy.Due to the emergence of long-distance detection and low-frequency noise measurement, the hydrophone analog front-end system puts forward new requirements of high precision and low power consumption for ADC.
Among various types of ADCs, SAR ADCs are characterized by medium to high accuracy and low power consumption.In addition, SAR ADCs are simple in structure, easy to integrate, and small in area, which makes SAR ADCs the first choice for analog front-end systems.In 2018, the University of Ulm, Germany, designed and flowed an 80KS/s, 16-bit SAR ADC on a 40nm CMOS process with a power consumption of only 0.11mW [4] .2022, Nanyang Technological University, Singapore, to design and program a 20MS/s noise-shaping SAR ADC on a 65nm CMOS process, and its total power consumption is 0.51mW [5] .In 2020， University of Electronic Science and Technology (UEST) designed and flowed a VCO-based 14-bit 4MS/s SAR ADC based on 40nm CMOS process with a power consumption of 157μW [6] .In 2021, Tongji University has designed and flowcharted a 10MS/s 16-bit SAR ADC based on a 4-bit Flash ADC and a 12-bit SAR ADC with two redundant bits, and its total power consumption is 10mW [7] .Currently, there are fewer studies on low-power SAR ADCs for hydrophone analog front-ends in China ， so this paper designs a 16 bit low-power SAR ADC based on Vcm-based architecture and the simulation results are in line with the initial design intent.Theoretical research of this article holds significant significance for the long-term deep-sea detection capabilities of sonar systems.

SAR ADC Circuit Design
The overall structure of the SAR ADC designed in this article is shown in Figure 1.It consists of two Sample and Hold (S/H) circuits, two Digital to analog converter(DAC) capacitor arrays, a comparator, and a SAR logic.After the analog signal is input, it passes through the Sample and Hold circuit and is then delivered to the comparators and the capacitor array.The output from the comparators is sent to the logic circuit for processing, and the final output is in digital code.The DAC capacitor array uses a successive approximation algorithm triggered by the output of the comparators.In the overall power consumption of SAR ADC, CDAC accounts for a large proportion, so improving the capacitor array architecture can greatly reduce power consumption.Therefore, this article uses Vcm-based capacitor array architecture.

Capacitor Array
Capacitor arrays have the following problems: firstly, as the accuracy increases, the capacitance increases exponentially, the area increases and the power consumption increases.To solve the problems of large capacitance array area and power consumption, segmented capacitance arrays are usually used.To further reduce the capacitance array area and power consumption, a Vcm-based architecture is used for sampling, thus reducing the total amount of capacitance per unit by half.The SAR ADC with Vcm-based architecture works similarly to the traditional SAR ADC, the main difference is the quantization method of the first bit.The specific switching process is as follows: In the sampling stage, the sampling switch φs is closed, the upper plate of the DAC capacitor array is connected to Vcm, and the lower plate of the capacitor is connected to Vinn and Vinp , respectively, so that the input differential signal is sampled to the lower plate of the DAC capacitor.The total capacitance magnitudes of the P-terminal and the N-terminal are CPtot and CNtot ,then at this time, the magnitudes of the charges at the P-terminal and the N-terminal of the upper plate are respectively: ( ) ( ) (2) After that the switch φs is first disconnected and then the lower plate connected to the input signal is disconnected, and the lower plates of the capacitor are both connected to the Vcm terminal, then the values of VDACP and VDACN can be obtained according to the conservation of charge: ) At this point the differential signal at the comparator input is: (5) Compared with the capacitance switching method of conventional SAR ADCs, the Vcm-based architecture approach accomplishes the first bit comparison without switching the highest bit capacitance.Therefore, the capacitance of the highest bit in the traditional SAR ADC can be eliminated, which reduces the total capacitance size by half.After that, the same switching method as the conventional SAR ADC is used to complete the switching of each weighted capacitance.If the first bit of the comparison results in b1=1, that is, Vin is greater than 0, the next Vin and 1/2Vref comparison, the highest bit of capacitance at the P end of the lower electrode plate from Vcm to Vref, the highest bit of capacitance at the N end of the lower electrode plate from Vcm to gnd.The same can be seen by the conservation of charge: Combining the two equations gives: As can be seen from the formula (8), the second bit of the comparison is realized at this time, and so on, the input signal can be gradually approximated and converted into digital code values.One of the conversion of the current comparison results of the comparator determines the next quantization when the digital logic circuit to control the DAC capacitor lower pole plate switch switch to Vref or gnd, eliminating the traditional SAR ADC guessing process, thus avoiding the capacitor 'back cut', reducing power consumption.The switching power consumption of traditional and Vcm-based architectures was simulated in MATLAB, as shown in the Figure 3.It can be seen that the Vcm-based architecture greatly saves power consumption.
Compared to traditional SAR ADCs, the overall capacitance of the Vcm-based architecture is reduced by half, which means that the build-up time of the maximum capacitance is halved, and then the time utilization is improved compared to traditional SAR ADCs, so the Vcm-based architecture also improves the speed for the overall ADC.At the same time, due to the reduction of the overall capacitance area, the power consumption of the Vcm-based architecture also has a greater advantage over traditional SAR ADCs.

Figure 3. Switching power consumption of two architectures
Then the matching requirement of capacitance is increasing, under the existing process conditions, the highest precision that can be achieved is 12 bits, if the precision is further improved, how to solve the matching problem of capacitance.The coupling capacitance in a fractional capacitor array is not an integer multiple of the unit capacitance, it is a fractional capacitance.Fractional capacitance can cause a lot of trouble in layout design and capacitance matching accuracy, because a very small mismatch in the coupling capacitance will cause a serious drop in overall accuracy.In order to overcome the above difficulties of capacitance array, the traditional segmented capacitance array is improved so that the size of the coupling capacitance Cs is equal to the unit capacitance Cu, and the improved MSB array contains the dummy capacitance Cu and only the MSB array capacitance is involved in sampling.
In this design, a 9+7 segmented DAC structure is used.The MSB capacitor array has 8-bit capacitance and the LSB capacitor array has 7-bit capacitance due to the reduction of one-bit sampling capacitance based on the Vcm-based high-bit sampling method.Figure 4 shows a diagram of the fully differential segmented capacitor network DAC module used in this design.

Comparator
For the 16 bit SAR ADC design for high precision needs, the comparator needs to be able to compare a voltage of 76 μV.The Latch circuit may have large offset voltages and other non ideal factors, so it generally requires a preamplifier stage to amplify the signal by more than 20 mV.That is to say, a preamplifier with sufficient high gain is needed to reduce the residual offset voltage of the entire comparator.Therefore, this design uses a 4-stage pre-amplifier circuit plus a dynamic latch cascade comparator structure to overcome the effects of comparator misalignment, noise, and speed.Comparators with pre-amplification circuits are generally calibrated with either input storage or output storage.Input storage calibration is suitable for high-gain amplifiers and is required to ensure that their inputs and outputs are stable when they are shorted, and the effect of phase margins needs to be considered or even additional frequency compensation circuits need to be added.Output storage calibration is a little less difficult to design and has a better performance of the out-of-phase calibration.Therefore，this design uses the output out-of-phase calibration technique to calibrate the out-of-phase voltage of the comparator, the specific circuit is shown in Figure 5.The circuit diagram of the preamplifier is shown in Figure 6, Vip and Vin are the input signals, IB is the bias current, and Vop and Von are the output voltages.M1 and M4 are diodes connecting the loads, and M2 and M3 are cross-coupled to form a negative impedance, and the gain of this circuit is: As long as the width-to-length ratio of M2 and M3 is less than that of M1 and M4, the overall negative feedback is guaranteed and no hysteresis occurs.The input signal of the first stage is still in a small signal state, so the first stage of the main consideration is the bandwidth, to be made large enough to enable the signal to pass through the amplification very quickly, the second to the fourth stage can be appropriate to reduce the bandwidth and improve the gain.
The dynamic latch circuit is shown in Figure 7.When CLK is low, the entire comparator is off.Node D-, D + are pulled to VDD through M1, M6, VOUT -and VOUT + are pulled to VDD through M2, M5, respectively.When CLK is high, M1 conducts, the entire dynamic latch is in the open state, if this time, VIN + is less than VIN -, then the node D + falling slower than the D -, VOUT + is also faster than the decline in the VOUT -.When VOUT + falls to a certain value, M3, M4, M7 and M8 constitute the latch for locking, at the same time VOUT-is also pulled to VDD, so that the comparator completes a comparison.

Results and Discussion
The 100 Monte Carlo simulation results of the comparator with the pre-amplified circuit using the output out-of-phase storage calibration method indicate that the average offset voltage is 162.253nV and its standard deviation is 4.10 μV, as shown in Figure 8 .Therefore, the offest voltage of the designed comparator is much less than 1/2LSB voltage, which satisfies the design of this comparator.

Conclusions
In this paper, a low-power 16 bit SAR ADC is designed with a capacitance array consisting of a 2-segment sub-capacitance array.The high sampling makes the coupling capacitance a unit capacitance and solves the problem of fractional capacitance mismatch.The capacitor switching method based on common mode voltage applied in this paper greatly reduces the power consumption compared with the traditional mode.Based on this structure, the corresponding output misalignment calibration 4-stage pre-amplification plus latching comparator module is designed.The sampling rate of the ADC is 250KS/s, and the simulation results show that its SNDR can reach 90.2 dB, ENOB can reach 14.69 bit, and the average power consumption is 2.507mW under the condition of 5 V supply voltage.

Figure 1 .
Figure 1.Structure diagram of SAR ADC in this article

Figure 2 .
Figure 2. Basic architecture of Vcm-based structured SAR ADC

Figure 4 .
Figure 4. DAC module diagram of fully differential segmented capacitor network based on Vcm-based

Figure 5 .
Figure 5. Structure diagram of high-precision comparator

Figure 6 .
Figure 6.Ramplifier circuit diagram Figures 7.Dynamic latch circuit diagram3.Results and DiscussionThe 100 Monte Carlo simulation results of the comparator with the pre-amplified circuit using the output out-of-phase storage calibration method indicate that the average offset voltage is 162.253nV and its standard deviation is 4.10 μV, as shown in Figure8.Therefore, the offest voltage of the designed comparator is much less than 1/2LSB voltage, which satisfies the design of this comparator.

Figure 8 .
Figure 8.The monte carlo simulation results of calibrated comparator offset voltage with preamplifier circuitry

Figure 9 .
Figure 9. FFT spectrum of 4096 sampling points after adding transient noise In order to verify the low power consumption characteristics of the designed SAR ADC, transient simulation of the whole circuit is carried out for 1000 sampling cycles to obtain the total transient current waveform of the circuit, and the current waveforms of the first 5 cycles are shown in Figure10.The effective current is calculated to be 501.4μAand the total power consumption is 2.507mW by Calculator tool.The results show that the SAR ADC designed in this paper meets the design requirements of low power consumption.

Figure 10 .
Figure 10.Current waveform for the first 5 cycles TABLE I. PERFORMANCE COMPARIOSN

TABLE I
TableIgives a summary of the performance of the ADC from simulation results and a comparison with other recent SAR ADCs.Fs is not competitive with other SAR ADCs, but FoMs is larger and SNDR is higher than other SAR ADCs.