Review of RF microsystem packaging process technology

The 3-D heterogeneous integration technology of microsystem is the best technical means to achieve higher integration, higher performance and higher working frequency of radio frequency (RF) electronic system. RF microsystem integration technology is categorized into three main types based on the packaging substrate: silicon-based, ceramic-based, and resin-based. In this work, the principle of RF microsystem integration technology is demonstrated in detail, and the process routes and characteristics of different packaging structures are clarified. Moreover, through the multi-dimensional comparison of different packaging structures, the application conditions of specific packaging structures are obtained. According to the comprehensive evaluation, the resin-based embedded chip package shows outstanding potentials in RF performance, integration capability, batch production capability and process cost. However, there are three shortcomings that limit its application in RF microsystems: Firstly, in terms of the universality of RF chips, metal grounding on the back of RF chips cannot be realized by this packaging, and special design of RF chips is required. At present, however, the universal chip with gold back grounding on the market cannot meet the requirements of the packaging process. Secondly, because of the high cost of customized chips, this packaging process is not suitable for small-scale production. Thirdly, the resin-based package does not have the sealing function, thus reliability of the product still needs to be verified. Ceramic-based RF microsystems do not require customized chips and have advantages in chip versatility compared to resin-based systems, with integration capabilities comparable to resin-based systems. However, its batch production capacity is much lower than resin based. In contrast, the silicon-based embedded chip package is as excellent as the resin-based products in chip versatility, RF performance, integration capability, batch production capability, etc., except that the manufacturing cost is high, and the yield should be effectively guaranteed in the manufacturing process. The conclusion provides a guidance for the future research of RF microsystem integration technology.

equipment design methods and implementation means, which is an important means to achieve electronic information equipment.
The advantages of RF microsystem are as follows: 1) With the short interconnection length, low delay, low loss, and support for heterogeneous integration, different chips and various passive components are integrated into a single package, which can achieve more complex and high-performance overall system [10][11][12][13].
2) The manufacturing process of adopting standard BGA for external connection without various RF and DC connectors is highly normative and universal.Therefore, the manufacturing period of new products is shortened and the manufacturing cost is reduced, which is more suitable for batch production [14][15][16].
3) The RF, digital, power supply and antenna units contained in the RF micro-system can be connected at the board level through the mature SMT process instead of cables, which effectively reduces the product size and significantly improves the system integration density and reliability [17][18].
Based on the significant advantages of RF microsystems, the technology of RF microsystems has developed rapidly, and the products have been widely used in civil and military fields.
The research results of automobile radar released by Singapore S-STAR Research Institute show that it has realized a 77GHz automobile radar using TSV technology and embedded packaging technology, as shown in Figure 1.[19].
Figure 1 77GHz radar of A-STAR Institute based on wafer level RF microsystem package [19] Shanghai Jiaotong University and the Chinese Academy of Engineering Physics jointly developed a W-band radar, which integrates an X-band track phase-locked loop chip, a W-band SiGe millimeter wave front-end chip and a GaN power amplifier adopting the MEMS photosensitive composite film RDL process, as shown in Figure 2. [20].

Figure 2
Physical schematic of W-band radar assembly [20] The 60GHz silicon interposer developed by LETI in France integrates the T/R micro-system as shown in Figure 3. [21].The TSV interposer adopts 120μm high resistance silicon material as the substrate， and the diameter of the via is about 60μm, and the thickness of the conformal electroplated copper metal layer in the via is not more than 10μm.The high resistance silicon interposer is connected with the RF transceiver chip by flip chip bonding, and the diameter of the micro bump is 80μm.The interposer is interconnected with the external PCB through the BGA to form the millimeter wave transceiver microsystem.

RF Microsystem Packaging Structure and Process
The basic framework of RF microsystem is stacked by high-density interposers.According to the difference of interposers material or integration process, RF microsystems can be classified into two types.According to the interposers materials ，there are three categories of RF microsystems silicon-based ，ceramic-based，and resin-based.On the other hand, based on the differences in the internal RF chip installation and signal interconnection methods, RF microsystems can be classified into surface-mounted and embedded types.Surface mounting means that the chip is directly mounted on the surface of the interposer, and the signal connection between the chip and the interposer is completed through wire bonding; However, the chip in the embedded type is mounted in the cavity of the interposer, and the signal connection is completed by RDL.Due to the difference in material characteristics, silicon and ceramic-based RF microsystems can be realized by surface-mount and embedded type, while resin-based RF microsystems mainly adopt the latter at present.2.1 Silicon-based (Sib) RF Microsystems

Silicon-based surface-mount (SibSM) RF microsystem
The SibSM RF microsystem utilizes silicon interposers for support，with surface-mounted core chips and wire bonding for signal readout ， as depicted in Figure 5.The product is a broadband RF transceiver microsystem based on silicon MEMS technology, in which GaAs multi-function chip (MFC) and MEMS filter are integrated into one silicon chip.The overall size of this X-band RF transceiver module composed of four layers of interposers is about 25mm × 18mm × 1mm [24].
The packaging process of the product is depicted in Figure 6，where the interposers labeled as A，B，C， and D are individually processed before being separated into two groups for wafer-level bonding.Specifically， interposers A and B are joined together，while interposers C and D are bonded.Then, two sets of hybrid interposer wafers are diced into dies in which GaAs MFC and MEMS filter chips are embedded by the adhesive bonding technology, and the signal is led out by wire bonding.Finally, two sets of hybrid interposer chips are bonded by the chip-level bonding and stacked into RF microsystems.The complete detailed process flow of SibSM RF microsystem is as follows: (a) Figure 6 Packaging Process Flow of X-band Transceiver Microsystem 1) Processing of interposers: in order to reduce the difficulty of processing, the side-wall metallization of TSV technology is generally used to make the interposer independently, which can be completed by using a more mature and a lower cost electroplating process； 2) Wafer-level bonding of two interposers: two interposers are bonded together by applying certain pressure and temperature, and usually the bonding temperature is about 330 ℃； 3) Dicing: Dice the hybrid interposers into single chips using a precision dicing system； 4) Adhesive bonding: During the manufacturing process ， the chip may undergo various temperature gradients when adhesive bonding.To enhance the reliability of chip bonding，the commonly chosen adhesive bonding technique is Ag-sintered technology， which undergoes a curing process at approximately 200 ℃.This technology can endure high temperature processes up to 350 ℃ after curing.
5) Wire bonding: The process utilized to establish electrical signal connections between various chips as well as between chips and substrates.In order to ensure the effective transmission of RF signal, the arch height of gold wire should be strictly controlled； 6) Chip-level bonding: The completion of multilayer interposers stacking is achieved through chip-level bonding technology.

Silicon-based-embedded (SibED) RF microsystem
The SibED RF microsystem consists of silicon interposers that have core chips embedded within them.The surface of chips is usually covered with photosensitive intermediary materials as a protective layer, and then Re-Distribution Layer (RDL) technology is applied for signal extraction.Figure 7 shows a T/R RF microsystem product and its package structure，which is stacked by fourlayersof interposers with an overall dimension of 20mm × 20mm × 1.5mm [25].The manufacture flow of the package is demonstrated in Figure 8, which mainly includes the embedding of heterogeneous chips, RDL interconnection and high-precision multilayer interposers stacking process.In this paper, the side with chip embedded in the interposer in Figure 8 is defined as the back side in the followings.f) Create a cavity on the rear side of the interposer via the etching process to incorporate the chip.
g) The cavity of the interposer is coated with nano silver paste, and the chip is embedded into the cavity by the adhesive bonding technology.
h) RDL is performed on the front surface of the chip and the interposer to interconnect the PAD of the chip with the TSV of the interposer.
2) Fabrication of interposers B and D: The interposers B and D follows a similar process flow as described above，with the exception that there is no need to etch the cavity for chip embedding in interposers B and D.
3) Bonding and stacking: a) Two modules are formed by A and B, C and D respectively through wafer-level bonding, which are defined as hybrid interposers, as shown in Figure 9.

Ceramic-based (Ceb) RF Microsystems 2.2.1 Ceramic-based surface-mount (CebSM) RF microsystem
The CebSM RF microsystem is supported by high/Low temperature co-fired ceramic (HTCC/LTCC) substrate.the core chip is surface mounted, and the signal is read out by wire bonding.The schematic diagram of broadband channel microsystem product and its packaging structure is shown in Figure10, which shows that the product is stacked by two layers of HTCC substrates with an overall dimension of about 21.1mm × 16mm × 5mm [26].The specific packaging process is as follows: 1) The UBM layer is applied to both the first and second layer of the HTCC substrate.
2) The micro bumps are fabricated on the UBM layer.
3) The first layer of HTCC substrate is bonded to the shell surface by flip-chip bonding technology.4) The bare chip is bonded to the first layer of HTCC substrate by surface mounted technology.5) The second layer of HTCC substrate is inversely bonded to the surface of the first layer of HTCC substrate.6) The bare chip is bonded to the second layer of HTCC substrate by surface mounted technology.7) Shell capping.8) Ball gate array(BGA) is planted on the bottom of the shell.

Ceramic-based embedded (CebED) RF microsystem
The CeBED RF microsystem utilizes a substrate made of high/low temperature co-fired ceramic (HTCC/LTCC) for support.The core chip is embedded in the cavity of ceramic substrate, and the surface of chip and substrate are covered with a photosensitive intermediary layer.RDL technology is performed for signal extraction.The typical product and packaging structure is shown in Figure 11, which is stacked by two layers of LTCC substrates.The core RF chip is embedded in the LTCC substrate, and the surface is covered with Benzocyclobutene (BCB) film.The overall dimension of the product is about 9mm × 9mm × 1.1mm [27].

Figure 11 Schematic diagram of K-band receiving and transmitting amplifier microsystem products and
packaging structure [27] The packaging process of the product is generally as follows: 1) The LTCC multilayer substrate is processed according to the circuit diagram.
2) RF circuit chip is embedded in LTCC cavity by Au-Sn eutectic welding technology.
3) Fabrication of gold micro bumps on RF chip surface.4) The RF LTCC substrate surface is spin coated with BCB film, and the micro connection between the micro bumps on the chip surface and the RF line is realized through multiple photolithography and electroplating technology.
5) Ball planting balls at the bottom of RF LTCC substrate.
6) The control circuit chip is directly mounted on the upper surface of the LTCC substrate, and the signal interconnection is realized by wire bonding technology.
7)Ball planting at the bottom of control circuit LTCC substrate.
8) The interface between control circuit LTCC substrate and RF LTCC substrate is connected through BGA solder ball.

Resin-based (Reb) RF Microsystem
The Reb RF microsystem utilizes the fanout wafer-level packaging technique ， which enables the placement of numerous RF and digital chips within a confined space through wafer reassembly.Subsequently， state-of-the-art manufacturing processes are employed to accomplish RDL and bump preparation.After dicing and separation, the package can realize electrical performance interconnection with external substrate [28].The Reb RF microsystem packaging technology can be categorized into three types chip first/face down，chip first/face up，and chip last packaging.A typical product with an overall dimension of about 27mm×27mm ×0.43mm and its packaging process which adopts the first one packaging technology are shown in Figure 12 and Figure 13., respectively [29].
The flow of the packaging process for the multi-channel T/R module is depicted in Figure 13. 1) The glass carrier is pasted with a temporary bonding film.
2) RF chip and digital chip are mounted to the set position by high-precision chip mounter.
3) The chips with glass carrier are integrally laminated to form a resin wafer by using wafer level plastic packaging technology.4) De-bonding and separate the carrier.5) After the surface of chips is passivated, the window area is exposed through photolithography and etching process, and then RDL is formed by physical sputtering, electroplating and photolithography technology.6) BGA is fabricated at the bottom of the substrate through the ball planting technology, and then the substrate is sliced to form separately packaged RF microsystems.

Discussion of Different Packaging
In summary， due to the limitation of the application of metal grounding on the back of RF chips， RF chips in RF microsystem packaging are predominantly oriented face up.As a result，the process technology for RF microsystem integration can be categorized into two methods: chip surface mounting and chip embedding.The application characteristics of the two packaging methods are shown in Table 1.In terms of packaging process, except for the micro processing technology adopted for interposer manufacturing, the other processes of RF chip surface mount packaging method usually employ the traditional micro assembly adhesive bonding technology, which is relatively mature and easy to implement.On the other hand, RF chip embedded packaging method is completely implemented by micro process technologies such as RDL.Currently ， the low yield is attributed to the relative complexity of this process.In terms of chip universality, except that RE packaging methods require special design for chips, other methods can take into account the mainstream chip design methods in the market.From the perspective of RF signal transmission, embedded-type adopts micro process technology such as RDL to realize signal interconnection, resulting in short transmission path and better high-frequency performance.In respect of integration capability, the interposer of SiBE package is compatible with CMOS process and has the ability to integrate various active and passive devices.In addition, for airtight assurance, the double-layer interposers are able to achieve sealing after bonding without any aid of the sealing bodies, resulting in higher integration under the same volume.In terms of batch production capacity, the RE RF package involves fewer processes and no stacking designs.In addition，wafer-level manufacturing makes it more suitable for mass production.In regard of cost，the RE RF package does not require packaging substrates，TSV and other cumbersome processes，which leads to a relatively simple manufacturing process ， thus reducing the process cost.The process of SB package is complex and costly.However, as it is compatible with wafer-level processing technology, it can be used for mass production.The manufacturing process of CB package is mature and flexible with no demand for customized chips.However, due to the high substrate manufacturing price, it is more suitable for small batch product development.
According to the comprehensive evaluation, the resin-based embedded chip package shows outstanding potentials in RF performance, integration capability, batch production capability and process cost.However, in terms of the universality of RF chips, metal grounding on the back of RF chips cannot be realized by this packaging, and special design of RF chips is required.At present, however, the universal chip with gold back grounding on the market cannot meet the requirements of the packaging process.Moreover, because of the high cost of customized chips, this packaging process is not suitable for small batch products.In addition, the resin-based package does not have the sealing function, thus reliability of the product still needs to be verified.In contrast, the silicon-based embedded chip package is as excellent as the resin-based products in chip versatility, RF performance, integration capability, batch production capability, etc., except that the manufacturing cost is high, and the yield should be effectively guaranteed in the manufacturing process.

Conclusion and prospect
In conclusion, this work describes the process architecture of RF microsystem integration technology.RF microsystems are categorized into three types based on different packaging substrate materials: silicon-based， ceramic-based ， and resin-based.Ulteriorly, according to the way the chip is integrated into the package substrate, silicon-and ceramic-based RF microsystems can be classified into surface mounted and embedded types.By comparing the five typical packaging structures and their manufacturing methods, the application conditions of different packaging structures are clarified, which provides effective guidance for the development of RF micro system integration technology.RF microsystem packaging technology will find extensive applications as microsystem technology advances.But at present, RF micro-system packaging still faces many technical challenges, including electromagnetic shielding in the package, overall thermal management, manufacturing cost and long-term reliability.The above research needs to be strengthened to promote the further maturity and application of RF microsystem technology.

Figure 3
Figure 3 Schematic diagram of LETI 60GHz Si interposer Northrop Grumman/Qorvo team adopts copper bumps, chip embedded, chip RDL fan-out, hot-via and other interconnection structures, combined with the multi-temperature gradient bonding technology, to realize three-dimensional stacked interconnection of silicon interposer, SiGe active interposer and CMOS chip [22].The millimeter-wave RF microsystem developed by Chung-Hao Tsai team adopts the InFO-WLP process to integrate the RF chip and antenna, and the external interface is led out by standard BGA,as shown in Figure 4 [23].

Figure 4
Figure 4 Schematic diagram of millimeter-wave RF microsystem: (a) Cross section of double-sided InFO WLP sample and (b) System architecture of RF chip and array antenna on InFO WLP At present, the packaging technology research of RF micro-system is relatively extensive, and the packaging forms are diverse.This paper combs the system framework of RF microsystem process integration technology, and compares different packaging processes to clarify their specific application conditions.

Figure 5 X
Figure 5 X-band transceiver microsystem: (a) Physical and (b) Schematic diagram of packaging structure[24]

Figure 7
Figure 7 T/R RF Microsystem Products: (a) Physical and (b) Schematic Diagram of Packaging Structure[25]

Figure 8 T
Figure 8 T/R RF Microsystem Packaging Process Flow Diagram 1) Fabrication of interposers A and C: a) TSV blind holes with different depths are formed in silicon interposers by dry etching technology.b) Passivation layers were deposited，and metal was filled by electroplating in the via.c) RDL is performed on the surface of the interposer.d) Temporary bonding between the interposer and glass carrier.e) The copper pillars within the via are revealed on the back of the interposer through the process of chemical mechanical polishing(CMP).f)Create a cavity on the rear side of the interposer via the etching process to incorporate the chip.

Figure 9
Figure 9 Schematic Diagram of Two Hybrid Interposers b) The hybrid interposer is sliced to obtain a single chip module.c) The single-chip modules are stacked and interconnected through flip-chip bonding to form a RF microsystem.

Figure 10
Figure 10 Schematic Diagram of Broadband Channel Microsystem Products and Packaging Structure[26]

Table 1
Application Comparison of RF Microsystem Packaging Process RF chip adopts surface mounting and embedding for chip integration