An accelerated modelling method of full-bridge modular multilevel converter considering dead-time

To avoid short-circuits of the same side switching of power converters, the dead time is of significance in the pulse trigger gating signal for full bridge modular multilevel converter (FB-MMC). However, the previous equivalent models use the binary resistance switching model to equivalent the switching state which is impossible to simulate the switching with dead time, and the detailed model (DM) with higher levels is time-consuming and inefficient in electromagnetic transient (EMT) simulation. To address this problem, based on the state-space averaging method, a speed-up average value model (AVM) of FB-MMC considering dead time is proposed. Firstly, the working state of FB-MMC is obtained through analysing the switching states with dead time and is classified into three cases according to the capacitor. Secondly, derived from state-space equation, the three cases are integrated into a unified model by introducing the duty cycle, and then the equivalent controlled source is used as the interface circuit between the external grid and capacitor. Finally, a 49-level two-terminal MMC-HVDC system consisting of FB-MMC is constructed in PSCAD / EMTDC simulations, showing that the proposed AVM compared with DM has high accuracy and operation efficiency.


Introduction
In practice, the switch devices in full-bridge modular multilevel converter (FB-MMC) have non-ideal features, and dead time is obligated to be introduced to prevent straight-through between the upper and lower switches on each bridge arm of full bridge submodules (FB-SMs) from short-circuits fault [1] .The introduction of dead time will induce many adverse dead-time effects on system operations, including outputs amplitudes reduction, output quality distortions, arm inductor voltage increment, and zerocurrent-clamping phenomenon [1][2] .With the rapid development of SiC power semiconductor technology, the switching speed of power devices has been greatly improved, and dead-time effect is more and more notable [3][4] .Thus, the dead-time effect is one of the most significant issues for FB-MMC.
Researches on dead time for power devices can be generally divided into two categories: compensation of dead-time effect and analysis modelling of switching with dead time.The compensation of dead-time effect category achieves dead-time compensation through control pulse width angle selection [5] , injection voltage error compensation [6] or multivariable control [7] , etc.However, since the existence of inductor current ripple and parasitic capacitance, it will add some difficulty to data detection, and the dead-time compensation effect is not ideal.The adverse effects of dead-time on

Topology structure and port characteristics of FB-MMC considering dead time
The topology of FB-MMC is given in figure 1, which consists of three phase legs.Each phase leg contains two bridge arms composed of N sub-modules in series.Udc and Idc are the amplitudes of DC voltage and current respectively, ua, ub and uc are the AC voltages, LS is the arm inductor, ijp and ijn are the phase currents of upper and lower arms, where j = a, b, c.The topology of FB-SMs is given in the dotted box.Each FB-SMs consists of four IGBT with a reverse parallel diode and a capacitor.iSM, uSM and uC are the input current, output voltage and capacitor voltage respectively.There are four working states of the FB-SMs, which are positive input, negative input, bypass and locking state.Under the ideal states of ignoring dead time, there are five switching modes in the operation states, that is, T1 and T4 are turned on, T2 and T3 are cut off when positive input, T2 and T3 are turned on, T1 and T4 are cut off when negative input, T1 and T3 are turned on, T2 and T4 are cut off or T2 and T4 are turned on, T1 and T3 are cut off during bypass and no IGBT is turned on during blocking.However, in practical engineering applications, in order to avoid the directly short-circuit fault of the complementary switching, the pulse trigger signal needs to introduce the dead-time delay, that is usually to avoid simultaneous conduction at the cost of simultaneous shutdown of two sets of switches in a short time.In other words, when the FB-SMs changes from one working state to another state, the rising edge trigger signal needs to be triggered after a dead time delay, while the falling edge trigger signal does be triggered normally.Consequently, the dead-time delay control method will cause the switching signal to have only one IGBT turned on during the dead-time.Therefore, the four working states of the FB-SMs are transformed from the five switching modes of the ideal situation to the nine switching modes of the actual project.Considering the dead time of the actual switching mode and FB-SMs port output voltage is given in table 1.

Electromagnetic transient equivalent acceleration modelling for FB-MMC
It can be seen from table 1, according to the port output voltage, that the nine switching modes considering the dead time can be divided into three cases regardless of current direction and switching mode.Three cases of current flow path are given in the figure 2. Taking case 1 as an example, the FB-SMs capacitor voltage uC and bridge arm current iarm are selected as state variables, and the positive direction is shown in figure 2(a).According to Kirchhoff 's voltage and current law, write the state space equation of the form dX/dt=AX+B as follows: In equation (1), Ron represents the resistance of the switching device when on.Similarly, the state space equations of case 2 and case 3 can be obtained as follows: Based on weighted average method, the periodic average operator for each state can be obtained.According to Euler formula, the three periodic average operators are integrated in the TS length interval and unified equation can be obtained: Where g1, g2, g3 stands for the duty cycle of state one, two and three in the period TS respectively.Simplify equation ( 4) and the state space average equation of FB-SMs in one cycle TS can be obtained: The FB-SMs mathematical model can be obtained by equation (5), and also FB-MMC bridge that the FB-SMs are cascaded mathematical model can be established.The equivalent AVM is shown in figure 3, and corresponding expressions are show in equation ( 6).

Simulation and verification
To verify the accuracy and acceleration of the proposed model, a DM and AVM of the 49-level twoterminal MMC-HVDC system consisting of FB-MMC, as shown in figure 4, are built on PSCAD/EMTDC.The total simulation duration is set as 1.2 s, which a metal grounding short circuit fault occurred at 0.75s, and the system recovered from the fault at 0.755s.The test system parameters are shown in table 2.   From the comparison diagram and the simulation relative error calculation results, it can be seen that the AVM is highly consistent with the simulation results of the DM in the steady-state stage, and the simulation trend is basically the same in the fault recovery transient stage, indicating that the AVM proposed in this paper can accurately simulate the DM considering dead time.

Speedup factor test
A DM and AVM of the FB-MMC open-loop model with 31, 41, 51 and 61 levels are respectively established, and the CPU time is recorded by the PSCAD/EMTDC built-in function to evaluate the speedup effect of AVM.The simulation time-step is set to 5us, the duration is 5s, and the configurations of CPU is Intel Core i5-1030NG7.The corresponding speedup factor of 31, 41, 51 and 61 levels are 16.55, 24.29, 29.49 and 67.53, respectively, indicating that the speedup effect can further increase as the number of FB-SMs increases.AVM is especially suitable for multi-MMC integrated applications such as multi-terminal DC transmission with high levels.

Conclusions
This paper proposes AVM of FB-MMC considering dead time, based on the state space averaging method.The equivalent model has high accuracy and significant acceleration effect under steady-state and transient conditions.In addition, this model considers the dead time of the switch, which makes up for the defect that the previous equivalent model uses the binary resistance to establish the IGBT mathematical model and cannot simulate the dead time.At the same time, the actual capacitance of the FB-SMs is retained, which can realize the simulation of the charging and discharging process of a single FB-SMs, and effectively improve the equivalent accuracy.Also, the equivalent speed-up model is simple in structure, easy to expand, and has certain reference significance for other models with power switching elements.

Figure 1 .
Figure 1.Topology of an FB-MMC and FB-SMs.

Figure 2 .
Figure 2. The current flow path of each condition: (a) Case one; (b) Case two; (c) Case three.

Table 1 .
Switching modes and port voltage.

Table 2 .
Parameters of the MMC-HVDC.Figure5(a) is the simulation results of FB-MMC active power transmission.The average relative error in steady state is 0.07 %, and the maximum relative error in transient stage is 5.54 %.Figure5(b)is the simulation results of the arm current of the FB-MMC.The average relative error in steady state is 2.79 %.Figure5(c) is the simulation result of the FB-SMs capacitor voltage.The average relative error in steady state is 2.42 %, and the maximum relative error in transient stage is 6.08 %.