Research on FPGA-based dual-channel time synchronization system

As geological exploration progresses in depth and scope, the distance between transmitting and receiving systems also increases. Consequently, the synchronization of time between the two becomes an increasingly critical issue. In response, this paper presents a proposed design for a time synchronization system that is suitable for use between transmitting and receiving equipment. The system uses GPS as the main clock source. The information within the GPS system will be encoded and decoded using the FPGA. This allows us to obtain both UTC time and the time of the IRIG-B code format, enabling compatibility with the various system interfaces. Our experiments have confirmed that the system has a time error at the microsecond level, and the precision satisfies the design requirements. This verifies the validity and reliability of the system.


Introduction
In contrast to small-scale and shallow geological surveys, large-scale surveys require synchronized data reception from multiple devices distributed throughout the survey area.Due to the large geographical distances between them, the previous practice of achieving time synchronization through wired communication is no longer applicable.Based on the above issues, mainstream time communication protocols are used, and therefore time synchronization requirements must be strictly adhered to ensure the reliability of data acquisition.
The GPS synchronization method is to receive the standard time signal transmitted by the satellite in orbit through the GPS receiver.Then, the time information is decoded and encoded according to specific requirements and sent to each device to realize the time synchronization function.At home and abroad, IRIG-B has been widely used in power systems and is a mature mainstream time synchronization [1].And with the development of chip technology, there are a variety of chips as the choice of processing unit [2], can be selected by the designer according to power consumption, cost, use of scenarios, and other practical needs of different programs, such as ZYNQ, FPGA + DSP, FPGA + ARM, MCU and other different programs [3].The FPGA master chip program with a short development cycle, fast parallel processing speed and reasonable cost is used in this design.According to the actual demand, the second pulse signal is used as the reference flag, and the IRIG-B code is the final output signal.

Introduction to IRIG-B Code
In this paper, we have designed a time synchronization system based on the FPGA-based IRIG-B code.The reliability of the system has been verified through field exploration operations and proved to be well-suited for complex environmental conditions in the field.It is worth noting that the IRIG time code has six formats, each with different code periods, code rates, and time information.Among these formats, the most widely used and accurate one is the IRIG-B code.
Figure 1 illustrates the three code element formats.IRIG-B code period lasts for 10 milliseconds.During this time, high and low levels are controlled to indicate "1 code element", "0 code element", or "P code element".It is crucial to maintain the output level within this 10 ms window.Consequently, it is necessary to control the output high and low levels within 10 ms, define the output array as 1000 bits, and transmit it at a rate of 1000 bits per second [4].When outputting a "P" code element, it is necessary to output a high level in the first 8 milliseconds and a low level in the last 2 seconds of the code element cycle [5].When outputting a "1" code element, it is necessary to output a high level in the first 5 milliseconds and a low level in the last 5 seconds of the code element cycle [6].When outputting a "P" code element, it is necessary to output a high level in the first 2 milliseconds and a low level in the last 8 seconds in one code element cycle.After obtaining the year, hour, minute, second, and time data, generate the corresponding array based on each value, and output it in accordance with the format of the IRIG-B code [7].

Hardware Structure
The hardware portion of the system is shown in Figure 2. The system's hardware circuit comprises four components.The GPS antenna receives GPS signals and sends them to the time receiving circuit for processing [8].Once the circuit receives the satellite signals, it transmits time information to the FPGA via a serial port.The FPGA extracts, decodes, and encodes the information before outputting it to the equipment requiring time synchronization.Then, the FPGA extracts, decodes, and encodes the initial time data to obtain the IRIG-B code, which is ultimately transmitted to the equipment requiring time synchronization.

Time Receiver Circuit
The schematic diagram of the time receive circuit is shown in Figure 3.The time receiving circuit employs a custom GPS timing chip, the LEA-6T, manufactured by U-Blox in Switzerland.The circuit produces a second pulse 1PPS signal with a GPS time error of less than 15 ns.Its functions include acquiring current time information and accessing the second pulse signal to calibrate time with high accuracy.

FPGA Selection
This design utilizes the EP4CE15E22C8N chip as the primary control chip.The chip is capable of achieving a maximum processing speed of 400 MHz and features four internal PLL clocks, each of which has five clock outputs for frequency reduction and frequency doubling to maintain clock synchronization as per the project's requirements.Additionally, the chip contains an embedded multiplication unit that, when coupled with existing IP cores, significantly shortens the R&D cycle for the project [9].Furthermore, the external IO ports are diverse, enabling communication with various devices for data processing [10].The chip features an included multiplier unit that significantly shortens the project development time, along with the current IP cores.
The FPGA acquires GPS message data in GPRMC format via the serial port.It verifies the accuracy and completeness of the frame header $GPRMC and the time valid flag bits, completes 30 detection cycles, and confirms the validity of GPS time.It then extracts time information from the message format's various positions, providing the precise UTC time.

System software design
The system flow is shown in Figure 4.After the system is turned on, the time receiving circuit sends GPS data to the FPGA via the serial port.However, the initial GPS signal is unstable due to the insufficient number of locked satellites, so the FPGA continuously detects the received data until the valid bits are identified as such.The system's counter will tally the data, and once the counting time reaches three minutes, it can be confirmed that the system has achieved stable operation.From this point, the FPGA will commence the conversion of the time data format.The ASCII information received is first converted to 8421BCD code format before combining with the TOD value and adhering to the three basic code elements format of the IRIG-B code.
It is known that a basic IRIG-B code element period is 10 milliseconds, and it is necessary to limit the high and low level time in it to achieve the purpose of outputting different code elements, so a code element period is divided into 10 parts, the length of time of each part is 1 millisecond, and then the high and low level of each 1 millisecond is controlled according to the type of code element to be output.

System testing
Figure 5 displays the actual IRIG-B code waveform outputted by synchronously outputting the code using the DL850 Yokogawa oscilloscope recorder while observing the waveform at the rising edge of the 1PPS signal.The first code element is the "P" code element, used to locate the flag bit.Technical term abbreviations will be explained when introduced.The 8-bit code element displays time information that corresponds with the "1" code element's output.Each of the next ten bits of the code element appears once in the middle of the two "P" code elements.The "0" code element directly follows the second information expressed in the 8-bit code element.The minutes, hours, years, and other information follow in turn.The output of the IRIG-B code from the system is connected to the external time interface of the DL850 device via a coaxial cable to reduce external interference.Once connected, the equipment status is monitored.Figure 7 demonstrates the equipment's time display when the system is not operating, indicating that it is not locked while Figure 8 shows the equipment's display once the system is operating regularly, demonstrating that it is locked.This concludes that the IRIG-B code output from the system is valid.

Conclusion
The time synchronization system presented in this paper utilizes GPS as the signal source and FPGA as the primary control chip.It has the capability to produce UTC time, IRIG-B code, and pulse per second signal.By measuring the output waveform of the system and verifying equipment accessibility, the time synchronization function can be achieved, allowing for stable, long-term operation.Further, measurement of the rising edge of the 1PPS and IRIG-B time waveforms demonstrates that the system error aligns with design requirements, making it suitable for a broad range of industrial and scientific exploration applications.

Figure 6 .
Figure 6.Rise time of 1PPS and IRIG-B.The output of the IRIG-B code from the system is connected to the external time interface of the DL850 device via a coaxial cable to reduce external interference.Once connected, the equipment status is monitored.Figure7demonstrates the equipment's time display when the system is not operating, indicating that it is not locked while Figure8shows the equipment's display once the system is operating regularly, demonstrating that it is locked.This concludes that the IRIG-B code output from the system is valid.