Design of an acoustic direction finding system based on split array frequency domain beamforming algorithm

According to the technical requirement, the principle of the acoustic direction finding and positioning algorithm is introduced, and based on the engineering implementation requirements of split array frequency domain beam forming algorithm, a hardware implementation method based on FPGA +DSP is introduced, which use FPGA to realize the logic control and two pieces of MS320C6678 multi-core DSP to realize the digital beam forming. The hardware system design scheme can realize the program-controlled amplification, filtering, collection, real-time data storage and beam forming processing of the multi-channel acoustic analog signals for acoustic receiving array. At the same time, it can also communicate with the upper computer to achieve upper computer instructions, data transmission, and parameter settings. It has been verified through engineering practice that this scheme has high data processing efficiency and reliable direction finding calculation effect.


Introduction
The 21st century is an important period for the utilization and development of marine resources.With the continuous exploitation of marine resources, the number of ships, autonomous underwater vehicles (AUV), marine facilities, and personnel entering the ocean has significantly increased, which puts forward more urgent requirements for improving the ability of emergency search and rescue support at sea.Due to the severe attenuation of electromagnetic waves when propagating in water, acoustic communication is currently the only form of communication that can remotely transmit information underwater [1][2].So currently, the main method for emergency search and rescue at sea is to install underwater acoustic positioning beacons on equipment, which locate their positions by transmitting signals [3].The beacons emit CW pulses with a certain frequency and acoustic equipment is invented for searching for acoustic beacon signals on the sea surface.For example, when an aircraft crashes into water, the underwater acoustic beacon installed on the black box automatically sends a specific frequency of ultrasonic pulses that cannot be heard by the human ear, similar to the underwater "SOS" indicating sound source of the searched target.This pulse signal can be detected by sonar and acoustic positioning instruments.Underwater acoustic beacons have gradually expanded from traditional applications such as aircraft and ship black boxes to various fields of maritime operations.Therefore, the search and positioning equipment for underwater acoustic beacons has also gradually developed and expanded, from shipboard suspended equipment to various types such as shipborne towed, UUV autonomous, and aircraft airdrop [4].
This article proposes a hardware implementation scheme for the search and positioning of underwater acoustic beacon signals based on the split array frequency domain beamforming direction finding algorithm.This scheme has the advantages of fast data processing response and high reliability, and has

Direction finding algorithm
The signal-to-noise ratio gain of splitting cross correlation processing with the same number of array elements is half of that of square integral processing, which reduces by 3dB [5].However, the splitting cross correlation processing takes advantage in the directionality.That is because the split array cross correlation output undergoes a great jump in the mean value of the signal from zero to the appearance of the target, which is more sensitive than the square integral processing (jumping from the average noise intensity).Therefore, split cross correlation processing is used to accurately determine the target position in passive sonar [6][7][8].
In order to analyze the principle of split array direction finding, we first look into the situation of two hydrophones receiving signals, as shown in figure 1.Let the angle between the incidence direction of signal and the normal direction of the edge line of the element be .If the received signal of the left element is marked as () st , then the right element signal arrives () x , and the right beam is marked as r x .
Taking single frequency signal f as an example.Let the left beam signal be Among them Similarly, the expression for the right beam signal () r xtcan be obtained.When their amplitudes are the same, the only difference between the left and right beams is the delay.We consider, Among them, Im and Re represent the real and imaginary parts of complex numbers, respectively, so Im ( ) 1 ˆarctan 2 Re ( ) G. H. Knapp pointed out that using this method the Cramer-Rao Lower Bound estimated is Among them, T is the observation time, () When the input signal-to-noise ratio is low, In the simplest case, if both () Next, we need to seek a relationship between  and .
Regarding the optimal and precise orientation of linear arrays, we first discuss the split beam orientation of linear arrays.Consider left beam signal 1 () So the left beam signal is Similarly, a right beam signal can be obtained sin 2 arctan sin cos 2 Similarly, the phase of the right beam can be calculated

Hardware System Design Scheme
The functions implemented by the hardware circuit include collecting analog signals from one hydrophone and 16 linear arrays, programmable amplification and filtering, achieving real-time storage and beamforming processing, and receiving real-time signals from various types of sensors (height, depth, temperature, salinity, attitude, water leakage).And real-time communication with the upper computer can be achieved through sending instructions to upload data download parameter settings for the board.
Based on the functions of the system, three boards are designed to be implemented, namely power management board, signal conditioning board, and acquisition control board.The hardware system composition is shown in figure 4.  The power management board provides power for the electronic devices of the system, achieving the function of power conversion.The signal conditioning module mainly consists of pre-amplification, filtering, automatic gain control, and other parts to achieve the pre-conditioning of analog signals [9].These two parts of the circuit are using mature circuit design, and will not be repeated here.

Signal Conditioning Board
The acquisition control board is the core module of the hardware system, which receives a total of 17 signals from two 8-element linear arrays and a single hydrophone, achieving functions such as acquisition and beamforming, target orientation calculation, sending and receiving communication instructions, and real-time uploading of calculated directional information.The core part of the acquisition control board in this scheme adopts an embedded structure of DSP and FPGA, with 2 DSPs as data processors and 1 FPGA as logic controller [10].The functional block diagram is shown in figure 5: This board includes two TI's TMS320C6678 eight core DSP processors, which are interconnected through HyperLink to achieve inter chip memory and peripheral sharing.On board is a SPARTAN6 FPGA chip from XILINX company, which has one 4x GTP interface interconnected with the SRIO interface of DSP0 to achieve high-speed data exchange of SRIO protocol, and another GTP interconnected with the SRIO interface of DSP1 to achieve data exchange of SRIO protocol.
The onboard external interface includes one gigabit network (from DSP0), one pair of RS422 (receiving and sending), and five RS485 transmissions.Two onboard EMMCs, each with a storage capacity of 64GB, add up to 128GB for storing and reading raw data.

FPGA logic design
The FPGA part mainly completes interface management and data communication with DSP; Collect AD conversion results of 18 analog signals and cache them; Implement initialization during power on or reset of DDR3 and eMMC, or write and read data during system operation; Receive gain setting instructions for analog sampling channels through the external memory interface (EMIF)of DSP6678.
There are two main interfaces between FPGA and DSP6678: EMIF and SRIO.EMIF is mainly responsible for transmitting system parameters and control instructions.The system parameters mainly include: data from the 5-way RS485 interface, gain control of the system analog channel, system time, initialization status of the storage module, and read/write start position of the eMMC module; The control instructions of the system mainly include: start storage, end storage, original data upload, etc.
The SRIO interface is used for data interaction with DSP6678.After receiving the start upload data instruction from DSP6678 from the EMIF interface, FPGA uploads the 18 AD sampling results cached in DDR3 to DSP through the SRIO interface.After the data transmission is completed, FPGA sends a hardware interrupt to DSP.During this process, FPGA must ensure that the bandwidth of SRIO uploading data is greater than the bandwidth of data generation, otherwise it will cause data loss.
After the FPGA receives the instruction from the DSP to read eMMC data, the eMMC control module reads the experimental data generated from the external eMMC FLASH.After first level caching, it is forwarded by SRIO to DSP6678.Every time 1M bytes are forwarded, a hardware interrupt is submitted to the DSP.
The 18 channel data signal is processed by the analog board signal and enters the MAX11904 chip; The 0-1v analog signal is converted into a 20 bit digital signal.In order to match the rate imbalance between data production and consumption, these signals need to go through DDR3 caching before being stored and forwarded.DDR3 has 18 signal storage channels, one eMMC cache data channel, one eMMC data read channel, and one SRIO data read channel; The read and write timing and priority of each channel need to be logically managed.The active Xilinx DDR3 IP only has six read and write ports.How to allocate more than 20 read and write requests to a limited number of six read and write ports requires detailed planning and design.
The priority planning adopted in this scheme is as follows: the storage priority of 18 analog signals has the highest priority, while the read and write priority of the other channels is arbitrated based on time polling.
Each sampling point has a data bit width of 20 bits and a storage bit width of 32 bits.Taking 192KHz as an example, the write data bandwidth of AD with 18 channels for DDR3 is: ( ) The cache channel bandwidth of eMMC is 13.824MByte;The total read and write bandwidth of DDR3 for the entire system is 13.824MByte X 4=55.296MByte.Not exceeding the indicator limit of DDR3 IP core.
EMMC work is divided into two stages: initialization stage and storage reading stage.The initialization of eMMC is mainly completed by FPGA.After the system is powered on and stabilized, DDR3 initialization is successful.Next, the eMMC control module enters the waiting to receive initialization instructions stage.Once receiving the initialization instruction from the DSP, the eMMC control module starts the eMMC initialization program.When initialization is complete, the signal eMMC_ INIT_OK will be pulled up, and EMMC enters read or store mode.Module eMMC_ DATA_ PACKAGE encapsulates data in a system agreed format.The output data of ADC is encapsulated into 20 bits, with channel indicator bytes added to the front, forming a 32-bit sampling point data, and 18 channels forming a sampling frame.
The system has a total of 18 analog sampling channels, each with a fixed gain and a digitally adjustable gain.
The gain digital control input from the upper computer transmitted to DSP6678 through the network port, and the DSP then transmits this value to the TVG SET MODULE of FPGA through the EMIF bus.The TVG SET MODULE uses the SPI bus to set the digital potentiometer TPL0501, and the set value is the value received through the EMIF bus.
Potentiometer TPL0501 divides the stable voltage of 2V and generates voltage TVG_1-1 corresponding to the digital input of channel TVG through the following circuit and inverter circuit of the next stage, as it shown in figure 6.The execution process of digital gain is shown in figure 7. Adjusted gain control voltage TVG_ 1-1 serves as the input signal for the gain control chip VCA810.The variation range of TVG_1-1 is -2V to 0V.When TVG_1-1 is equal to -1V, the amplification factor of VCA810 on the signal is 1.More specific details can be referred to the instruction manual for chip VCA810.
The FPGA outputs a total of 6 channels of TVG, and maps three addresses on the DSP EMIF interface, with offsets as follows: `define gain_set_cs1 12'h000 `define gain_set_cs2 12'h002 `define gain_set_cs3 12'h004 Each address corresponds to two bytes, and each byte corresponds to one TVG channel, totaling six channels.For example, the low byte of `define gain_set_cs1 12'h000 corresponds to the control amount of TVG1 digits, the high byte corresponds to the control amount of TVG2 digits, and the remaining addresses are calculated accordingly.

DSP Program Design
This solution uses TI's TMS320C6678 multi-core DSP for the engineering implementation of the direction finding and positioning algorithm.The DSP data processing process of the split array frequency domain beamforming algorithm is shown in figure 8.The number of calculation points for each channel is 2048, and frequency domain beamforming is used to achieve direction finding.
The DSP array signal processing implementation adopts split array frequency domain beamforming algorithm, and the DSP embedded software mainly includes network communication, beamforming algorithm implementation, and sampling data reading control.
The specific array signal processing process is shown in Figure 9: One channel of signal is first subjected to bandpass filtering, followed by FFT transformation, phase compensation, and finally cross spectral direction finding for the correlated 4-element array data.

Summary
This article introduces a hardware implementation scheme for acoustic direction finding algorithm based on FPGA+DSP architecture, which can achieve programmable amplification, filtering, and acquisition of multi-channel acoustic analog signals, and can be stored and beamforming processed in real-time.At the same time, it can communicate with the upper computer to achieve upper command, data, and parameter settings.This plan has been verified through engineering practice, with high data processing efficiency and reliable results, and has certain reference significance for the development of other similar equipment.

Figure 1 . 2 ..
Figure 1.Two receiving hydrophones Figure 2. Array splitting beam orientation Figure 2 shows the split beam orientation of a linear array, with left subarray

(
c represents the speed of sound, and d represents the interval between adjacent primitives).
So, the phase difference between the left and right beams of the linear array is calculating  , you can calculate .If the length of the linear array is example, the beamwidth of a 3dB point in a linear array 0directional accuracy of a linear array is approximately 1 80 times the main lobe width of the beam, and of course, it is also related to the input signal-to-noise ratio.The principle block diagram of split array frequency domain beamforming direction finding is shown in figure3.

Figure 3 .
Figure 3. Schematic diagram of direction finding in frequency domain beam forming of split array

Figure 4 .
Figure 4. Overall block diagram of system circuit designThe power management board provides power for the electronic devices of the system, achieving the function of power conversion.The signal conditioning module mainly consists of pre-amplification, filtering, automatic gain control, and other parts to achieve the pre-conditioning of analog signals[9].These two parts of the circuit are using mature circuit design, and will not be repeated here.The acquisition control board is the core module of the hardware system, which receives a total of 17 signals from two 8-element linear arrays and a single hydrophone, achieving functions such as acquisition and beamforming, target orientation calculation, sending and receiving communication instructions, and real-time uploading of calculated directional information.The core part of the acquisition control board in this scheme adopts an embedded structure of DSP and FPGA, with 2 DSPs as data processors and 1 FPGA as logic controller[10].The functional block diagram is shown in figure5:

Figure 5 .
Figure 5. Functional block diagram of acquisition control circuit

FilteringFFTFigure 8 .
Figure 8. Data processing flow chart Each channel data input includes 2048 points, 16 sets of data, a sampling frequency of 192kHz, a signal pulse width of 10ms, and a total of 2048 FFT points.The FFT window length is twice the pulse width length, with a step of half a pulse width length.Each group of split beams consists of 4 elements, with an array opening angle of 60 ° to 60 °.The system has 16 pre-formed beams, and the pre-formed angles are selected by the upper computer software.The array signal processing flow is shown in figure 9.