The parasitic capacitance considerations of metal interconnects in sub 10 nm era

With the development of the integrated circuit industry and semiconductor technology, we have entered the sub-10 nanometers era, which means the distance between adjacent components in a device is less than 10 nm. This is a situation where the parasitic capacitance of metal interconnects must be considered. Parasitic capacitance can act as a significant influence in different ways on disparate devices. Fin field-effect transistors and microelectromechanical systems are typical devices and deserve further detailed explanation on their parasitic capacitance. There are many ways to reduce parasitic capacitance and its attendant effects, including using materials with low dielectric constants and optimizing the structure of the layout. Some others are newly brought out in recent years due to advanced industrial technology and new materials, including carbon nanotubes, oxide-free spacer layers, and tunneling hybrid technology. All these methods are of great significance and practicability to producing and applying semiconductor devices and structures. Knowing more about this expertise about parasitic capacitance can help us better understand its nature and specialties.


How does parasitic capacitance form
The parasitic capacitance in metal interconnects refers to the capacitance formed in chip layout and connection, owing to the coupling of the electric field between metal wires and interactions between transistors and some other components.The separation and accumulation of charges between wire segments, ground planes, and power supply planes often cause parasitic capacitance.The amount on one of them affects the charge distribution on the other, which forms the capacitance between the wires.
In an integrated circuit (IC), parasitic capacitance may negatively affect the circuit's performance.The capacitance may also cause problems such as reflection and delay when the signal is transmitted through the wire.Therefore, it is necessary to consider parasitic capacitors when designing ICs and take measures to reduce their influence on circuits.
When considering the parasitic capacitance of metal interconnects in the sub-10 nanometre era, it becomes a much more severe problem.The main reason is that the width and separation distance of the metal interconnects diminish sharply as the size of the semiconductor devices becomes smaller.This will contribute to a much more apparent separation and aggregation of charges among adjacent wires, which then form a larger parasitic capacitance.
Knowing about the forming process is vital to further understanding parasitic capacitance.

Commonalities and differences in different devices and materials
Parasitic capacitors in other materials and devices have some commonalities and differences.The commonality is that regardless of material and device type, the shorter the distance between two conductors, the greater the parasitic capacitance.As a result, the parasitic capacitance between the wires in an IC tends to be significant.Another commonality is that parasitic capacitance becomes increasingly essential to the circuit as the frequency increases.In high-frequency circuits, parasitic capacitors can cause signal reflection, reduce bandwidth, increase noise, and other problems.It is necessary to pay special attention to parasitic capacitance and minimize its influence on circuit performance when designing high-frequency circuits.
Some differences in parasitic capacitance also exist.In a transistor, for example, the parasitic capacitance between the base and the collector tends to be much smaller than between the emitter and the ground.The reason is that the transistor has a positive-negative junction between the emitter and the base, which can reduce the parasitic capacitance.Another situation is that using different dielectric materials in capacitors can significantly change the parasitic capacitance size.For example, the parasitic capacitance in an air capacitor is small, while that in a capacitor made with a high dielectric constant material, such as aluminum electrolytes or titanium dioxide, will be more significant.
There are some differences and commonalities among different materials and devices.Understanding these differences and commonalities can help designers better reduce the impact of parasitic capacitance on circuit performance.

Influence of parasitic capacitance on tiny size devices
Parasitic capacitance is a common problem in ICs, affecting their performance and reliability.Here are some possible effects: They are reducing circuit speed.In high-speed logic and analog circuits, parasitic capacitors may reduce circuit speed by causing signal transmission delays and slower rise and fall times.
We are increasing power consumption.Due to parasitic capacitors, the circuit requires more energy to overcome the charge buildup and voltage spikes created when the current is reversed.
They are impacting signal integrity.Parasitic capacitors can cause problems like signal reflection, ring oscillation, and interference.These problems may make the circuit lose accuracy and stability and even lead to system failure.
Parasitic capacitance is an important factor affecting the performance and reliability of circuits.Some standard technology and devices are being used in the large-scale IC industry.The parasitic capacitance influences all of them but with some differences.
IC devices with a size below 10 nm are one of the most advanced chip technologies.Some common ones include fin field-effect transistors (finFET), microelectromechanical system (MEMS) devices, three-dimensional stacked memory, heterogeneous integrated device, photoelectric IC, quantum computing devices, etc.Here we choose finFET and MEMS devices as two typical examples and further explain ways of parasitic capacitance to influence them.

FinFET transistor
The finFET is a three-dimensional metal oxide semiconductor field-effect transistor (MOSFET) that enables lower power consumption and better performance.It uses a thin rod (called a "fin") perpendicular to the substrate as the gate and controls the current between the source and drain by controlling the gate.
In finFET, most parasitic capacitors are generated due to their unique three-dimensional structure.The three-dimensional structure of the source, gate, and drain forms a parasitic capacitance between each other.These capacitors will affect the performance of the finFET, such as switching speed and noise, as well as the geometrical shape of the finFET.For example, the grid capacitance can have a significant influence on the inherent delay of the device.The S/D parasitic capacitance, which may be due to the top of the S/D region to the top of the gate or the top of the S/D region to the gate side wall, has a significant effect on the performance of devices, as well as the overall parasitic capacitance [1,2].It depends on the geometry of the finFET as well as the material.Additionally, there are other parasitic capacitors, such as ground capacitance, drain capacitance, and grid capacitance.These can affect finFET's performance in terms of sensitivity and interference.Parasitic capacitance also affects power consumption and reliability.The movement of electrons in three-dimensional space leads to a larger contact area and channel length, which will increase the occurrence of leakage current and tunnel current, thus increasing power consumption and reducing reliability.
However, parasitic capacitance is not always totally detrimental when considering finFETs.Estimating parasitic capacitance has many uses, like providing a way to compare the efficiency of different layouts.It is also helpful for accurately estimating gate capacitance and, to some extent, reflects the effective channel length of the transistors [3,4].Since finFET is an alternative and silicon-on-insulator architecture differs from planar MOSFET in terms of layout and layer stacking, many of these capacitors likely have different values in finFET.Knowing which layouts can be optimized will contribute to developing future finFET parasitic capacitance models appropriately.
A low dielectric constant material can be used to reduce the detrimental effects caused by parasitic capacitance.Also, a structure of silicon oxide combined with high-temperature silicon nitride oxide can be used to improve the reliability of finFET.

MEMS device
MEMS devices combine mechanical, electronic, and computer technologies to achieve sensors, actuators, and controllers of small size, high sensitivity, and precision.
In MEMS, parasitic capacitance occurs naturally due to the device's physical structure and material properties.The capacitance can affect the performance of MEMS devices, such as reducing the signal-to-noise ratio.This is because parasitic capacitors introduce additional noise to the circuit and may affect the device's sensitivity.
Other effects may happen.Changing the frequency response is one of that.This can cause the device to gain higher or lower gain at specific frequencies, affecting its performance.Another influence is to affect the stability of the device.They may cause the machine to drift or lead to other erratic behaviors if associated with sensors.Electro-mechanical model of the microelectromechanical system with parasitic capacitance [3,4] To minimize the effect of parasitic capacitance, MEMS designers often consider optimizing the device's physical structure and material characteristics.They may also take other steps to isolate parasitic capacitors, such as shielding or narrowing electrode spacing.For example, in a particular situation as the MEMS gyroscope with push-pull configuration, the parasitic capacitance exists between the driver port drive positive (DP) and the sensing port drive sense positive (DSP), as well as the drive negative (DN) port and drive sense negative (DSN) port [5,6].There is also a smaller additional parasitic capacitance between DP and DSN port.Experiments and research have proved that the parasitic current caused by differential drive and differential sensing magnifies at the differential amplifier.The output of the amplifier will be the sum of the parasitic capacitance of the induction port (DSP and DSN), which is analyzed theoretically and experimentally.Applying the same AC canceled out on a second differential amplifier, provided that the external signal and the parasitic feed communication signal have the same phase and amplitude.This method is easy to conduct, diminishing the parasitic feed-through capacitance entirely.

Ways to treat parasitic capacitance and reduce it
Since the influences made by parasitic capacitance in metal interconnect situations are always undesirable, designers have come up with a variety of valuable ways to reduce parasitic capacitance in the sub-10 nanometre era.Some of the methods have been proven practical and widely used in the IC industry.At the same time, some new ways with higher efficiency have been brought out thanks to the progress in the semiconductor industry and the introduction of new materials.

Common and practical methods
3.1.1.Using materials with a low dielectric constant.Using soft dielectric constant material is an effective method to reduce the parasitic capacitance in ICs.On conventional silicon oxide (SiO2) media, the dielectric blocks the electric field between metal wires, which creates a parasitic capacitance.Materials with a lower permittivity relative to air can better isolate the electric field and reduce the size of parasitic capacitance.Some common low-permittivity materials include silicon nitride (Si3N4) and low-permittivity polymers such as B-staged benzocyclobutene (BCB) and fluoride.
Low dielectric constant materials are often used in semiconductor devices' insulation and dielectric layer to reduce parasitic capacitance.For example, in transistors and MOSFETs, using low-permittivity materials to manufacture gate media can reduce the capacitance between gate and drain (Cgs) and the capacitance between gate and source (Cgd).Similarly, using low dielectric constant materials to fabricate interconnect layers and substrate insulation can also reduce the parasitic capacitance between different metal layers.
Although parasitic capacitance can be effectively reduced by using low-permittivity materials, some low-permittivity materials are more expensive to manufacture and have high sensitivity to temperature and humidity.Therefore, it is crucial to balance these factors in practical applications and select appropriate materials with low dielectric constant to meet specific design requirements.

3.1.2.
Optimize the structure of the layout.Optimizing layout structure is crucial to reducing parasitic capacitance in IC design.Here are some common ways to maximize layout structure: We are reducing the wire length.In an IC, shortening the size of wires is an effective way to reduce parasitic capacitance.Using the shortest cables to connect devices and components can significantly reduce parasitic capacitance.
They are adding ground wires.Ground wires eliminate interference signals in circuits and ensure signal integrity.They also help reduce parasitic capacitance.Adding ground wires can inhibit the electric field diffusion, and the coupling effect between metal wires can be reduced.
They avoid right and sharp angles.Right angles and sharp angles in ICs can create a focusing effect on electric fields, leading to increased parasitic capacitance.Therefore, they should be avoided as far as possible in layout design, and smooth curves and arcs should be used instead.
I am splitting winding.In high-frequency circuits, splitting winding can reduce the coupling effect between lines and parasitic capacitance.By splitting long interconnectors into multiple short segments, current can be transmitted more evenly, reducing crossover and coupling effects between lines.
Optimizing the layout structure is an effective method to reduce parasitic capacitance.Designers must choose different ways according to the requirements to achieve the best performance and reliability.

Increase layers of interface.
Increasing the boundary layer is another effective method.The boundary layer is a layer of conductive or semiconductor material inserted between two dielectric materials to change the dielectric constant and charge distribution and reduce the numerical value of the parasitic capacitance.There are some common ways to add a boundary layer.
First, we can add interface layers between interconnect layers.In multilayer metal interconnect structures, interface layers can be added between different interconnect layers, such as silicon nitride (Si3N4) or alumina (Al2O3).These boundary layers can reduce the parasitic capacitance between different metal layers and improve the speed and reliability of the circuit.
Then, we can add a boundary layer to a transistor.In a transistor such as MOSFET, the capacitance between the gate and the drain (Cgs) and the capacitance between the gate and the source (Cgd) can be reduced by taking a high dielectric constant gate dielectric and adding a low dielectric stable boundary layer below it.
It's also helpful to add a boundary layer to a capacitor.A capacitor can be added to reduce the parasitic capacitance between the electrodes.For example, adding a copper boundary layer in a metal-silicon nitride titanium dioxide capacitor reduces the parasitic capacitance between the metal electrode and the silicon nitride.
While adding a boundary layer can effectively reduce parasitic capacitance, it may introduce other problems, such as increasing contact resistance in the transistor.Therefore, careful analysis and optimization are required to ensure no additional issues are raised and to achieve the desired results.

Optimize the parameters of technology.
Optimizing process parameters is a practical and effective method in IC manufacturing.The following are ways to optimize process parameters: I am adjusting the electron beam exposure dose.Electron beam exposure dose is one of the critical factors affecting the precision of responsible definition details in IC manufacturing.By changing the exposure dose, the pattern's size, shape, and edge smoothness can be controlled, thereby reducing the distance and area between the wires and the coupling capacitance.
We are optimizing the oxide layer thickness.The oxide layer is the medium that protects the IC component and separates different metal layers.By optimizing the thickness of the oxide layer, the dielectric constant of the dielectric layer can be reduced, thus reducing the interconnection capacitance between different metal layers.
It controls the size of the contact hole.The size of the contact hole directly affects the parasitic capacitance in IC.By maintaining its size, we can reduce the distance and area between the wire and the contact hole and the coupling capacitance.
I am using unique manufacturing processes.For example, local silicon nitride passivation technology or cathode-luminescence manufacturing of components such as transistors can reduce the parasitic capacitance between the electrode and the substrate.
However, other factors, such as cost and manufacturing difficulty, must be considered when optimizing process parameters.Designers need to make trade-offs and optimizations based on actual requirements.

Carbon nanotube layouts.
As a new material, carbon nanotubes (CNTS) have broad application prospects in microelectronics.CNTS is about 1 to 10nm in diameter, much thinner than ordinary metal wires.So they can accommodate more wires in the same wiring area.In addition, CNTS conduct electricity very well, with only a sixth of the electrical resistivity of copper, which means they have less resistance at the same length.Compared with traditional metal wires, CNTS can effectively reduce parasitic capacitance.The capacitance and inductance values of CNTS can be controlled by selecting different shapes or processing techniques to reduce parasitic capacitance [8][9][10].
However, the preparation and processing technology of CNTS wiring is more complex than that of traditional metal wires, which requires a higher level of technology.Designers also need to consider the manufacturing cost and feasibility.In practical applications, the contact mode and quality between CNTS and microelectronic devices also affect their performance.Therefore, when using CNTS as a wiring material, factors such as the contact mode with the device, interface structure, and contact quality need to be considered.

Oxide-free spacer layer.
An oxide spacer is one of the most used materials in microelectronic devices.However, the oxide has a relatively high dielectric constant which will increase parasitic capacitance.Hence, the oxide-free spacer layer is needed to reduce the parasitic capacitance in some special situations.
The main components of oxide-free spacer include silicon nitride, silicon carbide, and silicon fluoride.The dielectric constant of these materials is lower than that of oxides so that the parasitic capacitance can be reduced effectively.Moreover, the oxide-free spacer is more chemically stable and adaptable to extreme environments such as high-temperature treatment.In practice, the oxide-free spacer layer is usually a multilayer structure.Using a multilayer structure of silicon nitride and silicon fluoride to reduce parasitic capacitance can significantly improve the speed and sensitivity of MOSFETs.
Of course, there are some problems while using an oxide-free spacer.For instance, non-oxide materials are difficult to process due to their higher hardness, requiring higher preparation and processing technology.Furthermore, the low thermal conductivity of non-oxide materials may affect the heat dissipation performance of the device.

Tunneling hybrid technology.
The tunneling hybrid technology is an advanced method to reduce parasitic capacitance, which can realize the structure design of high efficiency and low power consumption in devices.The technique utilizes the quantum tunneling and composite effects between copper/soft dielectric constant materials to reduce parasitic capacitance and improve device performance.
This technique is mainly achieved by adding a copper/low dielectric constant composite layer between the metal wire and the soft dielectric stable material.Composite layers can be obtained by "sputtering" technology or other processing methods.When the device works, the mixed layer will produce a quantum tunneling effect and form an Oyom-level resistance, effectively reducing the parasitic capacitance between the wire and the material with a low dielectric constant.
This technology can not only significantly reduce the parasitic capacitance of the device but is also efficient in improving the speed of the device, reducing power consumption, improving reliability, and other aspects of the performance.Furthermore, the preparation process of this technology is relatively simple and compatible with the traditional semiconductor manufacturing process, so it has a good application prospect.
Problems with this technology also exist, such as the impact of the composite layer's growth quality, thickness, and interface structure on the device performance, as well as the heat resistance and stability of the mixed layer.Therefore, it is necessary to consider these problems comprehensively and optimize its preparation and processing technology continuously in practical application.

Conclusion
Parasitic capacitance is a side effect in all integrated circuit (IC) devices, especially in the sub-10 nm era.The generation of parasitic capacitance may be simple, but its influences can be various and grievous.
Many methods have been brought out to reduce parasitic capacitance.Though some of the advanced ones are recently put forward, all of them can contribute significantly to the IC industry since reducing the parasitic capacitance of metal interconnects is a great matter in electronics production.
It's of great help to study the influences and ways of generating parasitic capacitance in specific devices, which can help designers know it better and learn to solve this problem.Learning some existing methods of reducing parasitic capacitance can help us get an in-depth understanding of its peculiarities and make it easier to develop more advanced and efficient processes in future studies.

Figure 3 .
Figure 3.Transverse electric and magnetic field image of as-synthesized carbon nanotubes[7]