Quasi-3D Numerical Thermal Modelling of Electronic Systems in Package

The technology of three-dimensional (3D) packaging currently provides an increase in the efficiency of various electronic systems, bringing the volume of the package and heat dissipation into proper correlation. For many types of modern 3D packages the electro-thermal properties were not yet investigated. So the thermal modelling of 3D system in package (SiP) constructions became obliged for package designers. The commercial universal fully-3D simulators are not effective for practical engineers because of the complexity in using. The problem-oriented method called “Quasi-3D”was proposed and software tool Quasi-3D-Overheatwas developed to save the pre- and post-processing labour and CPU time. Numerical thermal modelling for different types of modern SiP structures: bridge-chip; p2 Pack; chip stack with TSV; embedded silicon fan-out was carried out and compared with measured temperatures. Simulation error was not more than 10–15%.


Introduction
With the acceleration of emerging fields such as mobile technologies, 5G, Internet of Things (IoT), Artifical Intelligence (AI), bigdata and cloud computing and others the microelectronic chip sizes are getting smaller and smaller.At another side, for automotive electronics, electrical motor drivers, power and voltage regulators and supplies and other applications the package volume of electronic components continue to be invariable while increasing the active device power.In both cases the power density is growing and it became more and more difficult to keep the balance betweenthe electrical power and heat dissipation.Recently, much attention has been put into research and development of 3D packages.But for many types of modern packages the thermal properties were not yet investigated.The complete thermal modeling is necessary.
Traditionally, the problem of heat dissipation in 3D packages was analyzed using the commercial multi-physical fully-3D simulators: ABAQUS [1], FloTHERM [2], ANSYS [3], COMSOL [4] and others.But, the fully-3D universal simulators have the restrictions well known for practical engineers: 1) it is difficult to prepare the pre-and post-processing data; 2)it is difficult to generate the adequate geometrical model of 3D package construction; 3) much CPU time is required for numerical solving of fully-3D problem.
Previously the correct simplification of the problem for the BGA packages [6], which shortenes the CPU time was proposed.
In this paper we extend this approach to electronic printed circuit board (PCB) systems which represent a large segment of the electronic component market.

Formulation of PCB Package Thermal Model
The temperature distribution T(x,y,z) in the global SiP/PCB construction is described by the 3D heat equation: ( , , ), where k is the coefficient of thermal conductivity and Q is the power density.The SiP structure in Figure 1 consists of N numbers of thinned layers (or stratums) of different materials.The every ξ-layer thickness z ξ is much less than the layer horizontal sizes: z ξ <<L Xξ ,L Yξ .So the temperature distribution in z-direction can be considered as linear and the derivative ∂T/∂z can be replaced by the difference: where ξ is the layer number.
The 3D equation ( 1) is transformed into a system of 2D equations describing the temperature distribution: • on the top surface of the package T 1 (x,y): where the term α(T AMB -T 1 ) takes into account convection on the package top surface, α is a convection coefficient; • on the surfaces of the inner layers of the package: the heat transfer between the layers is taken into account by the terms: k z(ξ-1) (T ξ-1 +T ξ )/Z ξ-1 and k zξ (T ξ+1 +T ξ )/Z ξ , where N is the quantity of package layers; • on the bottom surface of the package: 1 ( , ) .
where T AMB is the ambient temperature; • on the side surfaces of the package the appropriate boundary conditions for Equations ( 3) and ( 4) are established.
The software tool Quasi-3D-Overheat has been developed for numerical solution of eqn.( 3) and ( 4) describing the 3D constructions of SiP/PCB packages.The maximum number of structural layers is 20.The difference grid is generated automatically and its maximum size is 700×700 nodes.

The Results of Thermal Modelling of 3D Package Structures
Four popular SiP constructions were chosen as devices under test (DUT).The validation of the Q3D package models was carried out.The simulated results obtained using Quasi-3D-Overheat and standard fully-3D FEM simulators were compared.The acceptable coincidence was achieved.

Bridge-chip SiP technology
The first considered DUT is the SiP construction Figure 1 with three embedded dies: processor, FPGA logic and DRAM memory.Processor die size is 10×10 mm 2 and power is 74.49W; FPGA die size is 10×10 mm 2 and power is 44.8 W; DRAM die size is 10×20 mm 2 and power is 5.65 W [5].
The temperature distribution in the dies of SiP Figure 1 were simulated using COMSOL software tool, these results are presented in Figure 2.This temperature distribution for the same object was simulated using Quasi-3D-Overheat too, these results are presented in Figure 3.The CPU time was about 5 min for the 3.3GHz processor; difference grid in horizontal plane was 490×570.
Comparison of the simulation results presented in Figure 2 and Figure 3 shows a good agreement: difference for T max is not more, than 3 °C.

p 2 Pack technology
The SiP module produced by the p 2 Pack technology [7], was selected as a second DUT for thermal characterization.
The p 2 Pack technology is an embedding technology for power transistors such as IGBTs and MOSFETs.As the thickness of p 2 Pack is 1.2-1.7 mm, it is possible to embed this package into one single PCB and avoid additional connectors between logic control and power transistors.
The typical p 2 Pack structure is shown in Figure 4.The temperature map for this module simulated using the Quasi-3D-Overheat software tool is presented in Figure 6 (the CPU time was about 3 min for the 3.3GHz processor; difference grid in horizontal plane was 400×400).It coincides with the result achieved using software tool ABAQUS6.7 (see Figure 5): difference for Tmax is not more, than 3 °C.

3D chip stacking using TSV
The third considered DUT is the 3DIC construction Figure 7 with two embedded dies: Flip-Chip system-on-chip (FC SoC) and WideIO2, which are connected using TSV [8].These devices are used in mobile computing systems.In the paper [8] are presented the results of thermal modelling of this device: the temperature of the active surface of FC SoC is 97.8°C for power equal 4 W, the temperature of the active surface of Wide IO2 is 97.7°C for power 0.6 W. Thermal conductivity θ jA =15.5 °C/W.Also this device was simulated using the Quasi-3D-Overheat software tool (see Figure 8).It can be seen from the calculation results that the maximum temperature of FC SoC is 96.6°C, and the maximum temperature of Wide IO2 is 96.5°C.Thermal conductivity θ jA =15.1 °C/W.In this example the chip power was assumed to be 3 W, and the package size was fixed as 6 mm × 6 mm × 0.45 mm with an embedded die 100 μm thick and horizontal sizes 1×1, 2×2, 3×3, 4×4, 5×5 mm 2 .The simulation results of thermal resistances for the package with different die sizes under natural convection are shown in Figure 10 (curve 1).For the same object thermal resistances were simulated using Quasi-3D-Overheat tool.The results are presented in Figure 10 (curve 2).The CPU time was about 4 min for the 3.3GHz processor; difference grid in horizontal plane was 400×400.Comparison of curves 1 and 2 shows the good agreement between results from paper [9] and results calculated using Quasi-3D-Overheat tool.In Figure 11 the temperature distribution on the die is shown.

Conclusions
The model reduction technique for speeding up for thermal simulation of SiPs/PCDs was proposed.The specific features of SiP constructions were taken into account: 1) vertically stacked architecture; 2) each functional block is placed on a thinned layer of different materials; 3) short vertical z-axis interconnection through the layers.The software tool Quasi-3D-Overheat was developed for practical application.In comparison with the commercial universal fully-3D simulators the following advantages in practical design were realized: the data pre-and postprocessing and the procedure of 3D geometrical package model generation were simplified; processor time and RAM volume were greatly reduced (in 5 -10 times), saving the accuracy.Validation of the Q3D models for modern 3D IC packages: embedded bridge-chip; p 2 Pack; chipstack with TSV and embedded silicon fan-out, was carried out.Simulation results were compared with the measured temperatures for the real packages.The simulation error was not more 10 -15%.

Figure 1 .
Figure 1.a) Typical electronic system in package using bridge-chip technology [5].b) schematic representation of SiP construction in Quasi-3D model: 1top surface of TIM2; 2top surface of heat spreader; 3top surface of TIM1; 4top surfaces of dies; 5bottom surfaces of dies; 6top surface of bumps; 7top surface of substrate; 8top surface of interposer; 9bottom surface of interposer; 10bottom surface of substrate.

Figure 2 .
Figure 2. Top view of thermal profiles of embedded bridge chip simulated by COMSOL, Tmax=104.92°C[5]

Figure 4 .Figure 5
Figure 4. Exploded view of a Smart p 2 Pack [7].1the copper base plate; 2the lead frame with the active electronic components; 3the plate with the thermally conductive glass fabric and the copper layers; 4the logic control board into which the p 2 Pack is embedded The 3D temperature distribution in p 2 Pack structure simulated using software tool ABAQUS6.7 is shown in Figure 5 [7].It has taken about 40 min.CPU time for the 3.3GHz processor.The temperature map for this module simulated using the Quasi-3D-Overheat software tool is presented in Figure6(the CPU time was about 3 min for the 3.3GHz processor; difference grid in horizontal plane was 400×400).It coincides with the result achieved using software tool ABAQUS6.7 (see Figure5): difference for Tmax is not more, than 3 °C.

Figure 5 . 7 ]Figure 6 .
Figure 5. Temperature distribution in a p 2 Pack single cell assembled on a heat sink [7]