The Analytical Models of Fringe Parasitic Capacitance of FinFET - A Review

When planar MOSFET encounters its own scaling limit, FinFET was introduced and successfully replaced the traditional MOSFET. FinFET owns its privilege over the planar MOSFET for its high tolerance to short channel effect. However, due to FinFET’s 3D structure, high parasitic capacitance compared to planar MOSFET significantly degrades the transistor speed because of RC delay. This paper provides a review on the fringe capacitance of FinFET device based on the accuracy to experimental data of the two-dimensional and three-dimensional analytical models. Those models take the external and internal parasitic capacitance component into account. The three-dimensional model outperforms the two-dimensional model in levels of precision but requires more parameters and time to establish.


Introduction
MOS transistors have evolved over the past 60 years to demonstrate that they are still dominating the semiconductor industry.Even though this development has changed the physical structure from planar to 3D, the semiconductor device physics has stayed fundamentally the same.Further down scaling of the device results significant short channel effect, which could be handled by introducing new geometrical structure of the gate as to increase the gate to channel control.FinFET is proven successful during the last decade of industrial usage.However, with the shrinking of device sizes, parasitic capacitance becomes a significant factor to restrict the operation speed of CMOS devices.The 3D structure of FinFET not only causes a new distribution of electric field in the gate to channel region and improves the IV curve, but also it complicates the overall parasitic capacitance.Moreover, the fringe capacitance is gradually becoming a prevailing factor of total capacitance [1].Due to the proximity of the source/drain region to the gate, parasitic capacitance of FinFET rather increases compared to planar MOSFET, as shown in figure 1, as a result of worsening the logic delay.Furthermore, this situation exacerbates according to the RC delay when the number of fan-out (FO) increases where it increases the load capacitance by a great amount.Fringe capacitance is caused by two non-parallel electrode plate as separated by an insulator.The orthogonal surfaces of the gate and source/drain region in conventional MOSFET gives a fairly simple mapping model of fringe capacitance [3].The equation mapping of planar MOSFET device can be characterized when there is only non-parallel plates with offset and orthogonal plates being considered, with which strong agreement of analytical model and experiment data is revealed.However, when it comes to the analytical model of FinFET, the estimation becomes difficult.
Thanks to the exact symmetric structure of MOSFET, it is enough to only model one side of the device.The total fringe capacitance of FinFET is combined of external and internal components.The external fringe capacitance can be generalized as gate to fin capacitance ‫ܥ(‬ ) and source/drain electrode to fin capacitance ‫ܥ(‬ ).The internal fringe ‫ܥ(‬ ) capacitance is in response to the internal wall of the gate to the channel.As for the two-dimensional model, rather simple approximation is given directly, assuming the consistency of the electric potential between the silicon substrate and the bottom area of the gate electrode [4].The two-dimensional model is described as a conformal mapping, which presumes that the angle between the intersection would not change, as a trade-off against the level of precision and the effort to parameterized calculation.This review not only covers the conformal mapping method of fringe capacitance model, but also includes the detailed description of geometry-based analytical model.Further comparison and discussion is concluded in the last section.

Two-dimensional Analytical Model
Since the FinFET structure is non-planar compared to the traditional MOSFET, two-dimensional model divides the actual 3D structure into several 2D parts.The difficulty of modeling fringe capacitance is that perpendicular plates should be considered as a main part.Contrast to the parallel plate capacitance, the perpendicular plates refer to the electric field lines in elliptical way rather linear.In the 2D model provided, however, it adopts the basic estimation of the ellipse to maintain the mathematical simplicity.The 2D model is actually rather 1.5D because it is not modeling the structure under a complete xy-plane.As to keep the naming consistent, it calls the conformal mapping as 2D model and a structural mapping as 3D model [5][6][7].
The total fringe capacitance can be summarized as the combination of three main parts: fin to gate capacitance, source/drain contact to gate capacitance, and the inner fringe capacitance.Parameters of FinFET structure is illustrated below in figure 2. It contains the channel length ‫ܮ(‬ ), fin extension length ‫ܮ(‬ ௫௧ ), fin height ‫ܪ(‬ ), fin width (ܹ ), poly thickness (ܶ ௬ ), oxide thickness (ܶ ௫ ), source/drain contact width (ܹ ), and fin spacing length (ܵ ).

Typical Capacitance Structure in 2D
As mentioned above, two-dimensional model is made to keep the mathematics simple while remaining the accuracy of estimation as high as possible.In order to decompose the complex geometry of FinFET, simple structure is identified as helping to calculate the parasitic capacitance.Four basic types of capacitance component mapping are shown in figure 3. Detailed description of mathematical calculation is given in the paper presented by Salas et al. [5] and all capacitance component could be concluded as follows: where the ε is the relative dielectric permittivity of the material and in (1) -( 3) the L corresponds to the actual length of the conducting plane, compared to the l in (4) which is in response to the width of the plane orthogonal to the figure.
In the calculation of the capacitance, it can be separated of infinite number of small capacitance in parallel and in the end they would be summed up.The equation for the tiny part of capacitance presents as follows: where ∆A is the area of the parallel capacitor component and d represents the electric field line length [7].

Fin to Gate Capacitance Modeling
Figure 4 illustrate the two components of fin to gate capacitance.‫ܥ‬ ଵ represents the top of the gate electrode to the fin extension and ‫ܥ‬ ଶ represents the side wall of the gate electrode to the fin extension.‫ܥ‬ ଵ can be generalized using the above capacitance model (c), and it is modeled by Rodriguez et al. [1] as: where FT1 -FT3, ܽ ଵ ,ܽ ଶ are fitting parameters in order to smooth the function, which is 0.44, 0.64, -1.07, 2.54, and 2.26 × 10 ି଼ respectively.‫ܥ‬ ଶ can be characterized as the orthogonal plates with equation (b).It could be sampled with the approximation of ellipse as: where x and y represents the length of major and minor axis respectively [8].
The maximum length of the major axis can be set as ‫ܮ‬ ௫ = ೣ and the maximum length of the minor axis is set to . [8] ‫ܮ‬ and ‫ܪ‬ is related to the fitting parameter combined with ܶ ௫ .After considering the ݈ as the variable of the major length, minor length becomes a function of ݈ : And electric field line length could be expressed as a function of ݈ as: Taking the integral from 0 to ‫ܮ‬ ௫ gives the capacitance per width as: The total ‫ܥ‬ ଶ could be gotten from [8]: where ‫ݎ‬ = ‫ܪ‬ ‫ܮ‬ , and CF1 is the fitting parameter, which value is 0.935 [8].

Inner Fringe Capacitance Modeling
The inner fringe capacitance is generated by the source/drain channel and the gate electrode.Due to the low carrier concentration of zero gate voltage, the source/drain channel region performs the insulator behavior, and the device is in depletion region [7].It is said that the inner fringe capacitance would like to diminish close to zero with the increase of the gate voltage, where it gradually forms the inversion or accumulation region.Thus, the inner fringe capacitance is believed to be bias based considering that if the fin height ‫ܪ(‬ ) is smaller than the source/drain recess depth ‫ܦ(‬ ), only capacitance created by vertical source/drain region to the active channel is accounted for [7].Also considering the capacitance model (b) and (d), the inner fringe capacitance can be found as: where ݃ ଵ -݃ ଷ are fitting parameters, which is 0.35, 0.2 − 280H ୧୬ .ସହ, and 0.2 − 280(0.5W୧୬ ) .ସହ respectively; ߝ ௦ is the dielectric constant for the silicon substrate.

Three-dimensional analytical model
As mentioned in the previous session, the basic conformal mapping technique of the parasitic capacitance fails to present the highest level of estimation accuracy.Keeping the ellipse as a constant shape is not revealing the actual situation.Structure in [3] provides another solution to the ellipse electrical line to model the capacitance between the perpendicular plates, which is the most important component when analyzing the fringe capacitance.

Basic Capacitance Modeling
The basic capacitance modeling for the 3D structural mapping is different from the 2D mapping.In this method, it transforms the basic xy-coordinate into the elliptical coordinate, as shown in figure 6.The transformation is given as: where F = arcos.After fundamental transformation equation is provided, calculation of the fringe capacitance induced by the conductors can be described as parallel plates capacitance in the elliptical system [3].If ‫ݔ‬ ଵ ≠ ‫ݔ‬ ଶ holds true, the capacitance equation per unit width could be given as: It is said that based on the conformal mapping technique, the ellipse is meant to be confocal.In order to estimate the capacitance created by the gray area in figure 6, it adapts the 2D method where the electrical field line is non-linear and non-elliptical.The modified equation of estimation the capacitance per unit width of the gray area is given by: where W is the width of the certain device.
And the total capacitance in this model of a width W is given by:

Fin to Gate Capacitance Modeling
In this fin to gate capacitance model (figure 7), it further sub-divides the capacitance into four parts in total: ‫ܥ‬ ௧ , ‫ܥ‬ , ‫ܥ‬ ௦ௗ , and ‫ܥ‬ ௧௧ , where each part correlates to different structure.For modeling ‫ܥ‬ ௧ , it represents the capacitance from the top of the gate electrode to the top of the fin extension.It could be modeled by giving the variable as: ‫ݔ(‬ ଵ , ‫ݔ‬ ଶ , ‫ݕ‬ ଵ , ‫ݕ‬ ଶ ) = (0, ܶ ௦ , ܶ ௫ , ‫ܪ‬ ), where ‫ܪ‬ stands for gate height and ‫ܪ‬ = ܶ ௫ + ܶ ௬ + ‫ܪ‬ .And the equation given in section 3.1 becomes: For modeling ‫ܥ‬ ௦ௗ , it is measured of the sides of the gate electrode to the side of the fin extension.
The variables are given as: ).So that the equation becomes: For modeling ‫ܥ‬ , [3] uses pythagoras' theorem to determine the minimum and maximum effective length.So the corresponding variables of the system become ‫ݔ(‬ ଵ , ‫ݔ‬ ଶ , ‫ݕ‬ ଵ , ‫ݕ‬ ଶ ) = (0, ‫ܪ‬ ௫ (݅), ‫ܪ‬ (݅), ‫ܪ‬ ௫ (݅)), which leads the capacitance equation to be: The final part of the fin to gate capacitance would be ‫ܥ‬ ௧௧ , which relates to the side of the fin to corner bottom of the gate electrode, close to the substrate (box).The ‫ܥ‬ ௧௧ would be modeled ‫ݔ(‬ ଵ , ‫ݔ‬ ଶ , ‫ݕ‬ ଵ , ‫ݕ‬ ଶ ) = (0, ܶ ௦ , ܶ ௫ , ܶ ௦ ) as presented [3]: Therefore, the overall fin to gate capacitance would be calculated by:

Contact to Gate Capacitance Modeling
In this model, the source/drain contact to gate electrode models from the top of the gate to the whole top area of the source/drain region.The variable is ‫ݔ(‬ ଵ , ‫ݔ‬ ଶ , ‫ݕ‬ ଵ , ‫ݕ‬ ଶ ) = (0, ଶ , ܶ ௦ , ‫ܮ‬ ) so that the evaluation becomes: where ‫ܮ‬ is the length of the source/drain region and ‫ܮ‬ = ܹ + ‫ܮ‬ ௫௧ .

Inner Fringe Capacitance Modeling
For the inner fringe capacitance, it is closely related to the device geometry and material of the certain FinFET [3].For the tri-gate FinFET, [3] represents the formula for modeling the capacitance as:

Discussion
In order to determine the accuracy of the estimation, it is necessary to compare the analytical model with the extracted results and the experimental results.In planar MOSFET devices, the basic conformal mapping technique gives the error range below 3 percent.[2] As shown in figure 8, the analytical model of the fringe capacitance of planar MOSFET strongly agrees with the simulation results.However, for FinFET devices, the basic conformal mapping which assumes the elliptical electric field line to be circular.This assumption brings the huge derivation of error to the experimental results in order of 10 ିଷ [2].The level of accuracy brought by Shrivastava et al.'s work [9] in planar MOSFET was high enough, where the error ranges from -2 percent to 2 percent.However, when Bansal et al. [10] adopted the mapping technique from Shrivastava et al., the model results was off by roughly 5 × 10 ିଶ compared to the extracted value and was off by almost 10 ିଷ in level of magnitude compared to the experimental results from AC operation [2,11].The above model and comparison represent that the basic conformal mapping, especially consider the elliptical electric line as circular, is not sufficient for fringe parasitic capacitance modeling in FinFET devices.The accuracy of the fringe capacitance model depends on the precise estimation of the orthogonal plates' capacitance.Based on the work presented in reference [1,3,10,11], the estimation of the orthogonal plates capacitance was off from the experimental result by 3.2%, 2.4%, -1.3%, and 6.7%, consequently the approximation of the total fringe capacitance of ‫ܪ(‬ = 60݊݉, ܶ ௫ = 1.3݊݉, ܶ ௬ = 100݊݉, and ܵ = 100݊݉) was off by 8.0%, 3.1%, -1.1%, and 13.7% respectively.[2] In this paper, the 2D analytical model was mainly retrieved from reference [1,8] and the 3D analytical model is mainly obtained from reference [3].In the above comparison of the result, it is easy to find out that the 3D analytical model outperforms the 2D model in level of accuracy, which is suitable for designer to run simulation.However, on the mathematical complexity consideration, the 3D analytical model exceeds the 2D model and requires more parameters to acquire the result.Nevertheless, it is necessary to adopt the 3D model based on the accuracy.
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Conclusion
To conclude, a 2D model and a 3D model is reviewed in this paper.Both models discussed in this paper take the internal fringe component and external fringe component into account.Basic comparison is made by claiming that the accuracy of estimating the capacitance of perpendicular plates would influence the precision of the analytical model for fringe capacitance mapping.The 3D model outperforms the 2D model in level of precision mapping, however, with the trade-off of the mathematical simplicity and time

2. 3 .
Contact to Gate Capacitance Modeling ‫ܥ‬ ଷ , as the left component illustrated in figure 5, corresponds to the parasitic capacitance model (d), which relates to the orthogonal plates with gap in-between.It is necessary to consider the fringing part within the gap as well as the standard orthogonal plates capacitance.Linking the equation of capacitance model (b)

Figure 5 .
Figure 5. Two component of contact to gate capacitance.

Figure 8 .
Figure 8.Comparison between model (dash-line) and simulation result (dots) of total fringe capacitance of planar MOSFET considering spacer thickness [2].