High-performance LFSR circuit design based on XOR gates

The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.


Basic Introduction
Nowadays, portable technological devices like mobile phones, notebook computers and portable electronic products are an essential component of living [1].The increasing growth of global data has boosted the demand for information processing processors and integrated circuits with quick responses, tiny dimensions, low energy thresholds, and high density [2].More features have been included into a much smaller device as the process technology has been shrunk down incrementally within the nanoscale scale.The development of chips cannot be separated from the progress of integrated circuit technology.Currently, integrated circuits have also entered the Very Large Scale Integration Circuit (VLSI) stage.The exponential growth of semiconductor technology, from the 180nm process of the Pentium 4 processor to the 7nm chip process that Intel is breaking through, confirms Gordon Moore's prediction of Moore's Law.The research and development of high-performance chips provides a strong driving force and technological guarantee for the development of social technology.Chips are also entering the era of System on Chip (SoC).System level chip SoC, also known as system on chip, refers to the integration of microcontrollers, analogy circuits, digital circuits, memory circuits, and peripheral interface circuits into the system on chip.By integrating and reusing IP (Intelligent Property) cores, the design cycle of chip products is shortened, allowing chips to enter the consumer electronics market 2 faster.Nonetheless, it's likely that the designs will have additional flaws.with an increase in integration density.Large tests are used to find these flaws.Data quantities that need longer testing times are needed.Due to the high cost and affordable price of automated test equipment (ATE) testing programs, it is currently rarely considered for SOC testing [3].
The rapid development of excessive large scale integrated circuits brings convenience to the advance of society and technology, but also brings many problems to designers.Implementing more complex circuits on smaller scale silicon wafers can result in significant power consumption during circuit operation.With the development of the market, low-power design has become an inevitable demand.In addition to reducing power consumption during chip operation, a serious problem is gradually being exposed.The power consumption of the chip in test mode is much higher than that in normal operating mode, which is more evident during ultra large scale integrated circuit testing.The chip returned from chip testing is destroyed due to high power consumption, which not only affects the design cycle but also brings serious cost waste to the chip design.Testability design technology is mainly used to solve the testing problem of the chip, mainly referring to inserting some logic observation circuits inside the chip during chip design, making chip testing more efficient.By adding or improving test circuits, the difficulty of chip testing can be reduced, but this also increases the area of the internal circuit of the chip.Therefore, this technology is not suitable for tiny-scale integrated circuits, and only in very large scale integrated circuits will testability design be chosen for the circuit.The design for testability of extremely large scale integrated circuits has become a hot research topic in the field of chip testing technology.BIST is a potent DFT technology that is employed to address the challenges of enormous test data volume and extended test duration have extremely complicated VLSI circuit testing as a background.By extending the LFSR seeds, BIST creates a specific test pattern.Electronics circuits like the LFSR solve the issue of obtaining high output with minimal power usage.The practical applications of LFSR include hardware implementation and quick pseudo-random sequence generation [4].

Development process
With the advance of integrated circuit technology, the scale of integrated circuits continues to increase with the development of processes, and testability design for integrated circuits is becoming increasingly important.How to detect faults in integrated circuits with less testing cost in a short period of time has become the goal of engineers' design.Scholars at home and abroad have done a lot of research and exploration on linear feedback shift register (LFSR) circuit testing and how to reduce power consumption and improve performance in digital integrated circuit testing.To accomplish these goals, Goankar S presented an eight, sixteen and thirty-two bit LFSR for the development of pseudorandom sequences utilizing maximum length feedback polynomials [5].Although the LFSR will produce a large quantity of randomness, it will also have a low-rise time and fall time for use in communication systems [5].A novel method to produce pseudorandom numbers was presented by Shah T et al. and is known as Cipher.It is extensively used in security systems, satellite phones, and mobile phones [6].The main issue with ciphers is transmission error, which can often be caused by circuit propagation delay as well as the channel via which they are transmitted.Asymmetry dual LFSR was offered as a method for power optimization by Ying, Jen-Cheng et al.In the process of reseeding LFSR, the traditional method was improved by using two LFSR circuits to establish a relationship between adjacent bits to reduce the conversion count.Therefore, effectively not only ensuring appropriate values for irrelevant items, but also having fewer conversions overall.This design overcomes the shortcomings mentioned earlier and effectively solves the two main problems facing the industry today: the increase in test data volume and power consumption will gradually increase in testing large integrated circuits [7].To reduce the LFSR circuit's power dissipation, Fernandes R A, Rajan N. et al proposed power gating as a solution for reducing electricity leaking inside the circuit.Using a procedure called power gating, which involves switching off any circuits that aren't operating, integrated circuit designers may dissipate less energy.In this method, the fundamental part utilized to turn off the power is a sleep transistor [8].
This method is provided the Optimal solution, although on-off switching activity is one of the drawbacks of power gating.The process of switching required more time.A modified dynamic current mode logic that makes use of the LFSR circuit's power usage was created by Suresh Babu and colleagues [9].The downside of [8] is lessened by this design.Considering the high static power consumption of leakage or standby power supplies, a combination of dynamic current sources and connecting capacitors were adopted to make the circuit suitable for battery powered devices.This method effectively limits dynamic dissipation and reduces power consumption.Another low power LFSR is created by Ambalal P P, Anita Angeline A et al. using the grey encoding approach and the true signal phase clock (TSPC) [10].This literature recommended a D-FF design triggered by positive edge that would decrease leakage power and improve circuit performance.Chip decompression logic for analysis and the processing of compressed data are, for example, the foundation for test data compression, according to the literature on the multiple applications of LFSR in different circuit designs [11,14].As a result, we construct route delay faults using the LFSR decompression logic.Reversible computing is a research field that has not received special attention before and has recently begun to be novel.It is widely used in fields such as, digital signal processing, nanotechnology, and optical computing.However, his unique key generation relies on the provision of LFSR.LFSR is employed in huge array counter design, and it also performs better than a regular counter.To combat the power dissipation, a novel and efficient XOR/XNOR circuit based on Past Temporal Logic (PTL) is developed by Naseri H and others [15].

Introduction to this article
This body of literature examines the effects of various XOR gates created using diverse techniques.Cadence and ISE Design Suit 14.2 do the analysis.The general structure of this article is as follows: chapter 2 examines various XOR gate technologies, chapter 3 defines LFSR circuits based on XOR gates and introduces the results, and chapter 4 summarizes this literature.

Principle of LFSR
Typically, a shift register, and a feedback function make up the feedback shift register.The analogous feedback shift register is known as an LFSR when the feedback function is linear.XOR gates are normally employed to create linear functions.The LFSR circuit, which can produce pseudo-random number sequences, is often employed in the domains of key generation and communication.The LFSR circuit has simple structure and strong configurability.As a sequential circuit, it has high performance.It can produce fantastic random number sequences under the premise of occupying few hardware resources.Although its register state output has a repetition period, its theoretical cycle length and shift series form an exponential function relationship, which is sufficient to support the application needs.Linear feedback shift register (LFSR) refers to taking the output of linear function as the input of the shift register by using the current register state.XOR operation is a common single bit linear function.By XOR a specific register, the result of the XOR is taken as the input of the feedback shift register, and then the bits in the register chain are shifted as a whole.Due to the deterministic nature of the LFSR structure, the data stream generated by the register is entirely dependent on its structure.Due to the limited number of registers, cycles may eventually occur.If an LFSR can obtain the maximum period, it is called an m sequence.
The structure of linear feedback shift register is shown in Figure 1.ar-1 ... a0 are cascade shift registers of r level, and the status value of each register is binary number '0' or '1'.c0 ... cr are r+1 feedback coefficient, which controls the output of the register.When ci =0, it indicates that the system has no feedback, and the register output is disconnected.When ci =1, it indicates that the system has feedback, and the odd memory output participates in the operation.In the linear feedback shift register, cr =1, the last level register must be connected to participate in the operation to form effective feedback, otherwise the level r linear feedback shift odd memory will be simplified to the level r-1 or lower level linear feedback shift odd memory.c0=1 means that the feedback input has input and participates in the operation, otherwise it is called a static shift register, so c0= cr =1.The shift register is sequentially moved by the clock, and the state of the last level is output.The state of the first level is updated to the output of the module 2 encryption module, which serves as the input of the r-level cascading shift odd memory.Since the relationship between the register series r of the linear feedback shift register and the feedback coefficient ci is unique, this relationship can be described by a polynomial composed of feedback coefficients.The structure of the linear feedback shift register is shown in Figure 1.XOR addition is defined on a 2-element finite field, that is, modulo-2 addition.F(x) is called the generator polynomial or characteristic polynomial of the linear feedback shift register.For an r-level binary shift register, a maximum of 2 r different states can be taken.For linear feedback, i.e., modulo 2 additions, if all registers have initial values of 0, regardless of the shift register structure, the sum of modulo 2 addition is 0, then all registers in the entire system enter all 0 states, and the system enters an infinite loop and cannot be used.If all the remaining 2 r -1 states form an acyclic sequence, the output sequence of the shift register is the maximum periodic linear shift register sequence, and the maximum period of the sequence is N=2 r -1, and the linear feedback shift register is called m sequence.
Linear Feedback Shift Registers (LFSR) are used to create and analyse test patterns in an integrated self-test, and primitive polynomials are those that may generate the longest possible series of length (2n-1).The tap number in the case of a simple polynomial is co-prime, and the number of strikes must be even.The tap sequence n-n, n-m, n-l, n-k.... n-0, i.e., 0, n-m, n-l, n-k... n, will also yield a primal polynomial if the n-bit LFSR's tap sequence is n, m, l, k...0.This is how LFSR function, and it is often constructed using MOS Current Mode Logic (MCML), as seen in Figure 2. The first issue with MCML is the static power dissipation brought on by the constant current source employed in the circuit, which is not dependent on the operating frequency.At high working frequencies, this architecture is suitable, but the fixed current source causes the power/MHz to grow at low operating frequencies, which is unacceptable.Another issue is that different manufacturing method is needed in order to accomplish the huge load resister in the intended region and increase chip size.The final issue is the balance between rise and fall delay, which is a function of each gate load and is not as straightforward as it first appears.Further, so as to get around the MCML restriction without raising the price, an updated dynamic current mode logic circuit is used now.By combining a dynamic current source with capacitance coupling, the current source and resistance have been reconfigured in the circuit.This can effectively reduce power consumption, making the circuit more suitable for battery powered equipment.The LFSR circuit functions as a feedback scheme, with some FLIP-FLOP (FF) outputs acting as inputs to an XOR gate, the output of which is subsequently used as an input to the first FF's shift register.The feedback system involved determines how the random bit sequence is started.The following specifications are utilized in communication and error-correction circuits, respectively.The two fundamental parts needed to execute LFSR circuits are XOR gates and D-FF, which are depicted in Figures 3 and 4, separately.D-FFs are regarded as fundamental memory cells.The general drawbacks of the simple S-R NAND gate is eliminated by the addition of an inverter, which prevents the S&R inputs from having the same logic level.D-FF consideration uses clock S-R FF with an inverter in between S&R..In this, FF is set if the input value is high, otherwise it is reset.To distinguish the FF latching circuit from the data input, use the timed signal enabled.Control and controlled equipment D-FF is created by extending D-FF and adding a second S-R FF.A pass transistor, an inverter, and a pair of master and slave D-latches make up the circuit.When more transistors are switched off, the stacking effect occurs, which causes all the disclose current of transistors to accumulate.Reverse bias is used between the transistor source and gate to get around this.

Figure 3. Detect Positive Edge D-Flip Flop.
A technique to lessen leakage power in situations with low power is content with the use of these combined techniques.On stacked transistors, a dynamic current source lowers power loss while keeping efficiency.To compensate the static power loss, this design employs dynamic operation with CMLC.
The method being used is designed with a self-test pattern generator; thus, the IC can be self-tested without implementing any further specifications.
Because of this, testing and maintenance expenses are decreased overall.Efficiency is a function of LFSR minimum power dissipation.NAND gates are an option, although they require more space and power due to the higher number of transistors they use.Pass transistors were a popular choice in this work as a means of avoiding it because they reduce the number of transistors by reducing the gate.

XOR circuit design
Circuit functioning is restricted by rising power dissipation and rising area consumption as the integration level rises.As a result, designers are working to minimize the size and power consumption of systems like mobile phones, tablets, and laptops while keeping their functionality like speed and efficiency.This is because battery-powered portable devices like these are becoming more and more well-liked and in demand.To decrease the LFSR circuit's leakage power dissipation, we provide a unique XOR/XNOR circuit.This circuit is very well optimized in terms of power consumption and propagation delay thanks to its low output capacitance and low static power dissipation.The XOR/XNOR gate's full-swing construction is depicted in Figure 5.It takes six transistors to build this innovative device.This novel circuit is based on PTL logic, which has superior latency and power consumption than the traditional XOR/XNOR circuit.
In Figure 5, if the inputs A and B are both 0, the status of transistors N2, P2 and P3 is open, and transistors P3 and P2 transmit logic 0 to the XOR output.In contrast, the status of transistors in the XNOR circuit is off, and transistors P3 transmit logic to the XNOR output.In another combination, if the inputs A is 0 and B is 1, the status of transistors N2, N3 and P2 is open, the status of transistor P3 is off, and transistor N2 transmit logic 1 to the XOR output.Whereas in the XNOR design, the status of transistors N2, P2 and P3 is off, the status of transistor N3 is open, and transistor N3 transmit logic 0 to the XNOR output.In the XOR circuit the NMOS transistor [N3] is used to connect the NOT gate to design the critical route, whereas in the XNOR circuit the PMOS transistor [P3] is used to connect the NOT gate to design the critical route.Considering that NMOS transmits information faster than PMOS, XOR has lower critical path latency and better efficiency compared to XNOR gates.

LFSR circuit design
In my field of interest, the LFSR circuit is primarily made up of the minimum power XOR circuit and positive edge trigger D-FF (Figure 3).Both an internal and an exterior feedback mechanism can be used to realize the LFSR.Type 1 internal feedback mechanisms are depicted in this Figure 6. and external feedback systems are referred to as type two.The routes of the required FF in external feedback systems flow through XOR gates, however in internal feedback systems, just one XOR gate is present between the pair of FF designs, regardless of the quantity of FF employed.Due to its higher operating frequency, type one feedback system performs significantly more excellent than type two when compared to both models.
The number of nodes in the circuit is represented by the degree polynomial m.The relationship between the FFs utilized improves when the same clock signal is used in a feedback loop, which reduces power.Another method of minimizing power dissipation is to increase the number of test vectors, which results in decreased switching activity between FF.The 4-bit LFSR circuit's RTL structure is displayed in Figure 7 using the cadence tool.

Discussion of result
We constructed three, four, and five-bit LFSR circuits using ISE design suit 14.2 for XOR simulation based on PTL logic.This can effectively help us study how the different XOR design techniques affect LFSR circuits and how they can maintain good performance and low power consumption simultaneously.And based on 90 nm technology, Verilog HDL code was written for prosodic simulation.Through the above methods, we obtained useful experimental data and output waveforms, and constructed the layout of LFSR using rhythm, as illustrated in figures 8 and 9, separately.It is evident from Figure 8 that all Flip-Flops operate in pre-set mode when the reset value is at high potential.The state of the LFSR circuit is changed when the low reset signal and clock signal are applied.By reducing the number of states, or the switching activity inside the circuit, we are able to create lowpower LFSR circuits.
The behaviour of the XOR-based PTL logic is presented in the table below, along with a comparison of numerous XOR gates built using various techniques.As a consequence, XOR has the least amount of power dissipation and delay when performance is compared in terms of these two factors in Tab.1.The various design strategies utilized to cut down leakage power dissipation at various bit levels are listed in Table 2.The proposed LFSR with XOR in this work exhibited the high-power optimization, which is considerably less potent than previous LFSR design methods utilizing other XOR circuits.When compared to MCML-based LFSR, the three-bit DCML LFSR circuit is 20.14% better, but when we compare DCML-based LFSR with the suggested LFSR, the circuit's leaking power has been significantly reduced.

Conclusion
In this article, a high-behaviour XOR circuit is applied to create a high-performance LFSR shift register.
Considering that XOR circuits can significantly affect the overall power consumption and performance operation ability, they are one of the key elements of LFSR circuits.Therefore, we have studied and evaluated the impact of various XOR circuits.We started our research with basic MOS current mode logic and gradually delved into state current mode logic and XOR circuits based on transistor logic.Using the Cadence tool to assess performance aspects like as latency, power dissipation, and chip area, we found that the PTL logic based XOR circuit significantly outperforms past studies in terms of power, delay, and chip size.We develop the LFSR circuit to acquire the influence of the XOR gate using various design techniques after obtaining an improvement on the PTL-based XOR gate.Given the superior performance in the area of power dissipation compared to earlier LFSR, LFSR based on XOR gates.

Figure 1 .
Figure 1.Architecture of LFSR.Since the relationship between the register series r of the linear feedback shift register and the feedback coefficient ci is unique, this relationship can be described by a polynomial composed of feedback coefficients.The structure of the linear feedback shift register is shown in Figure1.XOR addition is defined on a 2-element finite field, that is, modulo-2 addition.F(x) is called the generator polynomial or characteristic polynomial of the linear feedback shift register.For an r-level binary shift register, a maximum of 2 r different states can be taken.For linear feedback, i.e., modulo 2 additions, if all registers have initial values of 0, regardless of the shift register structure, the sum of modulo 2 addition is 0, then all registers in the entire system enter all 0 states, and the system enters an infinite loop and cannot be used.If all the remaining 2 r -1 states form an acyclic sequence, the output sequence of the shift register is the maximum periodic linear shift register sequence, and the maximum period of the sequence is N=2 r -1, and the linear feedback shift register is called m sequence.Linear Feedback Shift Registers (LFSR) are used to create and analyse test patterns in an integrated self-test, and primitive polynomials are those that may generate the longest possible series of length (2n-1).The tap number in the case of a simple polynomial is co-prime, and the number of strikes must be even.The tap sequence n-n, n-m, n-l, n-k.... n-0, i.e., 0, n-m, n-l, n-k... n, will also yield a primal polynomial if the n-bit LFSR's tap sequence is n, m, l, k...0.This is how LFSR function, and it is often constructed using MOS Current Mode Logic (MCML), as seen in Figure2.The first issue with MCML is the static power dissipation brought on by the constant current source employed in the circuit, which is not dependent on the operating frequency.At high working frequencies, this architecture is suitable, but the fixed current source causes the power/MHz to grow at low operating frequencies, which is unacceptable.Another issue is that different manufacturing method is needed in order to accomplish the huge load resister in the intended region and increase chip size.The final issue is the balance between rise and fall delay, which is a function of each gate load and is not as straightforward as it first appears.Further, so as to get around the MCML restriction without raising the price, an updated dynamic current mode logic circuit is used now.By combining a dynamic current source with capacitance coupling, the current source and resistance have been reconfigured in the circuit.This can effectively reduce power consumption, making the circuit more suitable for battery powered equipment.The LFSR circuit functions as a feedback scheme, with some FLIP-FLOP (FF) outputs acting as inputs to an XOR gate, the output of which is subsequently used as an input to the first FF's shift register.The feedback system involved determines how the random bit sequence is started.The following specifications are utilized in communication and error-correction circuits, respectively.

Figure 4 .
Figure 4. XOR Circuit with Dynamic Current Source.

Figure 6 .
Figure 6. the suggested minimum power Internal feedback for LFSR.

Figure 8 .
Figure 8. Waveform of the minimal power LFSR circuit's output.