Design and optimization of CMOS layout structure for improved semiconductor device performance

CMOS layout structure plays a very important role in the field of semiconductor. Since the invention of CMOS technology in the 1970s, engineers have developed many other CMOS layout technologies based on it. This paper will also focus on the CMOS transistor layout structure, focusing on the analysis of three more important structures, demonstrating their impact on the performance of semiconductor devices. Before that, this paper will first introduce the basic theory of CMOS, such as the drift and diffusion of charge carriers in PN junctions, and the working principle of PMOS and NMOS, so as to facilitate us to further describe the optimization and improvement of CMOS structure. Then, the performance and characteristics of each structure are introduced in detail, and finally the comparison is made to highlight their advantages in technology and performance compared with traditional structures. In the future, CMOS structure layout will also become a hot spot, constantly creating more reasonable and advanced structures to improve semiconductor performance.


Introduction
CMOS stands for complementary metal oxide Semiconductor, which was discovered by C. T. Sha and Frank Wanlass in 1963.They showed that p-channel and n-channel metal oxide semiconductor (MOS) collective transistors are combined into logic circuits with complementary symmetric circuit configurations, and the power consumption is close to zero in standby mode [1].Then, the Radio Corporation of America (RCA) and the use of CMOS technology to produce polar power integrated circuits, used in the aerospace field, and promoted the technology into the commercial field.Later, in 1965, CMOS logic and memory for Air Force computers were designed [2].To reduce leakage, RCA switched to a more sophisticated silicon gate closed geometry CMOS technology in 1975.The integrated circuit made from this chip has a lower radiation response [3].By 1978, Toshiaki Masuhara introduced a high-speed random access memory that used a small lithography technique plus a silicon gate process, making CMOS integrated circuit performance comparable to bipolar conventional MOS integrated circuits [4].Through continuous development, COMS integrated circuit has become the driving force for the application of ultra-large integrated circuit in the field of high-tech performance calculation and engineering.CMOS integrated circuit has the outstanding characteristics of low power consumption, high reliability and high speed by using dynamic circuit, so the demand for it is increasing.Designers have solved the power density problem by miniaturizing hundreds or thousands of transistors onto a single chip with existing technology.
There are varying layout structure requirements for COMS in different fields, particularly in modern times where the structure has rapidly evolved to meet different design needs.To fulfill these requirements, various layout structures have been developed, such as the adaptive charge compensation structure designed by electrical engineers to hasten output recovery during undershoot.The CMOS layout structure was created using the 0.11um CMOS process and occupies a smaller area of about 0.078 square millimeters compared to the conventional structure.In post-placement simulation, the output recovery time was measured at 93.012 ns, representing a 57% reduction from traditional CMOS architecture.Additionally, this new structure consumes less energy, with the adaptive charge compensation structure using approximately 69.745 pW.In addition, electrical engineers have found that the COMS layout structure affects the charge sharing efficiency, which to some extent reflects the power consumption and device density of the integrated circuit device [5].In addition, there are other COMS layout structures that can be learned, such as the hash layout structure proposed not long ago, which can realize silicon-controlled rectifier (SCR), SCR has relatively high electrostatic discharge (ECD) robustness in nanoscale integrated circuits [6].Later, a new type of BJT test structure was proposed with the development.This structure was compared with the conventional structure in terms of matching performance, and it was found that the improvement of matching performance of this structure was mainly due to the reduction of the deep well effect.To improve matching characteristics, reducing the base region and minimizing the impact of DNW by decreasing the distance between the collector and emitter contact regions have been demonstrated as effective strategies in Figures 1-2, as reported in [7].Nowadays, the CMOS layout structure is more and more diverse, and the technology is more and more mature.In different fields, COMS has its unique layout structure.According to the overall structure of the total score, this paper first introduces the development history of CMOS in detail, and briefly summarizes the key technologies of CMOS at each key time.First, PN junction, two kinds of current in PN junction, diffusion current and drift current are analyzed.Based on this theory, NMOS and PMOS are described in detail, focusing on the enhanced MOS transistor.CMOS is composed of NMOS and PMOS.Then three important CMOS architectures, xhs,cym and phh, are introduced in detail.Compared with the traditional CMOS layout structure and technology in VI characteristic curve, junction capacitance and transmission speed, the different advantages of the three structures are obtained.Finally, the conclusion is made, which informs the important influence of CMOS layout structure on semiconductor performance and its important position in the semiconductor field.

Drift current and diffusion current
The paper focuses on the CMOS layout structure, CMOS full called complementary metal oxide semiconductor, its main structure is composed of NMOS and PMOS, so the paper will introduce the basic working principle of NMOS and PMOS in detail.The underlying working principle of PMOS and NMOS should be analyzed in combination with the PN junction diode, which involves the drift and diffusion of charge carriers.The two processes generate drift current and diffusion current, as shown in Figure 3. Charge carriers migrate when an electric field is applied, which results in drift current.Electrons move in the opposite direction from positive charge carriers, which move in the same direction as the electric field (holes).The final drift current is created by the net motion of the charged carriers, which produces a current flowing in the same direction as the applied electric field.The carrier mobility μ is influenced by the drift velocity, which rises with the strength of the electric field.
Charge carriers migrate from a high concentration to a low concentration to produce diffusion current.When the doping of the semiconductor is not uniform, the charge carriers will appear non-uniform distribution, which leads to the generation of concentration gradients.In this case, due to Brownian motion, the carriers will diffuse in order to reach equilibrium, and thus the diffusion current is generated, as shown in Figure 3.In this process, there is no external electric field intervention, mainly because the charge carriers of the same charge are highly concentrated in a region, and the repulsive force between particles will be generated.The repulsive force will push the charge carriers to move, forming a diffusion, leading to a change in concentration until a uniform distribution is reached.The initial particle concentration determines the direction of the diffusion current.The current moves in the direction of high concentration to low hole concentration [8].
Drift current means the current generated by the directional motion of particles under the action of external electric field, while diffusion current means the current generated by the migration of particles due to the concentration gradient.The drift current will predominate the total current density if a high electric field is provided.If there is no electric field present, the total current density will be dominated by the current produced by the carrier concentration gradient.

NOMS and PMOS
According to the formation principle of the above two kinds of current constitute the MOS transistor, and then according to the substrate of the transistor is divided into two different types of transistors.Refer to Figures 4-5 for important internal structures.The carrier density in the channel and, consequently, the resistance inside the channel, can both be changed by varying the gate voltage.P-channel improved FET is the name of this MOS FET [8].

CMOS
PMOS and NMOS are complementary and symmetrical connected, and only one of the two tubes is open at the same time during logic operation, so that there is no current at the source and drain, and the power consumption is reduced.This is shown in Figure 7.This paper will be a detailed description of COMS three more important layout structure, each layout structure will affect the performance of semiconductor devices, and each structure is based on the most basic principle of CMOS, involving the MOSFET internal process, structure; Such as the material of the gate, the thickness of the substrate and so on.As in Figure 8, BC-SOI MOSFET structure is a popular design that mitigates the floating body effect, and is fully compatible with standard MOSFETs, by preserving a thin silicon film between the field oxide and the oxide in the structure to prevent complete erosion by the field oxide.Improving the kink effect and BV_dss of the BC SOI MOSFET involves fully contacting the remaining thin silicon film to suppress the increase of body potential, as described in [9].

Body-contacted (BC) SOI MOSFET structure
For the convenience of comparison, the chip with BS SOI MOSFET layout structure and the conventional PD SOI MOSFET chip are fabricated using the same process.Try to control the other parameters except the gate oxide thickness parameters, including the process.The voltage and current curves, BV dss , junction capacitance and circuit transmission speed are compared.Through the analysis of the results, the structure layout can reduce the barrier voltage, the junction capacitance is smaller, and the data transmission speed is slightly slower than the traditional structure [9,10].
Further benefits are offered by it construction with minimized floating body effect.This structure can reduce body contact, resulting in a lower drain breakdown voltage.When the junction capacitance of BC SOI device is Vp= 0. 5V, the junction voltage will drop suddenly, but this is caused by the oxide buried in the ground.The BC SOI CMOSFET propagates around 36% more quickly than the CMOSFET.

A Metal-Oriented Layout Structure
The metal layout structure are usually arranged horizontally with minimal spacing, and the diffusion lines are usually arranged perpendicular to the metal lines.In Figure 9, the junction of the two lines forms a new transistor, and these variables can be controlled by parallel polycrystalline silicon lines.Metal-oriented layout structures have a number of important advantages.This type of layout structure is well suited for the flat design of chips.An identical logic circuit can transform rows and columns according to the requirements of the chip substrate.Rule, shown in Figure 10 , for polysilicon wire C. The ability to align p-well areas in various logic modules is a wonderful feature, as shown in Figure 10.This layout structure makes the calibration easy to perform because the main wiring in the circuit is realized by metal wires.So you can swap rows and columns or replace some extended rows and columns without changing the logic function.And since the wires are always horizontally parallel, the whole layout can be stretched horizontally, adding new wires and new modules to achieve higher levels of interconnection in the circuit.In order to connect these modules, a metal wire is generally used to connect the next layer of the module.In this case, the metal-oriented layout can avoid the mix of metal bus structures caused by complex logic, because all internal modules can be implemented by minimal spacing of metal wires on both sides.The layout structure is suitable for industrial production, a CAD operator can design four transistors in a day, and the manufacturing time and efficiency of the metal-oriented layout design is almost the same as that of the standard cell method [11].

A cross-coupled transistor structure
The last structure is the cross-coupled transistor structure, which makes no gate drain overlap to form the interconnect capacitor through simple wiring, and minimizes the parasitic resistance generated during interconnect, allowing smaller drain parasitic.This structure helps CMOS-VCOs function better in the high frequency and broadband ranges [12].
Moreover, the parasitic resistance reduced by simple wiring compensates the gate resistance degradation to some extent.Chip components are shared, thus reducing the size of the internal structure of the chip.This arrangement also reduces the number of drains, resulting in a more streamlined interior [12,13].In Figure 11 and Figure 12, a common centroid transistor pair is used for the gate of transistors M1 and M2.Errors on the silicon wafer caused by process-induced gradients can be eliminated by this hardware-property symmetry.Figure 12.Conventional RF transistor layout.After that, the low-parasitic co-centered cross-coupled transistor junction designed by high-frequency VCO is compared with the traditional design, and the design characteristics of this structure are introduced in detail.The data measurement and comparison are carried out in three aspects: operating frequency, tuning range and phase noise.It is found that the above data of the proposed transistor have increased, and the performance advantage is stronger compared with the traditional structure.

Summary of comparison
The BC SOI MOSFET structure primarily involves the creation of a thin silicon layer between two oxide layers.The second structure mainly uses parallel metal wires to connect each module of the layout structure.The third structure mainly uses the cross-coupling technology, so that the gate drain is extremely overlapping to form the interconnect capacitance, and the parasitic resistance generated when interconnecting is minimal, and the drain parasitic is smaller.Each of the three structures has its own advantages and disadvantages.The first structure has lower process requirements and only needs an additional layer of silicon film, which is highly compatible with the traditional CMOS process.The second structure is metal-oriented layout structure, which uses parallel metal lines and parallel diffusion lines for vertical layout to connect different modules.The process is more complex, but it is more compatible with CMOS logic structure, and the row and column can be transformed, but the logic can remain unchanged.The third structure of cross-coupling transistor structure, through a reasonable layout, so that the gate drain overlap to form an interconnect capacitor, the parasitic resistance generated during interconnect is minimal, the drain parasitic is smaller.It can enhance the performance of CMOS voltage-controlled oscillators (VCOs) in the high frequency and broadband range, but the scale is large and the difficulty is greater.So to sum up, the first structure focuses more on the improvement of the process, and the improvement of the structure is small.The latter two are the internal wiring layout of the structure, and the other is the layout of the internal module of the structure, which involves a larger scale and higher requirements, and can improve the performance of the whole CMOS transistor as a whole.

Conclusion
In this paper, three important CMOS architectures are studied and found to be closely related to the performance of CMOS.The advantages and disadvantages of each architecture are discussed in detail.The advantages of each layout structure compared with the traditional structure are compared in several general directions such as transmission speed, VI characteristic curve, junction capacitance and so on.This field is very popular in the modern semiconductor industry.Due to the bottleneck in the size of the chip, engineers can only improve the performance of CMOS chips by optimizing the layout structure, so they optimize and improve the material, circuit connection and even reasonable space utilization.So there is no doubt that this field is very worthy of in-depth research and analysis, and it is widely used in this field, especially the application of cross-coupled transistor structure, in order to save chip space, the gate is shared.In addition, there are many other applications that use it in CMOS chips to improve the performance of semiconductors.The field will continue to be hot in the future, Moore's law has reached a bottleneck, the best way for engineers now is to start with the layout structure, readjust the space and logic circuit connections, use lower resistance materials, and improve the performance of the semiconductor.So the future is very promising.I will also continue to study this field and learn more relevant knowledge with an open mind.

Figure 3 .
Figure3.Carrier drift velocity and drift current density in the direction of applied electric field[8].Charge carriers migrate when an electric field is applied, which results in drift current.Electrons move in the opposite direction from positive charge carriers, which move in the same direction as the electric field (holes).The final drift current is created by the net motion of the charged carriers, which produces a current flowing in the same direction as the applied electric field.The carrier mobility μ is influenced by the drift velocity, which rises with the strength of the electric field.Charge carriers migrate from a high concentration to a low concentration to produce diffusion current.When the doping of the semiconductor is not uniform, the charge carriers will appear non-uniform distribution, which leads to the generation of concentration gradients.In this case, due to Brownian motion, the carriers will diffuse in order to reach equilibrium, and thus the diffusion current is generated, as shown in Figure3.In this process, there is no external electric field intervention, mainly because the charge carriers of the same charge are highly concentrated in a region, and the repulsive force between particles will be generated.The repulsive force will push the charge carriers to move, forming a diffusion, leading to a change in concentration until a uniform distribution is reached.The initial particle concentration determines the direction of the diffusion current.The current moves in the direction of high concentration to low hole concentration[8].Drift current means the current generated by the directional motion of particles under the action of external electric field, while diffusion current means the current generated by the migration of particles due to the concentration gradient.The drift current will predominate the total current density if a high electric field is provided.If there is no electric field present, the total current density will be dominated by the current produced by the carrier concentration gradient.

Figure 4 .
Figure 4. Cross section of p-channel enhancement-mode MOSFET.NMOS refers to the fabrication of two highly doped N+ regions (with a large number of free electrons in the N+ region) on a P-type silicon substrate (which can provide a large number of moving holes), in addition to the use of metal aluminum to induce two conductive electrodes, called drain D and source S. The drain-source insulator is covered with a thin layer of silicon dioxide (SiO2) insulation, and an aluminum electrode is then positioned on top of it.This aluminum electrode serves as the gate electrode G and connects to an electrode B on the substrate,as shown in Figure5.The transistors are N-channel enhanced MOS transistors.The source and substrate of MOS transistors are generally connected[8].

Figure 5 .Figure 6 .
Figure 5.The n-channel enhancement-mode MOSFET.In addition to the p-channel enhanced MOS transistors and n-channel enhanced MOS transistors introduced above, there are also p-channel consumption MOS transistors and n-channel consumption MOS transistors, but they are mainly divided into two categories, PMOS and NMOS.The following figure mainly depicts the symbols of PMOS and NMOS in the circuit diagram, as shown in Figure 6.

Figure 8 .
Figure 8.The Body-contacted (BC) SOI MOSFET structure.As in Figure8, BC-SOI MOSFET structure is a popular design that mitigates the floating body effect, and is fully compatible with standard MOSFETs, by preserving a thin silicon film between the field oxide and the oxide in the structure to prevent complete erosion by the field oxide.Improving the kink effect and BV_dss of the BC SOI MOSFET involves fully contacting the remaining thin silicon film to suppress the increase of body potential, as described in[9].For the convenience of comparison, the chip with BS SOI MOSFET layout structure and the conventional PD SOI MOSFET chip are fabricated using the same process.Try to control the other parameters except the gate oxide thickness parameters, including the process.The voltage and current curves, BV dss , junction capacitance and circuit transmission speed are compared.Through the analysis of the results, the structure layout can reduce the barrier voltage, the junction capacitance is smaller, and the data transmission speed is slightly slower than the traditional structure[9,10].Further benefits are offered by it construction with minimized floating body effect.This structure can reduce body contact, resulting in a lower drain breakdown voltage.When the junction capacitance of BC SOI device is Vp= 0. 5V, the junction voltage will drop suddenly, but this is caused by the oxide buried in the ground.The BC SOI CMOSFET propagates around 36% more quickly than the CMOSFET.

Figure 9 .
Figure 9. MOS transistor.Metal-oriented layout structures have a number of important advantages.This type of layout structure is well suited for the flat design of chips.An identical logic circuit can transform rows and columns according to the requirements of the chip substrate.Rule, shown in Figure10, for polysilicon wire C. The ability to align p-well areas in various logic modules is a wonderful feature, as shown in Figure10.This layout structure makes the calibration easy to perform because the main wiring in the circuit is realized by metal wires.So you can swap rows and columns or replace some extended rows and columns without changing the logic function.And since the wires are always horizontally parallel, the whole layout can be stretched horizontally, adding new wires and new modules to achieve higher levels of interconnection in the circuit.

Figure 10 .
Figure 10.Geometrical layout.In order to connect these modules, a metal wire is generally used to connect the next layer of the module.In this case, the metal-oriented layout can avoid the mix of metal bus structures caused by complex logic, because all internal modules can be implemented by minimal spacing of metal wires on both sides.The layout structure is suitable for industrial production, a CAD operator can design four transistors in a day, and the manufacturing time and efficiency of the metal-oriented layout design is almost the same as that of the standard cell method[11].

Figure 11 .
Figure 11.Cross-coupled transistor layout.Figure12.Conventional RF transistor layout.After that, the low-parasitic co-centered cross-coupled transistor junction designed by high-frequency VCO is compared with the traditional design, and the design characteristics of this structure are introduced in detail.The data measurement and comparison are carried out in three aspects: operating frequency, tuning range and phase noise.It is found that the above data of the proposed transistor have increased, and the performance advantage is stronger compared with the traditional structure.