The accuracy analysis of different algorithms for 4-Bit absolute value detector

This paper proposes and compares three different algorithms for implementing a 4-bit absolute value detector (AVD) using Complementary Metal Oxide Semiconductor (CMOS) technology. The demand for low power, low delay and high-performance drive the need for AVDs. The proposed algorithms are analysed based on logical effort theory and simulation results for delay and energy performance. The circuits employ a range of logical gates, including multiplexers, NAND gates, XNOR gates, XOR gates, and inverters. The chosen proposed algorithm achieves the lowest delay and energy cost while maintaining high accuracy. Sizing and Vdd optimization can be used to optimize energy, and a 53.7 FO4(1V), 39.91Eu(1V) 4-bit Absolute-Value Detector can be achieved. Overall, this paper provides valuable insights into the design and optimization of AVDs using CMOS technology, which can have important applications in developing electronic systems.


Introduction
Absolute value detectors (AVDs) are circuits that compare the magnitude of two signed inputs and output a binary signal indicating which one is larger.AVDs are useful for processing bio-signals such as neural spikes, electrocardiograms (ECGs), and electromyograms (EMGs), which can have positive or negative polarity depending on the electrode configuration [1].AVDs can also be used for envelope detection, peak detection, and signal conditioning applications.The need for AVDs today is driven by the demand for low-power, high-performance, and miniaturized biomedical systems that can monitor and diagnose various health conditions.AVDs are often required to operate with low supply voltages, low noise levels, high accuracy, and high speed.However, conventional designs of AVDs suffer from drawbacks such as high complexity, high power consumption, large area occupation, and poor scalability [2].
Therefore, new designs of AVDs that can overcome these challenges are needed.This paper proposes and compares three different algorithms for implementing a 4-bit AVD using CMOS technology.Their delay and energy performance are analyzed based on logical effort theory and simulation results.This paper show that the proposed algorithm achieves the lowest delay and energy cost among the three algorithms while maintaining high accuracy.

Principle of 4-bit absolute value detector
The 4-bit absolute value detector is a circuit designed to compare the absolute values of two inputs.The detector comprises two main components: the half adder and the comparator [3].The half adder is responsible for realizing the absolute value circuit and identifying positive values based on the symbol bit.Conversely, the comparator outputs 1 the specified threshold is less than the input signal and 0 otherwise.This detector already possesses all the functions of a general AVD and can be easily expanded to more complex AVDs [4].For example, the proposed detector takes a 4-bit binary digital signal input, ranging from -7 to 7.
The basic diagram for an absolute-value detector is shown in Figure 1 and there have mainly two parts of the circuit's algorithm: (1) The realization of the absolute value involves determining the sign of the input signal and performing two's complement calculations for negative values.
(2) The comparison of the magnitude with the threshold input, which outputs 1 when the magnitude is greater than T and 0 otherwise.

Absolute value converter
The absolute value converter is a circuit used to convert an input signal to an unsigned binary number, which is the absolute value of the signal.Firstly, the signal input is converted into an unsigned binary number to realize the absolute value detector mentioned in the paper.For positive input signals, the intermediate variable output A of magnitude extraction is the same as the input.For negative input signals, perform two's complement calculation to get the intermediate variable, the corresponding positive value A. The sign of the input signal is determined first, which can be determined according to the sign bit, A3, which is the most significant bit of A.

Comparator
The comparator is a circuit that makes a comparison of two signals and indicates whether one is greater by outputting a binary signal.In the 4-bit absolute value detector, the comparator outputs 1 if the input signal exceeds the threshold and 0 otherwise.The comparator uses a ripple carry adder for comparison, which outputs a low logic value when the threshold is less than the magnitude of the input signal and a high logic value otherwise.

Key parameters of AVD
Using the theory of logic effort, many key parameters can be calculated [6].The trade-off between circuit speed and power consumption is very important for modern VLSI design.The calculation of delay and energy is useful for optimizing the circuit [7].
Overall logical effort can be calculated as shown in formula (1): As shown in Table 1, logic effort (g) will be used to calculate the formula (1).Path electrical effort can be calculated using the formula ( 2): Path branch effort can be calculated using the formula (3): Path effort can be calculated using the formula (4): Best stage effort can be calculated using the formula (5): Path parasitic delay can be calculated using the formula (6): Minimum path delay can be calculated using the formula (7): The size of gates can be calculated using the formula (8): The total energy can be calculated using the formula (9):

Circuit analysis
The input value is given in the complement format of 2, which ranges from -7 to +7.The magnitude of a positive number is the same as the number itself, while the negative number is found by flipping all bits and adding one.The magnitude is always 3 bits, compared to a given 3-bit threshold value in a comparator.The relationship of A0-A3 and A0'-A2' are shown in Formula (10) and Table 2.
1 0 1 0 0 0 In the comparator section, compare the output terminals A0'-A2' of the absolute value section with the threshold voltages B0-B2.The relationship of A0'-A2' and the output value F are shown in Formula (11).

Circuit A
Circuit A, shown in Figure 2, employs multiplexers, NAND gates, XNOR gates, XOR gates, and inverters.While the circuit is relatively concise, it utilizes a diverse range of logical gates.

Figure 2.
Circuit of A. The critical path is the longest path in a circuit and limits the clock speed.The path violates the timing the most and usually has the longest delay.The information from the critical path can be used to optimize the design of CMOS circuits and improve their performance and yield.The critical path of A is shown in Figure 3. (12) Path electrical effort can be calculated using the formula ( 13): Path branch effort can be calculated using the formula ( 14): Path effort can be calculated using the formula (15): Best stage effort can be calculated using the formula (16): Path parasitic delay can be calculated using the formula (17): Minimum path delay can be calculated using the formula (18): The Cin is shown in Table 3 below, which can be calculated using the formula (8).Table 3 4, only employs NAND gates, XOR gates, and inverters.This circuit uses fewer logic gates and is relatively simple to build.Path electrical effort can be calculated using the formula (21): Path branch effort can be calculated using the formula (22): Path effort can be calculated using the formula (23): Best stage effort can be calculated using the formula (24): Path parasitic delay can be calculated using the formula (25): Minimum path delay can be calculated using the formula (26):   (28) Path electrical effort can be calculated using the formula (29): Path branch effort can be calculated using the formula (30): Path effort can be calculated using the formula (31): Best stage effort can be calculated using the formula (32): Path parasitic delay can be calculated using the formula (33): Minimum path delay can be calculated using the formula (34): The Cin is shown in Table 5 below.

Comparison of circuits
This paper, the author proposed three different algorithms to implement a 4-bit absolute value detector.These three algorithms are based on the multiplexer, only-gates, and transmission gates.Although these three algorithms are used for implementing a detector, they have different delay and energy, which are shown in Table 6.Table 6.The Delay and Energy of Circuits.

Figure 3 .
Figure 3. Critical path of A. Using the formula in 2.4, the key parameters can be shown: Overall logical effort can be calculated using the formula (12):

Figure 4 .
Figure 4. Circuit of B. The critical path of B is shown in Figure 5.

Figure 5 .
Figure 5. Critical path of B. Using the formula in 2.4, the key parameters can be shown: Overall logical effort can be calculated using the formula (20):

Figure 6 .
Figure 6. Circuit of C. The critical path of C is shown in Figure 7.

Figure 7 .
Figure 7. Critical path of C.Using the formula in 2.4, the key parameters can be shown: Overall logical effort can be calculated using the formula (28): Table 6, circuit B has the lowest delay and circuit C has the lowest energy cost.The advantages and disadvantages of these three algorithms are as follows: Comparator-based algorithm: Pros: Simple implementation, low circuit complexity.Cons: Slow speed, high power consumption.Adder-based algorithm: Pros: Fast speed, low power consumption.Cons: High circuit complexity.Multiplexer-based algorithm: Pros: Fast speed, low circuit complexity.Cons: High power consumption.
From 3.4, circuit B can be chosen as the final circuit.Although circuit B has the minimum delay, the size and Vdd can be changed to optimize the energy.Figure8shows the relation of delay with sizing and Vdd.

Figure 8 .
Figure 8. Relation of delay with sizing and vdd.

Table 2 .
Truth table of the absolute value converter.

Table 4 .
The Cin is shown in Table4below.Each Cin. Circuit C, shown in Figure6, uses transmission gates to filter signals and employs NAND gates, NOR gates, XOR gates and inverters.