Design of preamplifier circuit for ECG circuit of wearable devices

In this study, a wearable electrocardiogram (ECG) acquisition system with high performance instrumentation amplifier is presented. It adopts a 3-op-amp circuit and utilizes 180nm CMOS technology to achieve large input impedance. Furthermore, a drive-right leg module is used to configure the input’s common-mode range, increasing the common-mode rejection rate. Simulations in standard 180nm CMOS technology show bandwidths ranging from 0.1Hz to 251Hz. The front-end circuit operates on a 0.8V power supply. At the same time, using LTspice to conduct a preliminary test on the performance of the circuit, the total integrated input-referred noise of the circuit is 3.98 µVRMS , and the power consumption is 5.059 µ W . This satisfies the need for an ECG circuit with low power and noise requirements for wearable technology. The preliminary research findings presented in this paper have established a solid theoretical framework for the amplifier used in the measuring of ECG signals.


Introduction
The World Health Organization (WHO) reports that cardiovascular diseases (CVDs) are the main cause of death globally, taking an estimated 17.9 million lives each year.A third of these fatalities occur before the age of 70.In this case, Electrocardiography technology is particularly important [1].Electrocardiography (ECG) is a vital technique in the medical field for monitoring and diagnosing various cardiac abnormalities.With the advent of wearable technology, continuous and real-time ECG monitoring has become possible, enabling healthcare professionals to gain valuable insights into a patient's cardiac health outside the clinical setting [2].The preamplifier circuit is a critical component of the ECG circuit in wearable devices, as it amplifies the low-amplitude ECG signals while minimizing noise and interference.In the present research a preamplifier circuit was designed and optimized for a wearable ECG device, taking into account variables including power consumption, gain, and noise reduction [3].
Several studies have explored different techniques and architectures for designing ECG preamplifier circuits.The most common approach is to use an instrumentation amplifier as the primary amplification stage, followed by additional filtering and amplification stages as needed [4].
This paper designs an OTA ECG amplifier composed of MOSFETs and capacitors and applies the designed amplifier to the circuit design.This project aims to develop an amplifier circuit suitable for

Method
Considering the very weak characteristics of the human body's ECG signal, the preamplification circuit of the ECG circuit designed in this paper will include two stages.That is, the first and second stages, respectively, are the fully differential input buffer and the differential with the single-ended amplifier.In the first stage, the differential signal is amplified to a specific level.In the second stage, the signal is filtered by two coupling capacitors while also being amplified once more.This work used the simulation program LTspice.

Operational transconductance amplifier (OTA)
As mentioned earlier, the ECG signal is weak.Therefore, factors such as low noise, high CMRR, high input impedance should be considered when selecting an amplifier.CMOS OTA has the characteristics of small size, low power consumption, low input reference noise, good common-mode rejection ratio, and high input impedance [5].In line with the higher precision and stability requirements of the circuit.In this paper, a simulation model of a 180nm CMOS OTA is used, as shown in figure 1.

Electrode and human body circuit
To simulate the electrode in actual use, the author used a 1MΩ resistor in parallel with a 50nF capacitor and then connected in series with a 2kΩ resistor which is shown in figure 2 [6].As shown in figure 3, the power supply V3 is used as the ECG signal generator, its voltage is 0.1mV, and its frequency is 10Hz.To mimic the body's low-frequency noise, the current generator generates 0.01μA of current at a frequency of 60 Hz.The circuit also uses resistors to simulate interference from electrodes on each end of the body.It uses three 200Ω resistors to simulate the resistance between the ends of the body.4, which is a fully differential input buffer with dual input and dual output composed of two OTAs.Its purpose is to amplify the differential signal and reduce the common-mode gain as much as possible.The target gain for this phase is determined by the following formula: Figure 5. Differential to Single-ended Amplifier.Substituting the resistance values of each resistor in figure 4 into the formula for calculation, it can be obtained that the amplification factor of the first stage is 50V/V.

Second stage.
The second stage is synthesizing and amplifying the first two signals.Its circuit is shown in figure 5, and the calculation formula is as follows.Similarly, by substituting the data in Figure 5 into the formula, it can be calculated that the Gain of the second stage is 2V/V.So in this paper, the gain of the 3 OP-AMP circuit is 100V/V, which is 40dB. (2)

Filter circuit
Despite the fact that stage one does not amplify the common-mode signal, it persists and must be separated from other common-mode signals by coupling capacitors [7].The common-mode impulses are erased by the coupling capacitors, but they also have another function.The electrode offset voltage (EOV), the OTA will become overloaded if there is a discrepancy in the direct current offset voltage between the two electrodes.[8].Together with a feedback resistor and a feedback capacitor, the coupling capacitors in this case produce a high-pass filter to block the EOV and other noise, such as 1/f noise and thermal noise.In figure 5, the high-pass portion of the circuit is shown (the circuit inside the circle).According to the characteristics of the ECG signal, the cut-off frequency of the high-pass filter is selected as 0.1Hz.The high-pass frequency of the filter is determined by equation (3), that is, the resistor and capacitor values determine the frequency.
When the -3dB cut-off frequency is 0.1Hz, the capacitance value determined by the second stage is 26.5pF.Substituting the two values, it can be calculated that a resistor of 60GΩ is required.
ECG signals are generally weak in character, ie their amplitude does not exceed mV.In actual use, the input and output are usually mixed with a large number of high-frequency interference signals.Therefore, a low-pass filter is needed to remove part of the interfering signal.In addition, since the ECG signal is a low-frequency signal, its energy is mainly lower than a few hundred hertz, so the cut-off frequency of our low-frequency signal is determined to be 250Hz.A low pass filter is integrated with OTA.The low-pass circuit is shown in figure 6. Figure 7. PMOS Test Circuit.

Pseudo resistor
According to the previous calculation, the required resistance value of the high-pass filter is 60GΩ.In addition to taking up a lot of room in wearable technology, such resistors also produce a significant amount of parasitic distributed capacitance, which reduces the frequency response and increases noise as the frequency rises.So it is a good choice for this project to use PMOS transistors to make pseudo resistors instead of super-high-value resistors [9].In this article, the author uses LTspice to perform DC sweep on 180nm PMOS, and the circuit is shown in figure 7. The resistance value of PMOS is simulated by formula (4), and the result is shown in figure 8.

Driven-right-leg circuit
The patient can be connected directly to the amplifier through the right-leg drive circuit to reduce the unexpected amount of common-mode interference that the human body can cause [10].Figure 10 is depicted.To further counteract common-mode interference, An inverting amplifier is used to collect the common-mode voltage from the human body, reverse its phase by 180 degrees, and then send it back to the common-mode spot on the body [7].

Requirements
During the design and simulation of the ECG sensor circuit, parameters such as bandwidth, differential gain, CMRR, total integrated input-referred noise, NEF, and power consumption were considered to ensure the ECG sensor's overall performance.As was already said, all computed and simulated values must fall within the desired range in order to fulfill the aim and construct a low-power, low-noise ECG amplifier circuit.

Differential gain and bandwidth
To determine the analog frequency range and differential mode gain of the designed circuit, the author used LTspice to perform an AC sweep from 1mHz to 1 MHz and obtained the simulation results in figure 11.As shown, the maximum differential mode gain is 38.7 dB.Also, the cutoff frequency is defined as a frequency at which the gain is 3 dB below the maximum gain, in this case, the cutoff frequency is approximately 35.7 dB.At this time, the frequency range is 0.1-251 Hz, and this result is within an acceptable range of error.

CMRR
The ratio of the differential-mode gain to the common-mode gain is known as the common-mode rejection ratio (CMRR) of an op-amp [11].By simulating designed circuit, it can be obtained that the differential mode gain is 38.7dB and the common mode gain is -82.8 dB.Calculated by formula (5), the CMRR of the circuit can be obtained to be about 121.5 dB.

Noise
The noise of the circuit design should be as low as possible for optimal circuit performance.To achieve this, we lowered the value of the resistors and set the OTA current of the two stages to less than 10nA.
As depicted in figure 12, the noise increases exponentially with frequency until it reaches its maximum level.After that, sounds would start to get smaller until they eventually became 0. Through noise simulation results, the total RMS noise of the circuit is 343.31μV.Then the total integrated inputreferred noise (INR) is given by equation (6).
The total RMS noise modelled across overall gain, which is approximately 86.1V/V, is used to determine the INR indicated in this equation.Therefore, the INR of this circuit should be 3.98µ  .3.5.NEF Equation ( 7) yields the noise efficiency factor (NEF), where VT is the thermal voltage, kB is Boltzmann's constant, T is the temperature,   is the total current drawn by the amplifier, BW is its bandwidth, and  , is its input-referred noise.So, the NEF is calculated as 5.08.

Power consumption
The power consumption rose along with the current.So, reducing the voltage of the power supply was the main method for reducing power dissipation.The standard for circuit design is that the combined power usage of all blocks is less than 5µW, by using LTspice, total power used by the circuit can be calculated to be 5.059µW which is shown in figure 13.

Discussion
Table 1 illustrates the differences between the circuit's actual design and our criteria.It can be seen from it that, except that the power consumption is 0.059 μw more than the design requirement, it shows that the circuit in this article is compliant with the specifications for the ECG circuit.The CMRR of the circuit can be greatly increased, and the noise of the circuit can be reduced, by utilizing a 3-op-amp amplifier circuit with high impedance.Moreover, after considering the weak characteristics of the human body's ECG signal, environmental noise will have an impact on the wearable ECG device's functioning.[12] In order to reduce noise, balance signal and environmental noise, and lessen the impact of clutter beyond the ECG signal's frequency range on the outcome, this work employs high-pass and low-pass filters.This procedure aids in reducing equipment noise while preventing the addition of further noise and improve the accuracy of the measurement results.However, due to the limitation of experimental conditions, this paper only designs the preamplifier circuit of the ECG circuit and simulates it based on LTspice.However, in the actual use of the circuit, due to the influence of the device manufacturing process and other unconsidered factors, there may be errors with the simulation results, which should be considered and improved in future research.The total amount of employed capacitance < 1nF 0.619nF

Conclusion
In conclusion, the design in this paper is quite successful in terms of noise reduction, accuracy, and size.By using LTspice simulation, the performance of the circuit is tested, and its portability is proved.The overall performance is in line with the purpose of this work, which is to design a wearable ECG sensor.Low power consumption, and low noise These are the key factors for using ECG circuits in wearables.This design enables us to better implant ECG circuits into wearable items such as watches, rings, bracelets, etc., to help patients with cardiovascular diseases monitor their physical conditions in realtime.In the follow-up research, it should be considered to continue to reduce the overall power consumption and noise of the circuit.At the same time, for ECG circuits suitable for wearable devices, digital backends for ECG signal acquisition, such as ADCs or Bluetooth modules, should also be considered in future research.It is hoped that this project will play an enlightening and guiding role in the follow-up research on ECG circuits for wearable devices so that more accurate and long-term ECG devices can be widely used by patients with cardiovascular diseases and help them monitor their physical condition, to provide medical guidance, and save the lives of more patients.

Figure 2 .
Figure 2. Electrode.As shown in figure3, the power supply V3 is used as the ECG signal generator, its voltage is 0.1mV, and its frequency is 10Hz.To mimic the body's low-frequency noise, the current generator generates

2. 3 .
3-op-amp circuit 2.3.1.First stage.The circuit of the first stage is shown in figure

Figure 4 .
Figure 4. Fully Differential Input Buffer.Figure5.Differential to Single-ended Amplifier.Substituting the resistance values of each resistor in figure4into the formula for calculation, it can be obtained that the amplification factor of the first stage is 50V/V.

Figure 8 .
Figure 8. PMOS Test Result.When L=180n and W=700n, it can be concluded from the simulation results that when Vgs=0.5V, the resistance of PMOS is about 10GΩ.Therefore, six PMOS transistors are connected in series to obtain the required resistance value of 60GΩ.figure 9 depicts the pseudo-resistor's structural layout.

Table 1 .
Comparison of requirements and simulation results.