Design of electronic clock and stopwatch based on FPGA and VHDL language

This paper designs a simple system that can include electronic clock and stopwatch based on FPGA(Field Programmable Gate Array) and VHDL(Very-High-Speed Integrated Circuit Hardware Description Language). The first chapter briefly introduces the research background. The second chapter introduces the theoretical basis of digital circuits and the hardware and software platform used in this paper. In the third chapter, the design of each sub-module of the system and the overall design of the system are carried out. This chapter is the core chapter of this article, which describes the functions of the module and explains the input and output ports. In this chapter, a core point of digital circuit design is reflected: combining modules that realize simple functions into modules that can realize complex functions. And integrate sub-modules that realize similar functions into a top-level module. The fourth chapter is the logic synthesis of the circuit. The fourth chapter shows the simulation of the core module function and the simulation of the system output. The conclusion section summarizes the interesting parts of the design of this paper.


Introduction
Since FPGAs(Field Programmable Gate Array) first appeared, their flexibility has been widely favoured by developers.FPGA is now widely used as a chip verification tool to test the logic function and reliability of the chip.As the simplest entry-level tool for digital circuits, this paper uses FPGA as the hardware platform and Vivado as the software platform to design a simple system that integrates electronic stopwatch and electronic clock functions.The second chapter introduces the theoretical basis needed for this paper.Binary signals are generally used in digital circuits, and each digit has only two values of 0 and 1, so as long as the circuit can correctly distinguish two different states, a certain deviation is allowed.For the specific functions realized, the design of the system sub-modules is completed and the functions and ports to be realized by the sub-modules are explained in detail.The innovative design of some modules can save hardware overhead.Specifically, it is to achieve as many functions as possible with as few modules as possible.The alarm is set by directly changing the state of the counter instead of using a separate register to set the alarm.Then, the fourth chapter conducts a simple simulation of the important modules and the functions of the system.The correctness of the functions of the sub-modules and the correctness of the interconnection of the sub-modules of the system are verified.Finally, the highlights and design deficiencies of this paper are summarized.

Digital circuit
Binary signals are generally used in digital circuits, and each digit has only two values of 0 and 1, so as long as the circuit can correctly distinguish two different states, a certain deviation is allowed [1].This greatly reduces the requirements for circuit manufacturing accuracy, working conditions and operating environment.In order to improve the accuracy of the signal, it can be solved by increasing the number of bits in the binary number.Relatively speaking, analogy circuits are much stricter than digital circuits in terms of manufacturing accuracy, working conditions, and operating environment requirements.Therefore, the first integrated circuits made were digital integrated circuits.So far, most large-scale and very large-scale integrated circuits are digital integrated circuits.

FPGA & VHDL
The EDA(Electronic design automation) tools used in PLD (Programmable Logic Device) programming include hardware and software.The hardware part consists of computer and programmer.First, the design must be entered into the computer.Therefore, people have developed hardware description languages and corresponding compilers for describing circuits.In addition, there must be programming software that can adapt to the selected device in order to complete the generation and writing of programming data.
FPGA (Field Programmable Gate Array) is a programmable device based on LUT (lookup table) structure using SRAM(Static Random-Access Memory) technology, which is lost when power off.FPGA typically used in data-intensive systems and the wiring delay is not fixed.In 1985, the XC2064, the world's first FPGA product launched by Xilinx, looked like an "ugly duckling" -using a 2μm process, containing 64 logic modules and 85,000 transistors, and the number of gates did not exceed 1,000.According to Ross Freeman, one of the founders of Xilinx and the inventor of the FPGA, for many applications, flexibility and customizability are attractive features if implemented properly.When Xilinx launched its third-generation FPGA product, the XC4000 series, in 1991, people began to seriously consider programmable technology [2].Perhaps since then, the shift to the latest semiconductor processes has been inexorable.
The VHDL(VHSIC Hardware Description Language) is a HDL(hardware description language) that can model the behaviour and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes.VHDL is named after the United States Department of Defence program that created it, the Very High-Speed Integrated Circuits Program (VHSIC).In the early 1980s, the VHSIC Program sought a new HDL for use in the design of the integrated circuits it aimed to develop [3].The product of this effort was VHDL Version 7.2, released in 1985.The effort to standardize it as an IEEE standard began in the following year.

Function of the system
The whole system basically realizes the function of a clock and a stopwatch.In clock mode, the digital tube displays the data of hours, minutes and seconds and counts in a 24-hour cycle.The alarm clock can be set by adding or subtracting, and the corresponding display digital tube flashes when setting.When the alarm goes off, you can temporarily turn off the alarm and wait ten minutes before the alarm goes off again, or turn off the alarm permanently.In stopwatch mode, the digital tube displays the data of minutes, seconds and milliseconds.Three data can be temporarily stored during the running of the stopwatch, and can be viewed in sequence after the stopwatch stops running.
In the clock mode, the frequency divider divides the frequency of the system clock signal to obtain signals of different frequencies for use by each module.The 1Hz signal is sent to the counter as a counting signal, and the 1kHz signal is sent to the scanning display module for dynamic display by the digital tube.The counter completes the counting of hours, minutes, and seconds and has the correct carry logic relationship, and the output is the BCD code of hours, minutes, and seconds.The output data selector will select the data from the counter and the data from the storage module, and will send different data to the display module in different modes.The display module realizes the dynamic display of the digital tube.That is, only one digital tube is lit in one clock cycle.When the frequency is high, the human eye cannot tell whether the digital tubes are lit at the same time or sequentially.When setting the alarm clock, the system needs to first judge whether it is in the setting mode.In the setting mode, the pulse signal input by the button will be debounced and sent directly to the counter as a count, indicating that it counts once.At this moment, the 1Hz counting signal of the frequency divider should be set inactive [4].After the alarm clock is set, the set time will be saved to the storage module.When the alarm clock is turned on, the current time and the time saved by the storage module will be judged.If the two data are equal, the alarm clock will work.There will be a signal indicating whether the alarm goes off.When the alarm clock sounds, send a piece of music signal to the buzzer and enter the waiting state.You can choose to snooze the alarm temporarily or turn it off permanently.If the alarm clock is temporarily stopped, the memory will add 10 to the minutes of the current clock data and save it, waiting for the next alarm clock to sound.If you choose to turn off the alarm clock permanently, the enable terminal of the alarm clock will be set to invalid.
In the stopwatch mode, the frequency divider divides the system clock frequency and sends the 100Hz signal to the counter as a counting signal.The counter will output the BCD code of minutes, seconds and milliseconds.After counting is started, the stopwatch data can be stored up to three times in the memory module.If stored multiple times, the previously stored data will be overwritten.This function of the memory is performed by a shift register.The storage signal pulse is sent to the memory module as a storage enable signal.After the stopwatch stops counting, you can check the data stored in the shift register in sequence.Both the data of the memory and the data of the counter will be sent to the output data selection module [5].Under different working conditions, the module will select different data for display.
The block of the system is shown in Figure 1.
Figure 1.Block of the design system.

Modules of the system
Group circuits containing similar functions into the same block.The system can basically be divided into 11 main modules, including frequency division module -generating clock signal for each module, Key debounce module, control module -generating control signal for each module, counter module, memory module, alarm judge module, output data selector, display module and buzzer driver.

Control module.
The control module will generate the control signals of each module according to the input and the current working state of the circuit to ensure that the functions and timing of each module are correct.Parts of the ports are as shown in Tables 1-2.Set(2:0) Setting terminal, the second can be set when the lowest bit is '1', the minute can be set when the second lowest bit is '1', and the hour can be set when the highest bit is '1'.
alarm in Feedback the alarm signal to the control module for judging other conditions.When the alarm is in progress, this port will input '1' for the control module, and input '0' for other times.
alarm out Connected to the output of the debounce module, to allow the alarm clock signal, when it is '1', it means that the alarm clock is on, and when it is '0', it means that the alarm clock is off.
add Add the value of the counter when setting the clock.

confirm in
The alarm clock confirmation signal after debounce, there will be a pulse when the alarm clock is confirmed.en tik out When the stopwatch mode enable signal is valid, this port will make the stopwatch enter the enabled and valid working state, otherwise the enable will be invalid.In the stopwatch mode, the 100Hz signal is sent to the stopwatch counter.

Table 2. (continued). clk out
The clock terminal of the clock mode.When the clock is working normally, the 1Hz signal will be sent to the clock counter.In the adjustment time mode, the pulse signal sent for addition and subtraction adjustment will be delayed by 20 as the clock terminal and sent to the counter.
in set If it is '1', it means that the clock is in the alarm setting state at this time.
en alarm Allow alarm signal, when in clock mode.

dp mode
The signal is sent to the decimal point control circuit as a judgment of whether the decimal point is displayed data sel mode The signal is sent to the display selection circuit to judge the number to be displayed.

latch en clk
Allows the latch signal, when the enable terminal is '0' in the clock mode, it allows the data at this time to be stored in the latch as an alarm clock.latch en tik The latch signal is allowed.When the enable terminal is '1' in the stopwatch mode, the data at this time can be stored in the latch as the reading of the count.addsub In the normal working mode of the clock, it is always '0'; in the setting mode, when the plus pulse arrives, the output will be '0' and will remain until the next plus or minus pulse arrives, and the output will be '1' when the minus pulse arrives and it will be kept until the next addition and subtraction pulse arrives.en wait The signal that allows to wait for ten minutes, that is, when the clock mode is working normally, the alarm clock will sound, and the signal will be set to '1' at this time, that is, it is allowed to wait at this time, and the key pulse input at this stage will set the alarm clock to 10 minutes later and on time.confirm out Confirming signal output terminal, when the clock mode is disabled, the confirm signal is valid, and confirm out will have a pulse.

Counter module.
This module is the core module of the whole system, which realizes the counting of clock and stopwatch.The clock counter consists of two modulo 60 counters and one modulo 24 counter.The stopwatch counter consists of a modulo 100 counter and two modulo 60 counters.The clock counter works in clock mode.The stopwatch counter works in stopwatch mode.
When the alarm clock is set, the 1Hz signal input to the clock counter will be shielded, and the counting pulses will be sent to the clock counter instead.The enable port and clear port on the clock are provided by the control module.The ports are as shown in Tables 3-4.Table 3. Input ports of counter module.En(2:0) Asynchronous enable signal, high enable is effective, the enable terminal is "001" during normal operation, which bit is set when setting, then the enable terminal of that bit will be '1', for example, the enable terminal is "001" when adjusting the division 010" in set Indicates that the counter is in the setting mode at this time.The adjustment of the counter output in the setting mode will not affect the counting of the next bit, that is, this signal will shield the cascade signal between the three counters, so that each counter in the counting mode Counters work independently of each other.addsub Synchronous addition and subtraction signal, when the rising edge of the clock arrives, the signal is '0' for counting up, and the signal is '0' for counting down.

Table 4. Output ports of counter module. port function count
The count output is 24 bits BCD code, the upper 8 bits are hours, the middle 8 bits are minutes, and the lower 8 bits are seconds.en out Carry/borrow terminal, in up-counting mode, when the count output is 6'H235959 and the enable is valid, it is '1'

Buzzer driver.
This module is a buzzer driver module.Its function is to use a pre-set audio signal to drive the buzzer when an alarm signal is received.Make the alarm signal sound more pleasant.This is an innovative place in this article for boring FPGA design.The music to be played is a fragment from the first movement of Dvořák's Cello Concerto No. 1 in B minor.After finding the score of the piece, first determine the timing of the rhythm and notes.What we have to do is to send the note signals to the buzzer in sequence according to the actual order of the notes [6].The notes needed for this piece can be approximately get by the frequency divider.The music clip is shown in Figure 2.  5-6.
Table 5. Input ports of buzzer driver.

port function alarm out
When the bit is '1', it means that the alarm clock is on at this time, and it is connected to the alarm judgment module.tempo The beat signal of the music output.The music output segment is a segment of Dvořák's Cello Concerto in B minor.The rhythm of this segment is 100, and the time value of an eighth note can be determined to correspond to a period of a 3.33Hz signal.duration.f Note #f, the corresponding frequency is 185.00Hz.g Note #g, the corresponding frequency is 207.63Hz.b Note b, the corresponding frequency is 246.94Hz.c1 Note #c1, the corresponding frequency is 277.18Hz.d1 Note #d1, the corresponding frequency is 311.13Hz.e1 Note #e1, the corresponding frequency is 329.63Hz.f1 Note #f1, corresponding frequency is 369.99Hz.g 1 Note g1, the corresponding frequency is 392Hz.g1 Note #g1, the corresponding frequency is 415.30Hz.a1 Note #a1, the corresponding frequency is 466.16Hz.b1 Note b1, the corresponding frequency is 493.88Hz.c2 Note #c2, the corresponding frequency is 554.37Hz.d2 Note #d2, the corresponding frequency is 622.25Hz.f2 Note #f2, corresponding frequency is 739.99Hz.The output terminal will use tempo as a counting module, add a data selector, and select the following frequency sequence in sequence according to the rhythm.

Top-level module synthesis
After synthesis, the overall structural framework of the Top-level module built in this paper is shown in the Figure 3.The ports are as shown in Tables 7-8.
Table 7. Input ports of top-level module.

port function clk50MHz
Connect to the 50MHz crystal oscillator module that comes with the development board, and divide the frequency of the signal to get the frequency signal we need.mode Select stopwatch mode and clock mode, mode is '1' for stopwatch mode, mode is '0' for clock mode.en Asynchronous enable work, when en is 1, the device works, when en is 0, the device suspends work.rst Asynchronous clear terminal, when rst is 1, the register status of the stored module and the counting module will be cleared.set hour When it is '1', hours adjustment is allowed.set minute When it is '1', minutes adjustment is allowed.set second When it is '1', second adjustment is allowed.en alarm The status of the alarm clock switch, when it is '1', the alarm clock is on, and when it is '0', the alarm clock is off.

Confirm
Alarm clock setting confirmation switch, after pressing it, the time at this time will be locked into the latch as the alarm clock time.latch in In stopwatch mode, when the rising edge of the signal arrives, the current data will be latched into the latch, and a total of three data can be latched; in clock mode, if the alarm is ringing at this time, when the rising edge of the signal arrives will turn off the alarm and make the alarm go off in 10 minutes.add When adjusting the time, minute, and second, press the next time to add one to the data.sub When adjusting the time, minute and second, press the next time to reduce the data by one.switch In the stopwatch mode, the temporarily stored data will be displayed.Pressing the switch will display the latched numbers sequentially.It can be seen from the figure that the counting logic is correct, the carry logic is correct, and the state of the enable signal is correct.When the clock counter counts to 235959, the counting state is 000000 when the next clock rising edge arrives.So basically we can assume that the counter is working fine [8].
All outputs of the system in the normal working state of the clock mode are shown in Figure 5.

Figure 5.
The result of the system output simulation.From the simulation, we can see the output signals of three digital tubes: sclk, rclk and dio can work normally.Because this simulation is aimed at system-level guidelines, this simulation mainly checks whether the interconnection relationship of each sub-module is correct in the process of hierarchical design.The output submodules have been verified to function correctly when the submodules were designed [9].Therefore, generally only a certain port is periodically output, we will think that the sub-modules are connected correctly.The simulation of individual modules is not listed here again due to the cumbersome workload.
When the buzzer is working, the output music signal is shown in Figure 6.
Figure 6.Simulation of the output of the buzzer.From the simulation, we can see that there is a significant difference in the signal frequency before and after.This indicates that the buzzer is "playing" a different note.But there is a noteworthy design flaw here, that is, when each note signal is played, it will always start from a high level [10].This also means that transitions between notes are not very natural.The sudden change in the phase of the note signal will cause a certain setback in the sense of the human ear.Make music sound less harmonious.

Conclusion
In this paper, the FPGA development board is used as the hardware platform, and the Vivado software is used as the software platform.A simple system that can simultaneously run an electronic stopwatch and an electronic clock is built.Its functions are often used in daily life.There are two biggest innovations in this paper.The first is that when setting the clock, the state of the counter can be directly changed through the key pulse.This greatly saves hardware overhead.At the same time, a key technical problem of the setting of addition and subtraction is solved.The same pulse will be sent to the counter as the addition and subtraction judgment signal and counting clock signal.There needs to be a small delay between these two signals.That is, the remaining judgment signals should be prepared in advance before the rising edge of the clock arrives.The second is to design an audio signal as the driver of the buzzer.Because the system crystal oscillator can only generate square wave signals but not sine wave signals.So, we can only produce a "not perfect" audio.So far, the boring FPGA has been played with new tricks based on the knowledge of the second-year undergraduate.
Due to the characteristics of FPGA -data loss when power loss, developers will generally not use FPGA to develop systems that need to implement specific functions.Due to the flexibility of FPGA, FPGA is currently mainly used as a verification tool for special-purpose chips and general-purpose chips.At present, the main force in the fields of deep learning and AI algorithms is GPU-its powerful computing power provides a good platform for deep learning.However, as a general-purpose graphics processing chip, GPU is far less flexible than FPGA.In the future, FPGA will also play a huge role in similar fields such as AI acceleration and accelerated algorithms.

Figure 2 .
Figure 2. Music clip.The ports are as shown in Tables5-6.Table5.Input ports of buzzer driver.

Figure 3 .
Figure 3.The input and output ports of the top module.
capabilities for system-on-chip development and high-level synthesis.Launched in April 2012, it is an integrated development environment (IDE) with system-to-IC level tools built on a shared scalable data model and common debug environment.Vivado includes Electronic System Level (ESL) design tools for synthesis and verification of C-based algorithmic IP cores; standards-based algorithmic and RTL IP packages for reuse; standards-based IP stitching and system integration of all types of system components; and verification of blocks and systems.It includes the built-in logic simulator ISIM.Vivado also introduces high-level synthesis, a toolchain that converts C code into programmable logic.Xilinx replaced the 15-year-old ISE software with the Vivado Design Suite, costing 1,000 man-years and $200 million[7].4.2.2.Simulation results.The simulation results of the counter obtained under the normal operation of the clock mode are shown in Figure 4.

Figure 4 .
Figure 4. Counter simulation results.It can be seen from the figure that the counting logic is correct, the carry logic is correct, and the state of the enable signal is correct.When the clock counter counts to 235959, the counting state is 000000 when the next clock rising edge arrives.So basically we can assume that the counter is working fine[8].All outputs of the system in the normal working state of the clock mode are shown in Figure5.

Table 1 .
Input ports of control module.
clk1MHzInternal delay signal.For some outputs, we hope that the rising edge will come later.This clock signal is used as the counting signal of the delayer.modeStopwatch/clock mode selection terminal.enCounter enable signal.

Table 2 .
Output ports of control module.According to the mode, the three counters of the clock module are selected to be enabled and judged.When the clock mode is not in the time adjustment state, the lowest bit counter is enabled and valid, and the lowest bit is enabled in the second adjustment state.It can be valid, the next low-order enable is valid in the minute adjustment state, and the highest-order enable is effective in the time adjustment state.

Table 6 .
Output ports of buzzer driver.

Table 8 .
Output ports of top-level module.Vivado Design Suite (also known as Xilinx Vivado or Vivado) is a software suite developed by Xilinx for the synthesis and analysis of HDL designs, with additional